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Created February 27, 2018 14:50
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ficr.diff
--- ficr-before.rs 2018-02-27 15:45:28.375958754 +0100
+++ ficr-after.rs 2018-02-27 15:44:11.041326001 +0100
@@ -1,413 +1,2311 @@
#[doc = "Factory Information Configuration Registers"]
pub struct FICR {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for FICR {}
impl FICR {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const ficr::RegisterBlock {
0x1000_0000 as *const _
}
}
impl Deref for FICR {
type Target = ficr::RegisterBlock;
fn deref(&self) -> &ficr::RegisterBlock {
unsafe { &*FICR::ptr() }
}
}
#[doc = "Factory Information Configuration Registers"]
pub mod ficr {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 16usize],
#[doc = "0x10 - Code memory page size"]
pub codepagesize: CODEPAGESIZE,
#[doc = "0x14 - Code memory size"]
pub codesize: CODESIZE,
_reserved1: [u8; 72usize],
#[doc = "0x60 - Description collection[0]: Device identifier"]
pub deviceid: [DEVICEID; 2],
_reserved2: [u8; 24usize],
#[doc = "0x80 - Description collection[0]: Encryption Root, word 0"]
pub er: [ER; 4],
#[doc = "0x90 - Description collection[0]: Identity Root, word 0"]
pub ir: [IR; 4],
#[doc = "0xa0 - Device address type"]
pub deviceaddrtype: DEVICEADDRTYPE,
#[doc = "0xa4 - Description collection[0]: Device address 0"]
pub deviceaddr: [DEVICEADDR; 2],
+ _reserved3: [u8; 84usize],
+ #[doc = "0x100 - Device info"]
+ pub info: INFO,
+ _reserved4: [u8; 768usize],
+ #[doc = "0x404 - Registers storing factory TEMP module linearization coefficients"]
+ pub temp: TEMP,
+ _reserved5: [u8; 72usize],
+ #[doc = "0x450 - Unspecified"]
+ pub nfc: NFC,
+ }
+ #[doc = r" Register block"]
+ #[repr(C)]
+ pub struct INFO {
+ #[doc = "0x00 - Part code"]
+ pub part: self::info::PART,
+ #[doc = "0x04 - Part Variant, Hardware version and Production configuration"]
+ pub variant: self::info::VARIANT,
+ #[doc = "0x08 - Package option"]
+ pub package: self::info::PACKAGE,
+ #[doc = "0x0c - RAM variant"]
+ pub ram: self::info::RAM,
+ #[doc = "0x10 - Flash variant"]
+ pub flash: self::info::FLASH,
+ #[doc = "0x14 - Description collection[0]: Unspecified"]
+ pub unused0: [self::info::UNUSED0; 3],
+ }
+ #[doc = r" Register block"]
+ #[doc = "Device info"]
+ pub mod info {
+ #[allow(unused_imports)]
+ use vcell::VolatileCell;
+ #[doc = "Part code"]
+ pub struct PART {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Part code"]
+ pub mod part {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::PART {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = "Possible values of the field `PART`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum PARTR {
+ #[doc = "nRF52832"]
+ N52832,
+ #[doc = "Unspecified"]
+ UNSPECIFIED,
+ #[doc = r" Reserved"]
+ _Reserved(u32),
+ }
+ impl PARTR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ match *self {
+ PARTR::N52832 => 0x0005_2832,
+ PARTR::UNSPECIFIED => 0xffff_ffff,
+ PARTR::_Reserved(bits) => bits,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline]
+ pub fn _from(value: u32) -> PARTR {
+ match value {
+ 337970 => PARTR::N52832,
+ 4294967295 => PARTR::UNSPECIFIED,
+ i => PARTR::_Reserved(i),
+ }
+ }
+ #[doc = "Checks if the value of the field is `N52832`"]
+ #[inline]
+ pub fn is_n52832(&self) -> bool {
+ *self == PARTR::N52832
+ }
+ #[doc = "Checks if the value of the field is `UNSPECIFIED`"]
+ #[inline]
+ pub fn is_unspecified(&self) -> bool {
+ *self == PARTR::UNSPECIFIED
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:31 - Part code"]
+ #[inline]
+ pub fn part(&self) -> PARTR {
+ PARTR::_from({
+ const MASK: u32 = 0xffff_ffff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u32
+ })
+ }
+ }
+ }
+ #[doc = "Part Variant, Hardware version and Production configuration"]
+ pub struct VARIANT {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Part Variant, Hardware version and Production configuration"]
+ pub mod variant {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::VARIANT {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = "Possible values of the field `VARIANT`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum VARIANTR {
+ #[doc = "AAAA"]
+ AAAA,
+ #[doc = "AAAB"]
+ AAAB,
+ #[doc = "AABA"]
+ AABA,
+ #[doc = "AABB"]
+ AABB,
+ #[doc = "AAB0"]
+ AAB0,
+ #[doc = "SPA0"]
+ SPA0,
+ #[doc = "Unspecified"]
+ UNSPECIFIED,
+ #[doc = r" Reserved"]
+ _Reserved(u32),
+ }
+ impl VARIANTR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ match *self {
+ VARIANTR::AAAA => 0x4141_4141,
+ VARIANTR::AAAB => 0x4141_4142,
+ VARIANTR::AABA => 0x4141_4241,
+ VARIANTR::AABB => 0x4141_4242,
+ VARIANTR::AAB0 => 0x4141_4230,
+ VARIANTR::SPA0 => 0x5350_4130,
+ VARIANTR::UNSPECIFIED => 0xffff_ffff,
+ VARIANTR::_Reserved(bits) => bits,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline]
+ pub fn _from(value: u32) -> VARIANTR {
+ match value {
+ 1094795585 => VARIANTR::AAAA,
+ 1094795586 => VARIANTR::AAAB,
+ 1094795841 => VARIANTR::AABA,
+ 1094795842 => VARIANTR::AABB,
+ 1094795824 => VARIANTR::AAB0,
+ 1397768496 => VARIANTR::SPA0,
+ 4294967295 => VARIANTR::UNSPECIFIED,
+ i => VARIANTR::_Reserved(i),
+ }
+ }
+ #[doc = "Checks if the value of the field is `AAAA`"]
+ #[inline]
+ pub fn is_aaaa(&self) -> bool {
+ *self == VARIANTR::AAAA
+ }
+ #[doc = "Checks if the value of the field is `AAAB`"]
+ #[inline]
+ pub fn is_aaab(&self) -> bool {
+ *self == VARIANTR::AAAB
+ }
+ #[doc = "Checks if the value of the field is `AABA`"]
+ #[inline]
+ pub fn is_aaba(&self) -> bool {
+ *self == VARIANTR::AABA
+ }
+ #[doc = "Checks if the value of the field is `AABB`"]
+ #[inline]
+ pub fn is_aabb(&self) -> bool {
+ *self == VARIANTR::AABB
+ }
+ #[doc = "Checks if the value of the field is `AAB0`"]
+ #[inline]
+ pub fn is_aab0(&self) -> bool {
+ *self == VARIANTR::AAB0
+ }
+ #[doc = "Checks if the value of the field is `SPA0`"]
+ #[inline]
+ pub fn is_spa0(&self) -> bool {
+ *self == VARIANTR::SPA0
+ }
+ #[doc = "Checks if the value of the field is `UNSPECIFIED`"]
+ #[inline]
+ pub fn is_unspecified(&self) -> bool {
+ *self == VARIANTR::UNSPECIFIED
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ # [ doc = "Bits 0:31 - Part Variant, Hardware version and Production configuration, encoded as ASCII" ] # [ inline ]
+ pub fn variant(&self) -> VARIANTR {
+ VARIANTR::_from({
+ const MASK: u32 = 0xffff_ffff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u32
+ })
+ }
+ }
+ }
+ #[doc = "Package option"]
+ pub struct PACKAGE {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Package option"]
+ pub mod package {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::PACKAGE {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = "Possible values of the field `PACKAGE`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum PACKAGER {
+ #[doc = "QFxx - 48-pin QFN"]
+ QF,
+ #[doc = "CHxx - 7x8 WLCSP 56 balls"]
+ CH,
+ #[doc = "CIxx - 7x8 WLCSP 56 balls"]
+ CI,
+ #[doc = "Unspecified"]
+ UNSPECIFIED,
+ #[doc = r" Reserved"]
+ _Reserved(u32),
+ }
+ impl PACKAGER {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ match *self {
+ PACKAGER::QF => 0x2000,
+ PACKAGER::CH => 0x2001,
+ PACKAGER::CI => 0x2002,
+ PACKAGER::UNSPECIFIED => 0xffff_ffff,
+ PACKAGER::_Reserved(bits) => bits,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline]
+ pub fn _from(value: u32) -> PACKAGER {
+ match value {
+ 8192 => PACKAGER::QF,
+ 8193 => PACKAGER::CH,
+ 8194 => PACKAGER::CI,
+ 4294967295 => PACKAGER::UNSPECIFIED,
+ i => PACKAGER::_Reserved(i),
+ }
+ }
+ #[doc = "Checks if the value of the field is `QF`"]
+ #[inline]
+ pub fn is_qf(&self) -> bool {
+ *self == PACKAGER::QF
+ }
+ #[doc = "Checks if the value of the field is `CH`"]
+ #[inline]
+ pub fn is_ch(&self) -> bool {
+ *self == PACKAGER::CH
+ }
+ #[doc = "Checks if the value of the field is `CI`"]
+ #[inline]
+ pub fn is_ci(&self) -> bool {
+ *self == PACKAGER::CI
+ }
+ #[doc = "Checks if the value of the field is `UNSPECIFIED`"]
+ #[inline]
+ pub fn is_unspecified(&self) -> bool {
+ *self == PACKAGER::UNSPECIFIED
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:31 - Package option"]
+ #[inline]
+ pub fn package(&self) -> PACKAGER {
+ PACKAGER::_from({
+ const MASK: u32 = 0xffff_ffff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u32
+ })
+ }
+ }
+ }
+ #[doc = "RAM variant"]
+ pub struct RAM {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "RAM variant"]
+ pub mod ram {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::RAM {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = "Possible values of the field `RAM`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum RAMR {
+ #[doc = "16 kByte RAM"]
+ K16,
+ #[doc = "32 kByte RAM"]
+ K32,
+ #[doc = "64 kByte RAM"]
+ K64,
+ #[doc = "Unspecified"]
+ UNSPECIFIED,
+ #[doc = r" Reserved"]
+ _Reserved(u32),
+ }
+ impl RAMR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ match *self {
+ RAMR::K16 => 0x10,
+ RAMR::K32 => 0x20,
+ RAMR::K64 => 0x40,
+ RAMR::UNSPECIFIED => 0xffff_ffff,
+ RAMR::_Reserved(bits) => bits,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline]
+ pub fn _from(value: u32) -> RAMR {
+ match value {
+ 16 => RAMR::K16,
+ 32 => RAMR::K32,
+ 64 => RAMR::K64,
+ 4294967295 => RAMR::UNSPECIFIED,
+ i => RAMR::_Reserved(i),
+ }
+ }
+ #[doc = "Checks if the value of the field is `K16`"]
+ #[inline]
+ pub fn is_k16(&self) -> bool {
+ *self == RAMR::K16
+ }
+ #[doc = "Checks if the value of the field is `K32`"]
+ #[inline]
+ pub fn is_k32(&self) -> bool {
+ *self == RAMR::K32
+ }
+ #[doc = "Checks if the value of the field is `K64`"]
+ #[inline]
+ pub fn is_k64(&self) -> bool {
+ *self == RAMR::K64
+ }
+ #[doc = "Checks if the value of the field is `UNSPECIFIED`"]
+ #[inline]
+ pub fn is_unspecified(&self) -> bool {
+ *self == RAMR::UNSPECIFIED
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:31 - RAM variant"]
+ #[inline]
+ pub fn ram(&self) -> RAMR {
+ RAMR::_from({
+ const MASK: u32 = 0xffff_ffff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u32
+ })
+ }
+ }
+ }
+ #[doc = "Flash variant"]
+ pub struct FLASH {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Flash variant"]
+ pub mod flash {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::FLASH {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = "Possible values of the field `FLASH`"]
+ #[derive(Clone, Copy, Debug, PartialEq)]
+ pub enum FLASHR {
+ #[doc = "128 kByte FLASH"]
+ K128,
+ #[doc = "256 kByte FLASH"]
+ K256,
+ #[doc = "512 kByte FLASH"]
+ K512,
+ #[doc = "Unspecified"]
+ UNSPECIFIED,
+ #[doc = r" Reserved"]
+ _Reserved(u32),
+ }
+ impl FLASHR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ match *self {
+ FLASHR::K128 => 0x80,
+ FLASHR::K256 => 0x0100,
+ FLASHR::K512 => 0x0200,
+ FLASHR::UNSPECIFIED => 0xffff_ffff,
+ FLASHR::_Reserved(bits) => bits,
+ }
+ }
+ #[allow(missing_docs)]
+ #[doc(hidden)]
+ #[inline]
+ pub fn _from(value: u32) -> FLASHR {
+ match value {
+ 128 => FLASHR::K128,
+ 256 => FLASHR::K256,
+ 512 => FLASHR::K512,
+ 4294967295 => FLASHR::UNSPECIFIED,
+ i => FLASHR::_Reserved(i),
+ }
+ }
+ #[doc = "Checks if the value of the field is `K128`"]
+ #[inline]
+ pub fn is_k128(&self) -> bool {
+ *self == FLASHR::K128
+ }
+ #[doc = "Checks if the value of the field is `K256`"]
+ #[inline]
+ pub fn is_k256(&self) -> bool {
+ *self == FLASHR::K256
+ }
+ #[doc = "Checks if the value of the field is `K512`"]
+ #[inline]
+ pub fn is_k512(&self) -> bool {
+ *self == FLASHR::K512
+ }
+ #[doc = "Checks if the value of the field is `UNSPECIFIED`"]
+ #[inline]
+ pub fn is_unspecified(&self) -> bool {
+ *self == FLASHR::UNSPECIFIED
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:31 - Flash variant"]
+ #[inline]
+ pub fn flash(&self) -> FLASHR {
+ FLASHR::_from({
+ const MASK: u32 = 0xffff_ffff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u32
+ })
+ }
+ }
+ }
+ #[doc = "Description collection[0]: Unspecified"]
+ pub struct UNUSED0 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Description collection[0]: Unspecified"]
+ pub mod unused0 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ #[doc = r" Value to write to the register"]
+ pub struct W {
+ bits: u32,
+ }
+ impl super::UNUSED0 {
+ #[doc = r" Modifies the contents of the register"]
+ #[inline]
+ pub fn modify<F>(&self, f: F)
+ where
+ for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+ {
+ let bits = self.register.get();
+ let r = R { bits: bits };
+ let mut w = W { bits: bits };
+ f(&r, &mut w);
+ self.register.set(w.bits);
+ }
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ #[doc = r" Writes to the register"]
+ #[inline]
+ pub fn write<F>(&self, f: F)
+ where
+ F: FnOnce(&mut W) -> &mut W,
+ {
+ let mut w = W::reset_value();
+ f(&mut w);
+ self.register.set(w.bits);
+ }
+ #[doc = r" Writes the reset value to the register"]
+ #[inline]
+ pub fn reset(&self) {
+ self.write(|w| w)
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ }
+ impl W {
+ #[doc = r" Reset value of the register"]
+ #[inline]
+ pub fn reset_value() -> W {
+ W { bits: 0 }
+ }
+ #[doc = r" Writes raw bits to the register"]
+ #[inline]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.bits = bits;
+ self
+ }
+ }
+ }
+ }
+ #[doc = r" Register block"]
+ #[repr(C)]
+ pub struct TEMP {
+ #[doc = "0x00 - Slope definition A0."]
+ pub a0: self::temp::A0,
+ #[doc = "0x04 - Slope definition A1."]
+ pub a1: self::temp::A1,
+ #[doc = "0x08 - Slope definition A2."]
+ pub a2: self::temp::A2,
+ #[doc = "0x0c - Slope definition A3."]
+ pub a3: self::temp::A3,
+ #[doc = "0x10 - Slope definition A4."]
+ pub a4: self::temp::A4,
+ #[doc = "0x14 - Slope definition A5."]
+ pub a5: self::temp::A5,
+ #[doc = "0x18 - y-intercept B0."]
+ pub b0: self::temp::B0,
+ #[doc = "0x1c - y-intercept B1."]
+ pub b1: self::temp::B1,
+ #[doc = "0x20 - y-intercept B2."]
+ pub b2: self::temp::B2,
+ #[doc = "0x24 - y-intercept B3."]
+ pub b3: self::temp::B3,
+ #[doc = "0x28 - y-intercept B4."]
+ pub b4: self::temp::B4,
+ #[doc = "0x2c - y-intercept B5."]
+ pub b5: self::temp::B5,
+ #[doc = "0x30 - Segment end T0."]
+ pub t0: self::temp::T0,
+ #[doc = "0x34 - Segment end T1."]
+ pub t1: self::temp::T1,
+ #[doc = "0x38 - Segment end T2."]
+ pub t2: self::temp::T2,
+ #[doc = "0x3c - Segment end T3."]
+ pub t3: self::temp::T3,
+ #[doc = "0x40 - Segment end T4."]
+ pub t4: self::temp::T4,
+ }
+ #[doc = r" Register block"]
+ #[doc = "Registers storing factory TEMP module linearization coefficients"]
+ pub mod temp {
+ #[allow(unused_imports)]
+ use vcell::VolatileCell;
+ #[doc = "Slope definition A0."]
+ pub struct A0 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Slope definition A0."]
+ pub mod a0 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::A0 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct AR {
+ bits: u16,
+ }
+ impl AR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:11 - A (slope definition) register."]
+ #[inline]
+ pub fn a(&self) -> AR {
+ let bits = {
+ const MASK: u16 = 0x0fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ AR { bits }
+ }
+ }
+ }
+ #[doc = "Slope definition A1."]
+ pub struct A1 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Slope definition A1."]
+ pub mod a1 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::A1 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct AR {
+ bits: u16,
+ }
+ impl AR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:11 - A (slope definition) register."]
+ #[inline]
+ pub fn a(&self) -> AR {
+ let bits = {
+ const MASK: u16 = 0x0fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ AR { bits }
+ }
+ }
+ }
+ #[doc = "Slope definition A2."]
+ pub struct A2 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Slope definition A2."]
+ pub mod a2 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::A2 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct AR {
+ bits: u16,
+ }
+ impl AR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:11 - A (slope definition) register."]
+ #[inline]
+ pub fn a(&self) -> AR {
+ let bits = {
+ const MASK: u16 = 0x0fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ AR { bits }
+ }
+ }
+ }
+ #[doc = "Slope definition A3."]
+ pub struct A3 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Slope definition A3."]
+ pub mod a3 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::A3 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct AR {
+ bits: u16,
+ }
+ impl AR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:11 - A (slope definition) register."]
+ #[inline]
+ pub fn a(&self) -> AR {
+ let bits = {
+ const MASK: u16 = 0x0fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ AR { bits }
+ }
+ }
+ }
+ #[doc = "Slope definition A4."]
+ pub struct A4 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Slope definition A4."]
+ pub mod a4 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::A4 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct AR {
+ bits: u16,
+ }
+ impl AR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:11 - A (slope definition) register."]
+ #[inline]
+ pub fn a(&self) -> AR {
+ let bits = {
+ const MASK: u16 = 0x0fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ AR { bits }
+ }
+ }
+ }
+ #[doc = "Slope definition A5."]
+ pub struct A5 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Slope definition A5."]
+ pub mod a5 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::A5 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct AR {
+ bits: u16,
+ }
+ impl AR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:11 - A (slope definition) register."]
+ #[inline]
+ pub fn a(&self) -> AR {
+ let bits = {
+ const MASK: u16 = 0x0fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ AR { bits }
+ }
+ }
+ }
+ #[doc = "y-intercept B0."]
+ pub struct B0 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "y-intercept B0."]
+ pub mod b0 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::B0 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct BR {
+ bits: u16,
+ }
+ impl BR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:13 - B (y-intercept)"]
+ #[inline]
+ pub fn b(&self) -> BR {
+ let bits = {
+ const MASK: u16 = 0x3fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ BR { bits }
+ }
+ }
+ }
+ #[doc = "y-intercept B1."]
+ pub struct B1 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "y-intercept B1."]
+ pub mod b1 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::B1 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct BR {
+ bits: u16,
+ }
+ impl BR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:13 - B (y-intercept)"]
+ #[inline]
+ pub fn b(&self) -> BR {
+ let bits = {
+ const MASK: u16 = 0x3fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ BR { bits }
+ }
+ }
+ }
+ #[doc = "y-intercept B2."]
+ pub struct B2 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "y-intercept B2."]
+ pub mod b2 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::B2 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct BR {
+ bits: u16,
+ }
+ impl BR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:13 - B (y-intercept)"]
+ #[inline]
+ pub fn b(&self) -> BR {
+ let bits = {
+ const MASK: u16 = 0x3fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ BR { bits }
+ }
+ }
+ }
+ #[doc = "y-intercept B3."]
+ pub struct B3 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "y-intercept B3."]
+ pub mod b3 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::B3 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct BR {
+ bits: u16,
+ }
+ impl BR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:13 - B (y-intercept)"]
+ #[inline]
+ pub fn b(&self) -> BR {
+ let bits = {
+ const MASK: u16 = 0x3fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ BR { bits }
+ }
+ }
+ }
+ #[doc = "y-intercept B4."]
+ pub struct B4 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "y-intercept B4."]
+ pub mod b4 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::B4 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct BR {
+ bits: u16,
+ }
+ impl BR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:13 - B (y-intercept)"]
+ #[inline]
+ pub fn b(&self) -> BR {
+ let bits = {
+ const MASK: u16 = 0x3fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ BR { bits }
+ }
+ }
+ }
+ #[doc = "y-intercept B5."]
+ pub struct B5 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "y-intercept B5."]
+ pub mod b5 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::B5 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct BR {
+ bits: u16,
+ }
+ impl BR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u16 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:13 - B (y-intercept)"]
+ #[inline]
+ pub fn b(&self) -> BR {
+ let bits = {
+ const MASK: u16 = 0x3fff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u16
+ };
+ BR { bits }
+ }
+ }
+ }
+ #[doc = "Segment end T0."]
+ pub struct T0 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Segment end T0."]
+ pub mod t0 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::T0 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct TR {
+ bits: u8,
+ }
+ impl TR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - T (segment end)register."]
+ #[inline]
+ pub fn t(&self) -> TR {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ TR { bits }
+ }
+ }
+ }
+ #[doc = "Segment end T1."]
+ pub struct T1 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Segment end T1."]
+ pub mod t1 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::T1 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct TR {
+ bits: u8,
+ }
+ impl TR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - T (segment end)register."]
+ #[inline]
+ pub fn t(&self) -> TR {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ TR { bits }
+ }
+ }
+ }
+ #[doc = "Segment end T2."]
+ pub struct T2 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Segment end T2."]
+ pub mod t2 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::T2 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct TR {
+ bits: u8,
+ }
+ impl TR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - T (segment end)register."]
+ #[inline]
+ pub fn t(&self) -> TR {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ TR { bits }
+ }
+ }
+ }
+ #[doc = "Segment end T3."]
+ pub struct T3 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Segment end T3."]
+ pub mod t3 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::T3 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct TR {
+ bits: u8,
+ }
+ impl TR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - T (segment end)register."]
+ #[inline]
+ pub fn t(&self) -> TR {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ TR { bits }
+ }
+ }
+ }
+ #[doc = "Segment end T4."]
+ pub struct T4 {
+ register: VolatileCell<u32>,
+ }
+ #[doc = "Segment end T4."]
+ pub mod t4 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::T4 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct TR {
+ bits: u8,
+ }
+ impl TR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - T (segment end)register."]
+ #[inline]
+ pub fn t(&self) -> TR {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ TR { bits }
+ }
+ }
+ }
+ }
+ #[doc = r" Register block"]
+ #[repr(C)]
+ pub struct NFC { # [ doc = "0x00 - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ] pub tagheader0 : self::nfc::TAGHEADER0 , # [ doc = "0x04 - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ] pub tagheader1 : self::nfc::TAGHEADER1 , # [ doc = "0x08 - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ] pub tagheader2 : self::nfc::TAGHEADER2 , # [ doc = "0x0c - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ] pub tagheader3 : self::nfc::TAGHEADER3 , }
+ #[doc = r" Register block"]
+ #[doc = "Unspecified"]
+ pub mod nfc {
+ #[allow(unused_imports)]
+ use vcell::VolatileCell;
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub struct TAGHEADER0 {
+ register: VolatileCell<u32>,
+ }
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub mod tagheader0 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::TAGHEADER0 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct MFGIDR {
+ bits: u8,
+ }
+ impl MFGIDR {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD1R {
+ bits: u8,
+ }
+ impl UD1R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD2R {
+ bits: u8,
+ }
+ impl UD2R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD3R {
+ bits: u8,
+ }
+ impl UD3R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F"]
+ #[inline]
+ pub fn mfgid(&self) -> MFGIDR {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ MFGIDR { bits }
+ }
+ #[doc = "Bits 8:15 - Unique identifier byte 1"]
+ #[inline]
+ pub fn ud1(&self) -> UD1R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 8;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD1R { bits }
+ }
+ #[doc = "Bits 16:23 - Unique identifier byte 2"]
+ #[inline]
+ pub fn ud2(&self) -> UD2R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 16;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD2R { bits }
+ }
+ #[doc = "Bits 24:31 - Unique identifier byte 3"]
+ #[inline]
+ pub fn ud3(&self) -> UD3R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 24;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD3R { bits }
+ }
+ }
+ }
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub struct TAGHEADER1 {
+ register: VolatileCell<u32>,
+ }
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub mod tagheader1 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::TAGHEADER1 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD4R {
+ bits: u8,
+ }
+ impl UD4R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD5R {
+ bits: u8,
+ }
+ impl UD5R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD6R {
+ bits: u8,
+ }
+ impl UD6R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD7R {
+ bits: u8,
+ }
+ impl UD7R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - Unique identifier byte 4"]
+ #[inline]
+ pub fn ud4(&self) -> UD4R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD4R { bits }
+ }
+ #[doc = "Bits 8:15 - Unique identifier byte 5"]
+ #[inline]
+ pub fn ud5(&self) -> UD5R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 8;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD5R { bits }
+ }
+ #[doc = "Bits 16:23 - Unique identifier byte 6"]
+ #[inline]
+ pub fn ud6(&self) -> UD6R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 16;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD6R { bits }
+ }
+ #[doc = "Bits 24:31 - Unique identifier byte 7"]
+ #[inline]
+ pub fn ud7(&self) -> UD7R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 24;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD7R { bits }
+ }
+ }
+ }
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub struct TAGHEADER2 {
+ register: VolatileCell<u32>,
+ }
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub mod tagheader2 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::TAGHEADER2 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD8R {
+ bits: u8,
+ }
+ impl UD8R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD9R {
+ bits: u8,
+ }
+ impl UD9R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD10R {
+ bits: u8,
+ }
+ impl UD10R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD11R {
+ bits: u8,
+ }
+ impl UD11R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - Unique identifier byte 8"]
+ #[inline]
+ pub fn ud8(&self) -> UD8R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD8R { bits }
+ }
+ #[doc = "Bits 8:15 - Unique identifier byte 9"]
+ #[inline]
+ pub fn ud9(&self) -> UD9R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 8;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD9R { bits }
+ }
+ #[doc = "Bits 16:23 - Unique identifier byte 10"]
+ #[inline]
+ pub fn ud10(&self) -> UD10R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 16;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD10R { bits }
+ }
+ #[doc = "Bits 24:31 - Unique identifier byte 11"]
+ #[inline]
+ pub fn ud11(&self) -> UD11R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 24;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD11R { bits }
+ }
+ }
+ }
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub struct TAGHEADER3 {
+ register: VolatileCell<u32>,
+ }
+ # [ doc = "Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." ]
+ pub mod tagheader3 {
+ #[doc = r" Value read from the register"]
+ pub struct R {
+ bits: u32,
+ }
+ impl super::TAGHEADER3 {
+ #[doc = r" Reads the contents of the register"]
+ #[inline]
+ pub fn read(&self) -> R {
+ R {
+ bits: self.register.get(),
+ }
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD12R {
+ bits: u8,
+ }
+ impl UD12R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD13R {
+ bits: u8,
+ }
+ impl UD13R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD14R {
+ bits: u8,
+ }
+ impl UD14R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ #[doc = r" Value of the field"]
+ pub struct UD15R {
+ bits: u8,
+ }
+ impl UD15R {
+ #[doc = r" Value of the field as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u8 {
+ self.bits
+ }
+ }
+ impl R {
+ #[doc = r" Value of the register as raw bits"]
+ #[inline]
+ pub fn bits(&self) -> u32 {
+ self.bits
+ }
+ #[doc = "Bits 0:7 - Unique identifier byte 12"]
+ #[inline]
+ pub fn ud12(&self) -> UD12R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 0;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD12R { bits }
+ }
+ #[doc = "Bits 8:15 - Unique identifier byte 13"]
+ #[inline]
+ pub fn ud13(&self) -> UD13R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 8;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD13R { bits }
+ }
+ #[doc = "Bits 16:23 - Unique identifier byte 14"]
+ #[inline]
+ pub fn ud14(&self) -> UD14R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 16;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD14R { bits }
+ }
+ #[doc = "Bits 24:31 - Unique identifier byte 15"]
+ #[inline]
+ pub fn ud15(&self) -> UD15R {
+ let bits = {
+ const MASK: u8 = 0xff;
+ const OFFSET: u8 = 24;
+ ((self.bits >> OFFSET) & MASK as u32) as u8
+ };
+ UD15R { bits }
+ }
+ }
+ }
}
#[doc = "Code memory page size"]
pub struct CODEPAGESIZE {
register: VolatileCell<u32>,
}
#[doc = "Code memory page size"]
pub mod codepagesize {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CODEPAGESIZE {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct CODEPAGESIZER {
bits: u32,
}
impl CODEPAGESIZER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Code memory page size"]
#[inline]
pub fn codepagesize(&self) -> CODEPAGESIZER {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
CODEPAGESIZER { bits }
}
}
}
#[doc = "Code memory size"]
pub struct CODESIZE {
register: VolatileCell<u32>,
}
#[doc = "Code memory size"]
pub mod codesize {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CODESIZE {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct CODESIZER {
bits: u32,
}
impl CODESIZER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Code memory size in number of pages"]
#[inline]
pub fn codesize(&self) -> CODESIZER {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
CODESIZER { bits }
}
}
}
#[doc = "Description collection[0]: Device identifier"]
pub struct DEVICEID {
register: VolatileCell<u32>,
}
#[doc = "Description collection[0]: Device identifier"]
pub mod deviceid {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DEVICEID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DEVICEIDR {
bits: u32,
}
impl DEVICEIDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - 64 bit unique device identifier"]
#[inline]
pub fn deviceid(&self) -> DEVICEIDR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
DEVICEIDR { bits }
}
}
}
#[doc = "Description collection[0]: Encryption Root, word 0"]
pub struct ER {
register: VolatileCell<u32>,
}
#[doc = "Description collection[0]: Encryption Root, word 0"]
pub mod er {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::ER {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct ERR {
bits: u32,
}
impl ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Encryption Root, word n"]
#[inline]
pub fn er(&self) -> ERR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
ERR { bits }
}
}
}
#[doc = "Description collection[0]: Identity Root, word 0"]
pub struct IR {
register: VolatileCell<u32>,
}
#[doc = "Description collection[0]: Identity Root, word 0"]
pub mod ir {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::IR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct IRR {
bits: u32,
}
impl IRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Identity Root, word n"]
#[inline]
pub fn ir(&self) -> IRR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
IRR { bits }
}
}
}
#[doc = "Device address type"]
pub struct DEVICEADDRTYPE {
register: VolatileCell<u32>,
}
#[doc = "Device address type"]
pub mod deviceaddrtype {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DEVICEADDRTYPE {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `DEVICEADDRTYPE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DEVICEADDRTYPER {
#[doc = "Public address"]
PUBLIC,
#[doc = "Random address"]
RANDOM,
}
impl DEVICEADDRTYPER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DEVICEADDRTYPER::PUBLIC => false,
DEVICEADDRTYPER::RANDOM => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DEVICEADDRTYPER {
match value {
false => DEVICEADDRTYPER::PUBLIC,
true => DEVICEADDRTYPER::RANDOM,
}
}
#[doc = "Checks if the value of the field is `PUBLIC`"]
#[inline]
pub fn is_public(&self) -> bool {
*self == DEVICEADDRTYPER::PUBLIC
}
#[doc = "Checks if the value of the field is `RANDOM`"]
#[inline]
pub fn is_random(&self) -> bool {
*self == DEVICEADDRTYPER::RANDOM
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Device address type"]
#[inline]
pub fn deviceaddrtype(&self) -> DEVICEADDRTYPER {
DEVICEADDRTYPER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "Description collection[0]: Device address 0"]
pub struct DEVICEADDR {
register: VolatileCell<u32>,
}
#[doc = "Description collection[0]: Device address 0"]
pub mod deviceaddr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DEVICEADDR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DEVICEADDRR {
bits: u32,
}
impl DEVICEADDRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - 48 bit device address"]
#[inline]
pub fn deviceaddr(&self) -> DEVICEADDRR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
DEVICEADDRR { bits }
}
}
}
}
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