gistfile1.txt

From 7ccec3b4d5a31defba6aee3e06bc1c1eae84c2a4 Mon Sep 17 00:00:00 2001
From: Janne Grunau <j@jannau.net>
Date: Tue, 31 May 2022 23:13:52 +0200
Subject: [PATCH 1/1] mailbox: apple: Add optional CPU control register

Required for starting/booting DCP after m1n1.

Signed-off-by: Janne Grunau <j@jannau.net>
---
 drivers/mailbox/apple-mailbox.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mailbox/apple-mailbox.c b/drivers/mailbox/apple-mailbox.c
index 43ee75219380..fca62ac57d1d 100644
--- a/drivers/mailbox/apple-mailbox.c
+++ b/drivers/mailbox/apple-mailbox.c
@@ -29,6 +29,9 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#define APPLE_ASC_CPU_CONTROL       0x44
+#define APPLE_ASC_CPU_CONTROL_START 0x10
+
 #define APPLE_ASC_MBOX_CONTROL_FULL  BIT(16)
 #define APPLE_ASC_MBOX_CONTROL_EMPTY BIT(17)
 
@@ -93,6 +96,7 @@ struct apple_mbox_hw {
 
 struct apple_mbox {
        void __iomem *regs;
+       void __iomem *cpu_regs;
        const struct apple_mbox_hw *hw;
 
        int irq_recv_not_empty;
@@ -368,6 +372,17 @@ static int apple_mbox_probe(struct platform_device *pdev)
        if (IS_ERR(mbox->regs))
                return PTR_ERR(mbox->regs);
 
+       mbox->cpu_regs = devm_platform_ioremap_resource_byname(pdev, "cpu");
+       if (!IS_ERR(mbox->cpu_regs)) {
+               u32 cpu_ctrl;
+               dev_info(&pdev->dev, "cpu_regs for CPU start");
+               cpu_ctrl = readl_relaxed(mbox->cpu_regs + APPLE_ASC_CPU_CONTROL);
+               writel_relaxed(cpu_ctrl | APPLE_ASC_CPU_CONTROL_START, mbox->cpu_regs + APPLE_ASC_CPU_CONTROL);
+               udelay(10);
+               cpu_ctrl = readl_relaxed(mbox->cpu_regs + APPLE_ASC_CPU_CONTROL);
+               writel_relaxed(cpu_ctrl & ~APPLE_ASC_CPU_CONTROL_START, mbox->cpu_regs + APPLE_ASC_CPU_CONTROL);
+       }
+
        mbox->hw = match->data;
        mbox->irq_recv_not_empty =
                platform_get_irq_byname(pdev, "recv-not-empty");
-- 
2.35.1