Skip to content

Instantly share code, notes, and snippets.

@jannau

jannau/gist:b52d60842f99a0b7d9d3d38a1bca263c Secret

Created November 21, 2021 22:25
Show Gist options
  • Save jannau/b52d60842f99a0b7d9d3d38a1bca263c to your computer and use it in GitHub Desktop.
Save jannau/b52d60842f99a0b7d9d3d38a1bca263c to your computer and use it in GitHub Desktop.
Download ZIP
t8103 pmgr hv SError
Raw
gistfile1.txt
Copying SEPFW (0x704000 bytes)...
Copying TrustCache (0x60000 bytes)...
Adjusting addresses in ADT...
Setting up bootargs at 0x81b858000...
Setting secondary CPU RVBARs...
cpu1: [0x210150000] = 0x81a450000
cpu2: [0x210250000] = 0x81a450000
cpu3: [0x210350000] = 0x81a450000
cpu4: [0x211050000] = 0x81a450000
cpu5: [0x211150000] = 0x81a450000
cpu6: [0x211250000] = 0x81a450000
cpu7: [0x211350000] = 0x81a450000
Disabling other iodevs...
- IODEV.UART
- IODEV.FB
- IODEV.USB_VUART
- IODEV.USB1
- IODEV.USB2
- IODEV.USB3
- IODEV.USB4
- IODEV.USB5
- IODEV.USB6
- IODEV.USB7
Doing essential MMIO remaps...
Updating page tables...
PT[200000000:200200000] -> HW
PT[200200000:200400000] -> HOOK.RW PMGRTracer
PT[200400000:235200000] -> HW
PT[235200000:235204000] -> RESERVED VUART
PT[235204000:23b700000] -> HW
PT[23b700000:23b7001c0] -> WSYNC.RW PMGRTracer
PT[23b7001c0:23b7001c4] -> RESERVED PMGR HACK
PT[23b7001c4:23b7001c8] -> WSYNC.RW PMGRTracer
PT[23b7001c8:23b7001cc] -> RESERVED PMGR HACK
PT[23b7001cc:23b700200] -> WSYNC.RW PMGRTracer
PT[23b700200:23b700208] -> HW
PT[23b700208:23b700220] -> WSYNC.RW PMGRTracer
PT[23b700220:23b700224] -> RESERVED PMGR HACK
PT[23b700224:23b700248] -> WSYNC.RW PMGRTracer
PT[23b700248:23b700250] -> HW
PT[23b700250:23b700270] -> WSYNC.RW PMGRTracer
PT[23b700270:23b700274] -> RESERVED PMGR HACK
PT[23b700274:23b700420] -> WSYNC.RW PMGRTracer
PT[23b700420:23b700424] -> RESERVED PMGR HACK
PT[23b700424:23b700500] -> WSYNC.RW PMGRTracer
PT[23b700500:23b700c00] -> WSYNC. PMGRTracer
PT[23b700c00:23b700d00] -> WSYNC.RW PMGRTracer
PT[23b700d00:23b704000] -> WSYNC. PMGRTracer
PT[23b704000:23b704100] -> WSYNC.RW PMGRTracer
PT[23b704100:23b708000] -> WSYNC. PMGRTracer
PT[23b708000:23b708100] -> WSYNC.RW PMGRTracer
PT[23b708100:23b70c000] -> WSYNC. PMGRTracer
PT[23b70c000:23b70c100] -> WSYNC.RW PMGRTracer
PT[23b70c100:23b710000] -> WSYNC. PMGRTracer
PT[23b710000:23b710100] -> WSYNC.RW PMGRTracer
PT[23b710100:23b738004] -> WSYNC. PMGRTracer
PT[23b738004:23b73800c] -> HW
PT[23b73800c:23b754000] -> WSYNC. PMGRTracer
PT[23b754000:23b754020] -> RESERVED CPU_START
PT[23b754020:23b78c000] -> WSYNC. PMGRTracer
PT[23b78c000:23d280000] -> HW
PT[23d280000:23d280058] -> WSYNC. PMGRTracer
PT[23d280058:23d280088] -> WSYNC.RW PMGRTracer
PT[23d280088:23d28008c] -> RESERVED PMGR HACK
PT[23d28008c:23d280098] -> WSYNC.RW PMGRTracer
PT[23d280098:23d28009c] -> RESERVED PMGR HACK
PT[23d28009c:23d280158] -> WSYNC.RW PMGRTracer
PT[23d280158:23d284000] -> WSYNC. PMGRTracer
PT[23d284000:23d284100] -> WSYNC.RW PMGRTracer
PT[23d284100:23d288000] -> WSYNC. PMGRTracer
PT[23d288000:23d288100] -> WSYNC.RW PMGRTracer
PT[23d288100:23d29c044] -> WSYNC. PMGRTracer
PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
PT[23d29c048:23d29c05c] -> WSYNC. PMGRTracer
PT[23d29c05c:23d29c060] -> RESERVED PMGR HACK
PT[23d29c060:23d2b9000] -> WSYNC. PMGRTracer
PT[23d2b9000:23d2b9030] -> HW
PT[23d2b9030:23d2dc100] -> WSYNC. PMGRTracer
PT[23d2dc100:23d2dc104] -> HW
PT[23d2dc104:23d2f4000] -> WSYNC. PMGRTracer
PT[23d2f4000:300000000] -> HW
PT[380000000:780000000] -> HW
Uploading ADT (0x4db54 bytes)...
Improving logo...
Shutting down framebuffer...
Enabling SPRR...
Enabling GXF...
Jumping to entrypoint at 0x81a450800
[cpu0] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu0] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1)
[cpu0] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1)
[cpu0] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1)
[cpu0] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1)
[cpu0] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1)
[cpu0] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1)
[cpu0] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu0] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu0] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu0] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu0] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu0] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu0] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu0] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0][0x000000081a469544] PMGR: W.4 0x23d2b001c (reg[1] + 0x3001c) = 0x0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700000 (ECPU0.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700008 (ECPU1.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700010 (ECPU2.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700018 (ECPU3.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700020 (PCPU0.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700028 (PCPU1.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700040 (ECPM.pstate + 0x00) = 0x21f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700048 (PCPM.pstate + 0x00) = 0x21f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700100 (SBR.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700108 (AIC.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700110 (DWI.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700118 (SOC_SPMI0.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700120 (SOC_SPMI1.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700128 (SOC_SPMI2.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700130 (GPIO.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700138 (PMS_BUSIF.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700140 (PMS.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700148 (PMS_FPWM0.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700150 (PMS_FPWM1.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700158 (PMS_FPWM2.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700160 (PMS_FPWM3.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700168 (PMS_FPWM4.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700170 (SOC_DPE.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700178 (PMGR_SOC_OCLA.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700180 (ISPSENS0.pstate + 0x00) = 0x4000244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700188 (ISPSENS1.pstate + 0x00) = 0x4000244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700190 (ISPSENS2.pstate + 0x00) = 0x4000244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700198 (ISPSENS3.pstate + 0x00) = 0x4000244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001a0 (PCIE_REF.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001a8 (AFT0.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001b0 (DEVC0_IVDMC.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001d0 (SIO_CPU.pstate + 0x00) = 0xf0000ff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001d8 (FPWM0.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001e0 (FPWM1.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001e8 (FPWM2.pstate + 0x00) = 0x244
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001f0 (I2C0.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7001f8 (I2C1.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700208 (I2C3.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700210 (I2C4.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700228 (AUDIO_P.pstate + 0x00) = 0x2ff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700230 (SIO_ADMA.pstate + 0x00) = 0x2ff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700140 (PMS.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700238 (AES.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700240 (SPI0.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700250 (SPI2.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700258 (SPI3.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700268 (UART_N.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700270+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700278 (UART1.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700280 (UART2.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700288 (UART3.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700290 (UART4.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700298 (UART5.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002a0 (UART6.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002a8 (UART7.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002b0 (UART8.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002b8 (MCA0.pstate + 0x00) = 0x200
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002c0 (MCA1.pstate + 0x00) = 0xff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700228 (AUDIO_P.pstate + 0x00) = 0x2ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700230 (SIO_ADMA.pstate + 0x00) = 0x2ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002c8 (MCA2.pstate + 0x00) = 0x200
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002d0 (MCA3.pstate + 0x00) = 0x200
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002d8 (MCA4.pstate + 0x00) = 0x200
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002e0 (MCA5.pstate + 0x00) = 0x200
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002e8 (DPA0.pstate + 0x00) = 0xff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700228 (AUDIO_P.pstate + 0x00) = 0x2ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002f0 (DPA1.pstate + 0x00) = 0x200
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7002f8 (MCC.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700300 (DCS0.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700310 (DCS1.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700308 (DCS2.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700318 (DCS3.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700340 (SMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700350 (RMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700358 (MMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700360 (DISP0_FE.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700350 (RMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700368 (DISPEXT_FE.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700350 (RMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700378 (DISPEXT_CPU0.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700368 (DISPEXT_FE.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003c0 (JPG.pstate + 0x00) = 0xf000300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003c8 (MSR.pstate + 0x00) = 0xf002300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003d0 (MSR_ASE_CORE.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003d8 (PMP.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003e0 (PMS_SRAM.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003e8 (APCIE_GP.pstate + 0x00) = 0xf0020ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003f0 (ANS2.pstate + 0x00) = 0xf0023ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003f8 (GFX.pstate + 0x00) = 0xf002300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700400 (ISP_SYS.pstate + 0x00) = 0x2300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700408 (VENC_SYS.pstate + 0x00) = 0xf002300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700410 (AVD_SYS.pstate + 0x00) = 0xf002300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700418 (APCIE_ST.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b7003f0 (ANS2.pstate + 0x00) = 0xf0023ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700470 (ANE_SYS.pstate + 0x00) = 0xf002300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700c00 (SEP.pstate + 0x00) = 0x1f0020ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b708000 (VENC_DMA.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b708008 (VENC_PIPE4.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b708010 (VENC_PIPE5.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b708018 (VENC_ME0.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b708020 (VENC_ME1.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b70c000 (ANE_SYS_CPU.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b710018 (DISP0_CPU0.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700360 (DISP0_FE.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d280058 (ps[0][0] + 0x00) = 0x2ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d280060 (NUB_SPMI0.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d280070 (NUB_AON.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d280080 (NUB_GPIO.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d2800a8 (NUB_FABRIC.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d2800b0 (NUB_SRAM.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d2800b8 (DEBUG_USB.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23d280058 (ps[0][0] + 0x00) = 0x2ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d2800c0 (DEBUG_AUTH.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23d280058 (ps[0][0] + 0x00) = 0x2ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700030 (PCPU2.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700038 (PCPU3.pstate + 0x00) = 0x1f0
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700260 (SPI4.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700320 (DCS4.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700330 (DCS5.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700328 (DCS6.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700338 (DCS7.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x2300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003b0 (DISPDFR_BE.pstate + 0x00) = 0x300
[cpu0] PMGR R 23b700420+0:32 = 0x20ff -> 0x20ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700428 (ATC0_PCIE.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700430 (ATC0_CIO.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700438 (ATC0_CIO_PCIE.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700440 (ATC0_CIO_USB.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700450 (ATC1_PCIE.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700458 (ATC1_CIO.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700460 (ATC1_CIO_PCIE.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b700468 (ATC1_CIO_USB.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23b7003b8 (MIPI_DSI.pstate + 0x00) = 0x300
[cpu0][0x000000081a462804] PMGR: R.4 0x23d280068 (NUB_SPMI1.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d280078 (MSG.pstate + 0x00) = 0x244
[cpu0] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0] PMGR R 23d280098+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700420+0:32 = 0x20ff -> 0x20ff
[cpu0][0x000000081a462804] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0x000000081a462934] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a462934] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0] CPUSTART W 23b754000+4:32 = 0x2
[cpu0] CPUSTART W 23b754000+8:32 = 0x2
[cpu0] Starting guest secondary 0:1
[cpu0] CPU #1: RVBAR = 0x81a450000
TTY> HV: Initializing secondary 1
TTY> HV: Entering guest secondary 1 at 0x81a450000
[cpu1] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu1] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1)
[cpu1] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1)
[cpu1] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1)
[cpu1] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1)
[cpu1] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1)
[cpu1] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1)
[cpu1] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu1] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu1] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu1] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu1] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu1] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu1] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu1] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b754000+4:32 = 0x4
[cpu0] CPUSTART W 23b754000+8:32 = 0x4
[cpu0] Starting guest secondary 0:2
[cpu0] CPU #2: RVBAR = 0x81a450000
TTY> HV: Initializing secondary 2
TTY> HV: Entering guest secondary 2 at 0x81a450000
[cpu2] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu2] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1)
[cpu2] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1)
[cpu2] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1)
[cpu2] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1)
[cpu2] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1)
[cpu2] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1)
[cpu2] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu2] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu2] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu2] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu2] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu2] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu2] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu2] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b754000+4:32 = 0x8
[cpu0] CPUSTART W 23b754000+8:32 = 0x8
[cpu0] Starting guest secondary 0:3
[cpu0] CPU #3: RVBAR = 0x81a450000
TTY> HV: Initializing secondary 3
TTY> HV: Entering guest secondary 3 at 0x81a450000
[cpu3] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu3] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1)
[cpu3] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1)
[cpu3] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1)
[cpu3] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1)
[cpu3] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1)
[cpu3] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1)
[cpu3] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu3] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu3] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu3] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu3] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1)
[cpu3] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1)
[cpu3] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu3] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b754000+4:32 = 0x10
[cpu0] CPUSTART W 23b754000+c:32 = 0x1
[cpu0] Starting guest secondary 1:0
[cpu0] CPU #4: RVBAR = 0x81a450000
TTY> HV: Initializing secondary 4
TTY> HV: Entering guest secondary 4 at 0x81a450000
[cpu4] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu4] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu4] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu4] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu4] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu4] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1)
[cpu4] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1)
[cpu4] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1)
[cpu4] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1)
[cpu4] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu4] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu4] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu4] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu4] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1)
[cpu4] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1)
[cpu4] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1)
[cpu4] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1)
[cpu4] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu4] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu4] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu4] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu4] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu4] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu4] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu4] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu4] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu4] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu4] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1)
[cpu4] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1)
[cpu4] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1)
[cpu4] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1)
[cpu4] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu4] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu4] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu4] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu4] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu4] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu4] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu4] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu4] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu4] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b754000+4:32 = 0x20
[cpu0] CPUSTART W 23b754000+c:32 = 0x2
[cpu0] Starting guest secondary 1:1
[cpu0] CPU #5: RVBAR = 0x81a450000
TTY> HV: Initializing secondary 5
TTY> HV: Entering guest secondary 5 at 0x81a450000
[cpu5] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu5] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu5] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu5] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu5] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu5] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1)
[cpu5] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1)
[cpu5] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1)
[cpu5] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1)
[cpu5] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu5] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu5] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu5] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu5] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1)
[cpu5] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1)
[cpu5] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1)
[cpu5] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1)
[cpu5] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu5] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu5] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu5] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu5] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu5] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu5] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu5] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu5] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu5] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu5] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1)
[cpu5] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1)
[cpu5] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1)
[cpu5] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1)
[cpu5] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu5] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu5] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu5] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu5] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu5] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu5] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu5] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu5] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu5] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b754000+4:32 = 0x40
[cpu0] CPUSTART W 23b754000+c:32 = 0x4
[cpu0] Starting guest secondary 1:2
[cpu0] CPU #6: RVBAR = 0x81a450000
TTY> HV: Initializing secondary 6
TTY> HV: Entering guest secondary 6 at 0x81a450000
[cpu6] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu6] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu6] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu6] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu6] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu6] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1)
[cpu6] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1)
[cpu6] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1)
[cpu6] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1)
[cpu6] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu6] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu6] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu6] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu6] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1)
[cpu6] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1)
[cpu6] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1)
[cpu6] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1)
[cpu6] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu6] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu6] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu6] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu6] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu6] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu6] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu6] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu6] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu6] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu6] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1)
[cpu6] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1)
[cpu6] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1)
[cpu6] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1)
[cpu6] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu6] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu6] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu6] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu6] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu6] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu6] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu6] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu6] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu6] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b754000+4:32 = 0x80
[cpu0] CPUSTART W 23b754000+c:32 = 0x8
[cpu0] Starting guest secondary 1:3
[cpu0] CPU #7: RVBAR = 0x81a450000
TTY> HV: Initializing secondary 7
TTY> HV: Entering guest secondary 7 at 0x81a450000
[cpu7] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu7] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu7] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu7] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu7] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu7] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1)
[cpu7] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1)
[cpu7] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1)
[cpu7] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1)
[cpu7] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu7] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu7] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu7] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu7] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1)
[cpu7] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1)
[cpu7] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1)
[cpu7] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1)
[cpu7] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1)
[cpu7] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1)
[cpu7] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu7] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu7] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1)
[cpu7] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1)
[cpu7] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu7] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu7] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu7] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu7] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1)
[cpu7] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1)
[cpu7] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1)
[cpu7] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1)
[cpu7] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1)
[cpu7] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1)
[cpu7] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1)
[cpu7] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1)
[cpu7] Pass: mrs x0, HID1_EL1 = 1440000002000000 (HID1_EL1)
[cpu7] Pass: msr HID1_EL1, x0 = 1440000002000000 (OK) (HID1_EL1)
[cpu7] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1)
[cpu7] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1)
[cpu7] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu7] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b7001f0 (I2C0.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b7001f0 (I2C0.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b7001f0 (I2C0.pstate + 0x00) = 0xff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001c8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001c0+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff -> 0x20ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff -> 0x20ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff -> 0x20ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff -> 0x20ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b7003e8 (APCIE_GP.pstate + 0x00) = 0xf0020ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b7003e8 (APCIE_GP.pstate + 0x00) = 0xf0020ff -> 0xf0020ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b7003e8 (APCIE_GP.pstate + 0x00) = 0xf0020ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff -> 0xff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a46241c] PMGR: R.4 0x23b7001a0 (PCIE_REF.pstate + 0x00) = 0xf0000ff
[cpu0][0x000000081a462428] PMGR: W.4 0x23b7001a0 (PCIE_REF.pstate + 0x00) = 0xf0000ff -> 0xf0000ff
[cpu0][0x000000081a462444] PMGR: R.4 0x23b7001a0 (PCIE_REF.pstate + 0x00) = 0xf0000ff
[cpu0] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu1] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu2] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu3] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu4] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu5] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu6] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu7] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1)
[cpu0] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu0] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu1] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu1] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu2] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu2] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu3] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu3] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu4] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu4] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu5] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu5] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu6] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu6] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu7] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu7] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu0] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu0] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu0] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu0] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu0] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu0] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu0] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu0] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu0] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu0] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu0] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu0] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu0] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu0] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu0] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu0] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu0] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu0] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu0] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu0] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu1] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu1] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu1] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu1] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu1] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu1] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu1] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu1] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu1] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu1] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu1] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu1] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu1] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu1] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu1] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu1] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu1] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu1] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu1] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu1] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu2] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu2] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu2] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu2] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu2] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu2] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu2] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu2] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu2] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu2] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu2] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu2] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu2] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu2] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu2] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu2] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu2] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu2] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu2] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu2] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu3] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu3] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu3] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu3] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu3] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu3] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu3] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu3] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu3] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu3] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu3] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu3] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu3] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu3] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu3] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu3] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu3] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu3] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu3] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu3] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu4] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu4] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu4] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu4] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu4] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu4] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu4] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu4] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu4] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu4] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu4] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu4] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu4] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu4] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu4] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu4] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu4] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu4] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu4] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu4] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu5] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu5] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu5] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu5] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu5] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu5] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu5] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu5] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu5] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu5] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu5] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu5] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu5] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu5] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu5] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu5] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu5] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu5] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu5] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu5] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu6] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu6] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu6] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu6] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu6] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu6] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu6] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu6] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu6] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu6] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu6] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu6] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu6] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu6] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu6] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu6] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu6] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu6] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu6] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu6] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu7] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1)
[cpu7] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1)
[cpu7] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5)
[cpu7] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4)
[cpu7] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5)
[cpu7] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4)
[cpu7] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5)
[cpu7] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4)
[cpu7] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5)
[cpu7] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4)
[cpu7] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu7] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu7] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1)
[cpu7] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1)
[cpu7] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7)
[cpu7] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6)
[cpu7] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7)
[cpu7] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6)
[cpu7] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7)
[cpu7] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700100 (SBR.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700100 (SBR.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700100 (SBR.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700108 (AIC.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700108 (AIC.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700108 (AIC.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700110 (DWI.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700110 (DWI.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700110 (DWI.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700118 (SOC_SPMI0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700118 (SOC_SPMI0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700118 (SOC_SPMI0.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700120 (SOC_SPMI1.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700120 (SOC_SPMI1.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700120 (SOC_SPMI1.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700128 (SOC_SPMI2.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700128 (SOC_SPMI2.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700128 (SOC_SPMI2.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700130 (GPIO.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700130 (GPIO.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700130 (GPIO.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700138 (PMS_BUSIF.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700138 (PMS_BUSIF.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700138 (PMS_BUSIF.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700140 (PMS.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700140 (PMS.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700140 (PMS.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700148 (PMS_FPWM0.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700150 (PMS_FPWM1.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700158 (PMS_FPWM2.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700160 (PMS_FPWM3.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700168 (PMS_FPWM4.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700170 (SOC_DPE.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700170 (SOC_DPE.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700170 (SOC_DPE.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700178 (PMGR_SOC_OCLA.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700178 (PMGR_SOC_OCLA.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700178 (PMGR_SOC_OCLA.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700180 (ISPSENS0.pstate + 0x00) = 0x4000244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700188 (ISPSENS1.pstate + 0x00) = 0x4000244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700190 (ISPSENS2.pstate + 0x00) = 0x4000244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700198 (ISPSENS3.pstate + 0x00) = 0x4000244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001a0 (PCIE_REF.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001a0 (PCIE_REF.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7001a0 (PCIE_REF.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001a8 (AFT0.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001b0 (DEVC0_IVDMC.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7001b8 (IMX.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001c0+0:32 = 0x1f0000ff: Dangerous write
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001c8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001c8+0:32 = 0x1f0000ff: Dangerous write
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001d0 (SIO_CPU.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001d0 (SIO_CPU.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7001d0 (SIO_CPU.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001d8 (FPWM0.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001e0 (FPWM1.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001e8 (FPWM2.pstate + 0x00) = 0x244
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001f0 (I2C0.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001f0 (I2C0.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7001f0 (I2C0.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001f8 (I2C1.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7001f8 (I2C1.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7001f8 (I2C1.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700208 (I2C3.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700208 (I2C3.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700208 (I2C3.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700210 (I2C4.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700210 (I2C4.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700210 (I2C4.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700218 (SPI_P.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700220+0:32 = 0xff -> 0xff
[cpu0] PMGR W 23b700220+0:32 = 0x100000ff: Dangerous write
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700228 (AUDIO_P.pstate + 0x00) = 0x2ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700228 (AUDIO_P.pstate + 0x00) = 0x2ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700228 (AUDIO_P.pstate + 0x00) = 0x2ff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700230 (SIO_ADMA.pstate + 0x00) = 0x2ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700230 (SIO_ADMA.pstate + 0x00) = 0x2ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700230 (SIO_ADMA.pstate + 0x00) = 0x2ff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700238 (AES.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700240 (SPI0.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700240 (SPI0.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700240 (SPI0.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700250 (SPI2.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700250 (SPI2.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700250 (SPI2.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700258 (SPI3.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700258 (SPI3.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700258 (SPI3.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700268 (UART_N.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700268 (UART_N.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700268 (UART_N.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0] PMGR R 23b700270+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700270+0:32 = 0xff -> 0xff
[cpu0] PMGR W 23b700270+0:32 = 0x100000ff: Dangerous write
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700278 (UART1.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700278 (UART1.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700278 (UART1.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700280 (UART2.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700280 (UART2.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700280 (UART2.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700288 (UART3.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700288 (UART3.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700288 (UART3.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700290 (UART4.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700290 (UART4.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700290 (UART4.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700298 (UART5.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700298 (UART5.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700298 (UART5.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002a0 (UART6.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002a0 (UART6.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7002a0 (UART6.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002a8 (UART7.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002a8 (UART7.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7002a8 (UART7.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002b0 (UART8.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002b0 (UART8.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7002b0 (UART8.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002b8 (MCA0.pstate + 0x00) = 0x200
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002c0 (MCA1.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002c0 (MCA1.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7002c0 (MCA1.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002c8 (MCA2.pstate + 0x00) = 0x200
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002d0 (MCA3.pstate + 0x00) = 0x200
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002d8 (MCA4.pstate + 0x00) = 0x200
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002e0 (MCA5.pstate + 0x00) = 0x200
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002e8 (DPA0.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002e8 (DPA0.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7002e8 (DPA0.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002f0 (DPA1.pstate + 0x00) = 0x200
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002f8 (MCC.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7002f8 (MCC.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7002f8 (MCC.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700260 (SPI4.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700260 (SPI4.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700260 (SPI4.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700300 (DCS0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700300 (DCS0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700300 (DCS0.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700310 (DCS1.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700310 (DCS1.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700310 (DCS1.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700308 (DCS2.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700308 (DCS2.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700308 (DCS2.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700318 (DCS3.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700318 (DCS3.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700318 (DCS3.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700340 (SMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700340 (SMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700340 (SMX.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700348 (APCIE.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700350 (RMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700350 (RMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700350 (RMX.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700358 (MMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700358 (MMX.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700358 (MMX.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700360 (DISP0_FE.pstate + 0x00) = 0x20ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700360 (DISP0_FE.pstate + 0x00) = 0x20ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700360 (DISP0_FE.pstate + 0x00) = 0x20ff -> 0x100020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700368 (DISPEXT_FE.pstate + 0x00) = 0x20ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700368 (DISPEXT_FE.pstate + 0x00) = 0x20ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700368 (DISPEXT_FE.pstate + 0x00) = 0x20ff -> 0x100020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700378 (DISPEXT_CPU0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700378 (DISPEXT_CPU0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700378 (DISPEXT_CPU0.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003c0 (JPG.pstate + 0x00) = 0xf000300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003c8 (MSR.pstate + 0x00) = 0xf002300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003d0 (MSR_ASE_CORE.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003d8 (PMP.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003d8 (PMP.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7003d8 (PMP.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003e0 (PMS_SRAM.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003e0 (PMS_SRAM.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7003e0 (PMS_SRAM.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003e8 (APCIE_GP.pstate + 0x00) = 0xf0020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003e8 (APCIE_GP.pstate + 0x00) = 0xf0020ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7003e8 (APCIE_GP.pstate + 0x00) = 0xf0020ff -> 0x1f0020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003f8 (GFX.pstate + 0x00) = 0xf002300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700320 (DCS4.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700320 (DCS4.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700320 (DCS4.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700330 (DCS5.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700330 (DCS5.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700330 (DCS5.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700328 (DCS6.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700328 (DCS6.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700328 (DCS6.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700338 (DCS7.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700338 (DCS7.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700338 (DCS7.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x2300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x2300
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x2300 -> 0x200f
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x23ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x23ff -> 0x100020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003b0 (DISPDFR_BE.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003b0 (DISPDFR_BE.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7003b0 (DISPDFR_BE.pstate + 0x00) = 0x300 -> 0xf
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003b0 (DISPDFR_BE.pstate + 0x00) = 0x3ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b7003b0 (DISPDFR_BE.pstate + 0x00) = 0x3ff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b7003b8 (MIPI_DSI.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700400 (ISP_SYS.pstate + 0x00) = 0x2300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700408 (VENC_SYS.pstate + 0x00) = 0xf002300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700410 (AVD_SYS.pstate + 0x00) = 0xf002300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700418 (APCIE_ST.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700418 (APCIE_ST.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700418 (APCIE_ST.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700470 (ANE_SYS.pstate + 0x00) = 0xf002300
[cpu0] PMGR R 23b700420+0:32 = 0x20ff -> 0x20ff
[cpu0] PMGR R 23b700420+0:32 = 0x20ff -> 0x20ff
[cpu0] PMGR W 23b700420+0:32 = 0x100020ff: Dangerous write
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700428 (ATC0_PCIE.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700430 (ATC0_CIO.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700430 (ATC0_CIO.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700430 (ATC0_CIO.pstate + 0x00) = 0x300 -> 0xf
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700430 (ATC0_CIO.pstate + 0x00) = 0x3ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700430 (ATC0_CIO.pstate + 0x00) = 0x3ff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700438 (ATC0_CIO_PCIE.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700440 (ATC0_CIO_USB.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700448 (ATC1_COMMON.pstate + 0x00) = 0x20ff -> 0x100020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700450 (ATC1_PCIE.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700458 (ATC1_CIO.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700458 (ATC1_CIO.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700458 (ATC1_CIO.pstate + 0x00) = 0x300 -> 0xf
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700458 (ATC1_CIO.pstate + 0x00) = 0x3ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700458 (ATC1_CIO.pstate + 0x00) = 0x3ff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700460 (ATC1_CIO_PCIE.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700468 (ATC1_CIO_USB.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700c00 (SEP.pstate + 0x00) = 0x1f0020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700c00 (SEP.pstate + 0x00) = 0x1f0020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700408 (VENC_SYS.pstate + 0x00) = 0xf002300
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700408 (VENC_SYS.pstate + 0x00) = 0xf002300 -> 0xf00200f
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700408 (VENC_SYS.pstate + 0x00) = 0xf0023ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700408 (VENC_SYS.pstate + 0x00) = 0xf0023ff -> 0x1f0020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b708000 (VENC_DMA.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b708000 (VENC_DMA.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b708000 (VENC_DMA.pstate + 0x00) = 0x300 -> 0xf
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b708000 (VENC_DMA.pstate + 0x00) = 0x3ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b708000 (VENC_DMA.pstate + 0x00) = 0x3ff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b708008 (VENC_PIPE4.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b708010 (VENC_PIPE5.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b708018 (VENC_ME0.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b708020 (VENC_ME1.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700470 (ANE_SYS.pstate + 0x00) = 0xf002300
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700470 (ANE_SYS.pstate + 0x00) = 0xf002300 -> 0xf00200f
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b700470 (ANE_SYS.pstate + 0x00) = 0xf0023ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b700470 (ANE_SYS.pstate + 0x00) = 0xf0023ff -> 0x1f0020ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b70c000 (ANE_SYS_CPU.pstate + 0x00) = 0x300
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b710018 (DISP0_CPU0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23b710018 (DISP0_CPU0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23b710018 (DISP0_CPU0.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280058 (ps[0][0] + 0x00) = 0x2ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280058 (ps[0][0] + 0x00) = 0x2ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d280058 (ps[0][0] + 0x00) = 0x2ff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280060 (NUB_SPMI0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280060 (NUB_SPMI0.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d280060 (NUB_SPMI0.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280070 (NUB_AON.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280070 (NUB_AON.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d280070 (NUB_AON.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280080 (NUB_GPIO.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280080 (NUB_GPIO.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d280080 (NUB_GPIO.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800a8 (NUB_FABRIC.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800a8 (NUB_FABRIC.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d2800a8 (NUB_FABRIC.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800b0 (NUB_SRAM.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800b0 (NUB_SRAM.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d2800b0 (NUB_SRAM.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800b8 (DEBUG_USB.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800b8 (DEBUG_USB.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d2800b8 (DEBUG_USB.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800c0 (DEBUG_AUTH.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800c0 (DEBUG_AUTH.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d2800c0 (DEBUG_AUTH.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280068 (NUB_SPMI1.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280068 (NUB_SPMI1.pstate + 0x00) = 0xf0000ff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d280068 (NUB_SPMI1.pstate + 0x00) = 0xf0000ff -> 0x1f0000ff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280078 (MSG.pstate + 0x00) = 0x244
[cpu0] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu0] PMGR W 23d280088+0:32 = 0x100000ff: Dangerous write
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d280090 (ATC1_USB_AON.pstate + 0x00) = 0xff -> 0x100000ff
[cpu0] PMGR R 23d280098+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23d280098+0:32 = 0xff -> 0xff
[cpu0] PMGR W 23d280098+0:32 = 0x100000ff: Dangerous write
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793270] PMGR: R.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff
[cpu0][0xffffcfb633793194] PMGR: W.4 0x23d2800a0 (ATC1_USB.pstate + 0x00) = 0xff -> 0x100000ff
[cpu5][0xffffcfb633793270] PMGR: R.4 0x23b700280 (UART2.pstate + 0x00) = 0xff
[cpu5][0xffffcfb633793194] PMGR: W.4 0x23b700280 (UART2.pstate + 0x00) = 0xff -> 0xf0
[cpu5][0xffffcfb633793270] PMGR: R.4 0x23b700280 (UART2.pstate + 0x00) = 0x200
TTY> HV: stage 1 translation failed at VA 0x682008060
[cpu5] Guest exception: EXCEPTION_LOWER/SYNC
== Exception taken from EL1h ==
SPSR = 0x60400005 (N=0, Z=1, C=1, V=0, TCO=0, DIT=0, UAO=0, PAN=1, SS=0, IL=0, SSBS=0, BTYPE=0, D=0, A=0, I=0, F=0, M=0x5(EL1h))
ELR = 0xffffcfb6336fc184 (0x81f4fc184)
ESR = 0x92000018 (ISS2=0x0, EC=0x24(DABORT_LOWER), IL=1, ISS=0x18)
FAR = 0x682008060
SP_EL1 = 0xffff800010053b50 (0x81958fb50)
x0-x3 = 0000000000000000 ffff189059600000 ffff800010d88060 0000000000000046
x4-x7 = ffff1892205cfe80 0000736b06020d0d 0d0d0206ebf38080 fefefeff646c606d
x8-x11 = 7f7f7f7f7f7f7f7f ffffcfb6336fc3ec 0101010101010101 0000000000000004
x12-x15 = 0000000000000040 ffffcfb633ef2000 0000000000000000 ffffffffffffffff
x16-x19 = 7320737361707962 203a74726f707075 0000000000000020 0000000000000000
x20-x23 = ffff18906ac70c80 ffff189059bcb010 ffff189059bcb000 ffffcfb633c1e090
x24-x27 = 0000000000000000 0000000000000006 ffffcfb634081060 ffffcfb63400055c
x28-x30 = 0000000000000000 ffff800010053b50 ffffcfb6336fc3ec
== Faulting code ==
81f4fc174: f9001fe0 str x0, [sp, #56]
81f4fc178: d2800000 mov x0, #0x0 // #0
81f4fc17c: f9400a82 ldr x2, [x20, #16]
81f4fc180: 91018042 add x2, x2, #0x60
* 81f4fc184: b9400042 ldr w2, [x2]
81f4fc188: d50331bf dmb oshld
81f4fc18c: 2a0203e0 mov w0, w2
81f4fc190: ca000000 eor x0, x0, x0
81f4fc194: b5000000 cbnz x0, 81f4fc194 <_start+0x20>
== Data abort decoding ==
No instruction syndrome available
== L2C Registers ==
L2C_ERR_STS: 0x11000ffc00000080
L2C_ERR_ADR: 0x2300040682008060
L2C_ERR_INF: 0x1
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment