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Created June 27, 2017 20:44
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0-example.rs
#![feature(const_fn)]
#![no_std]
extern crate aligned;
extern crate byteorder;
extern crate blue_pill;
extern crate cortex_m;
extern crate cortex_m_rt;
#[macro_use(rtfm)]
extern crate cortex_m_rtfm as rtfm;
extern crate embedded_hal as hal;
use core::mem;
use aligned::Aligned;
use blue_pill::led::{self, Green};
use blue_pill::time::Hertz;
use blue_pill::{Serial, Timer, stm32f103xx};
use byteorder::{ByteOrder, LittleEndian};
use cortex_m::itm;
use hal::prelude::*;
use rtfm::Threshold;
const BAUD_RATE: Hertz = Hertz(115_200);
const FREQUENCY: Hertz = Hertz(1);
rtfm! {
device: stm32f103xx,
peripherals: {
DWT @ 1,
ITM @ 1,
TIM2 @ 1,
USART1 @ 1,
},
resources: {
SLEEP_CYCLES: u32 = 0; @ 1,
},
init: {
body: init,
peripherals: [
AFIO,
DWT,
GPIOA,
GPIOC,
RCC,
TIM2,
USART1,
],
},
idle: {
body: idle,
local: {},
peripherals: [
DWT,
],
resources: [
SLEEP_CYCLES,
],
},
exceptions: {},
interrupts: {
TIM2: {
body: blinky,
priority: 1,
enabled: true,
local: {
snapshot: Option<u32> = None;
state: bool = false;
},
peripherals: [
DWT,
ITM,
TIM2,
],
resources: [
SLEEP_CYCLES,
],
},
USART1: {
body: loopback,
priority: 1,
enabled: true,
local: {},
peripherals: [
USART1,
],
resources: [],
},
},
}
// INITIALIZATION
fn init(p: init::Peripherals, _r: init::Resources) {
let timer = Timer(p.TIM2);
let serial = Serial(p.USART1);
p.DWT.enable_cycle_counter();
led::init(p.GPIOC, p.RCC);
timer.init(FREQUENCY.invert(), p.RCC);
timer.resume();
serial.init(BAUD_RATE.invert(), p.AFIO, None, p.GPIOA, p.RCC);
}
// IDLE LOOP: CPU USAGE MONITOR
fn idle(
_t: &Threshold,
_l: &'static mut idle::Local,
p: &idle::Peripherals,
r: &mut idle::Resources,
) -> ! {
loop {
rtfm::atomic(|t| {
let (before, after) = p.DWT.claim(t, |dwt, _| {
let before = dwt.cyccnt.read();
rtfm::wfi();
let after = dwt.cyccnt.read();
(before, after)
});
let elapsed = after.wrapping_sub(before);
r.SLEEP_CYCLES
.claim_mut(t, |sleep_cycles, _| { **sleep_cycles += elapsed; })
})
}
}
// TASKS
// Blink an LED and report CPU usage
fn blinky(
t: &Threshold,
l: &mut TIM2::Local,
p: &TIM2::Peripherals,
r: &mut TIM2::Resources,
) {
p.TIM2.claim(t, |tim2, _| {
let timer = Timer(tim2);
timer.wait().unwrap();
});
*l.state = !*l.state;
if *l.state {
Green.on()
} else {
Green.off()
}
// report CPU usage through the ITM
let curr = p.DWT.claim(t, |dwt, _| dwt.cyccnt.read());
let sleep_cycles = r.SLEEP_CYCLES
.claim_mut(t, |sleep_cycles, _| mem::replace(&mut **sleep_cycles, 0));
if let Some(prev) = l.snapshot.take() {
let elapsed = prev.wrapping_sub(curr);
let mut buffer = Aligned([0; 8]);
LittleEndian::write_u32(&mut buffer[..4], sleep_cycles);
LittleEndian::write_u32(&mut (*buffer)[4..], elapsed);
p.ITM
.claim(t, |itm, _| { itm::write_aligned(&itm.stim[0], &buffer); });
}
*l.snapshot = Some(curr);
}
// Serial interface loopback
fn loopback(
t: &Threshold,
_l: &mut USART1::Local,
p: &USART1::Peripherals,
_r: &mut USART1::Resources,
) {
p.USART1.claim(t, |usart1, _| {
let serial = Serial(usart1);
let byte = serial.read().unwrap();
serial.write(byte).unwrap()
});
}
Raw
1-expanded.rs
#![feature(prelude_import)]
#![no_std]
#![feature(const_fn)]
#![no_std]
#[prelude_import]
use core::prelude::v1::*;
#[macro_use]
extern crate core as core;
extern crate aligned;
extern crate byteorder;
extern crate blue_pill;
extern crate cortex_m;
extern crate cortex_m_rt;
#[macro_use(rtfm)]
extern crate cortex_m_rtfm as rtfm;
extern crate embedded_hal as hal;
use core::mem;
use aligned::Aligned;
use blue_pill::led::{self, Green};
use blue_pill::time::Hertz;
use blue_pill::{Serial, Timer, stm32f103xx};
use byteorder::{ByteOrder, LittleEndian};
use cortex_m::itm;
use hal::prelude::*;
use rtfm::Threshold;
const BAUD_RATE: Hertz = Hertz(115200);
const FREQUENCY: Hertz = Hertz(1);
mod _ceiling {
#![allow(non_upper_case_globals)]
#![allow(dead_code)]
pub const SLEEP_CYCLES: u8 = 1;
pub const DWT: u8 = 1;
pub const ITM: u8 = 1;
pub const TIM2: u8 = 1;
pub const USART1: u8 = 1;
mod verify {
#![allow(dead_code)]
#![deny(const_err)]
const SLEEP_CYCLES: u8 = ::MAX_PRIORITY - 1;
const DWT: u8 = ::MAX_PRIORITY - 1;
const ITM: u8 = ::MAX_PRIORITY - 1;
const TIM2: u8 = ::MAX_PRIORITY - 1;
const USART1: u8 = ::MAX_PRIORITY - 1;
}
}
pub mod _resource {
#[allow(non_upper_case_globals)]
pub static SLEEP_CYCLES: ::Resource<u32> = ::Resource::new(0);
#[allow(non_camel_case_types)]
pub struct SLEEP_CYCLES {
_0: (),
}
impl SLEEP_CYCLES {
pub unsafe fn new() -> Self {
SLEEP_CYCLES { _0: () }
}
pub fn claim<R, F>(&self, t: &::Threshold, f: F) -> R
where
F: FnOnce(&::Static<u32>, &::Threshold) -> R,
{
unsafe { SLEEP_CYCLES.claim(super::_ceiling::SLEEP_CYCLES, t, f) }
}
pub fn claim_mut<R, F>(&mut self, t: &::Threshold, f: F) -> R
where
F: FnOnce(&mut ::Static<u32>, &::Threshold) -> R,
{
unsafe {
SLEEP_CYCLES.claim_mut(super::_ceiling::SLEEP_CYCLES, t, f)
}
}
}
}
mod _peripheral {
static DWT: ::Peripheral<::stm32f103xx::DWT> =
unsafe { ::Peripheral::new(::stm32f103xx::DWT, 1) };
pub struct DWT {
_0: (),
}
impl DWT {
pub unsafe fn new() -> Self {
DWT { _0: () }
}
pub fn claim<R, F>(&self, t: &::Threshold, f: F) -> R
where
F: FnOnce(&::stm32f103xx::DWT, &::Threshold) -> R,
{
unsafe { DWT.claim(t, f) }
}
}
static ITM: ::Peripheral<::stm32f103xx::ITM> =
unsafe { ::Peripheral::new(::stm32f103xx::ITM, 1) };
pub struct ITM {
_0: (),
}
impl ITM {
pub unsafe fn new() -> Self {
ITM { _0: () }
}
pub fn claim<R, F>(&self, t: &::Threshold, f: F) -> R
where
F: FnOnce(&::stm32f103xx::ITM, &::Threshold) -> R,
{
unsafe { ITM.claim(t, f) }
}
}
static TIM2: ::Peripheral<::stm32f103xx::TIM2> =
unsafe { ::Peripheral::new(::stm32f103xx::TIM2, 1) };
pub struct TIM2 {
_0: (),
}
impl TIM2 {
pub unsafe fn new() -> Self {
TIM2 { _0: () }
}
pub fn claim<R, F>(&self, t: &::Threshold, f: F) -> R
where
F: FnOnce(&::stm32f103xx::TIM2, &::Threshold) -> R,
{
unsafe { TIM2.claim(t, f) }
}
}
static USART1: ::Peripheral<::stm32f103xx::USART1> =
unsafe { ::Peripheral::new(::stm32f103xx::USART1, 1) };
pub struct USART1 {
_0: (),
}
impl USART1 {
pub unsafe fn new() -> Self {
USART1 { _0: () }
}
pub fn claim<R, F>(&self, t: &::Threshold, f: F) -> R
where
F: FnOnce(&::stm32f103xx::USART1, &::Threshold) -> R,
{
unsafe { USART1.claim(t, f) }
}
}
}
#[allow(non_snake_case)]
mod TIM2 {
pub struct Local {
pub snapshot: ::Static<Option<u32>>,
pub state: ::Static<bool>,
}
pub struct Resources {
pub SLEEP_CYCLES: super::_resource::SLEEP_CYCLES,
}
pub struct Peripherals {
pub DWT: super::_peripheral::DWT,
pub ITM: super::_peripheral::ITM,
pub TIM2: super::_peripheral::TIM2,
}
}
#[allow(non_snake_case)]
mod USART1 {
pub struct Local {}
pub struct Resources {}
pub struct Peripherals {
pub USART1: super::_peripheral::USART1,
}
}
#[allow(non_snake_case)]
#[no_mangle]
pub unsafe extern "C" fn TIM2() {
#[allow(dead_code)]
#[deny(const_err)]
const TIM2: (u8, u8) = (1 - 1, ::MAX_PRIORITY - 1);
#[allow(dead_code)]
#[allow(non_upper_case_globals)]
#[deny(const_err)]
const SLEEP_CYCLES: u8 = _ceiling::SLEEP_CYCLES - 1;
let _ = stm32f103xx::interrupt::Interrupt::TIM2;
let f: fn(
&::Threshold,
&mut TIM2::Local,
&TIM2::Peripherals,
&mut TIM2::Resources,
) = blinky;
#[allow(unused_unsafe)]
static mut LOCAL: TIM2::Local = unsafe {
TIM2::Local {
snapshot: ::Static::new(None),
state: ::Static::new(false),
}
};
f(
&::Threshold::new(1),
&mut LOCAL,
&TIM2::Peripherals {
DWT: _peripheral::DWT::new(),
ITM: _peripheral::ITM::new(),
TIM2: _peripheral::TIM2::new(),
},
&mut TIM2::Resources { SLEEP_CYCLES: _resource::SLEEP_CYCLES::new() },
)
}
#[allow(non_snake_case)]
#[no_mangle]
pub unsafe extern "C" fn USART1() {
#[allow(dead_code)]
#[deny(const_err)]
const USART1: (u8, u8) = (1 - 1, ::MAX_PRIORITY - 1);
let _ = stm32f103xx::interrupt::Interrupt::USART1;
let f: fn(
&::Threshold,
&mut USART1::Local,
&USART1::Peripherals,
&mut USART1::Resources,
) = loopback;
#[allow(unused_unsafe)]
static mut LOCAL: USART1::Local = unsafe { USART1::Local {} };
f(
&::Threshold::new(1),
&mut LOCAL,
&USART1::Peripherals { USART1: _peripheral::USART1::new() },
&mut USART1::Resources {},
)
}
#[allow(non_snake_case)]
mod init {
pub struct Peripherals<'a> {
pub _0: ::core::marker::PhantomData<&'a ()>,
pub AFIO: &'a ::stm32f103xx::AFIO,
pub DWT: &'a ::stm32f103xx::DWT,
pub GPIOA: &'a ::stm32f103xx::GPIOA,
pub GPIOC: &'a ::stm32f103xx::GPIOC,
pub RCC: &'a ::stm32f103xx::RCC,
pub TIM2: &'a ::stm32f103xx::TIM2,
pub USART1: &'a ::stm32f103xx::USART1,
}
pub struct Resources<'a> {
pub _0: ::core::marker::PhantomData<&'a ()>,
pub SLEEP_CYCLES: &'a mut ::Static<u32>,
}
}
#[allow(non_snake_case)]
mod idle {
pub struct Local {}
pub struct Peripherals {
pub DWT: super::_peripheral::DWT,
}
pub struct Resources {
pub SLEEP_CYCLES: super::_resource::SLEEP_CYCLES,
}
}
fn main() {
let init: fn(init::Peripherals, init::Resources) = init;
let idle: fn(
&::Threshold,
&'static mut idle::Local,
&idle::Peripherals,
&mut idle::Resources,
) -> ! = idle;
::_free(|cs| unsafe {
init(
init::Peripherals {
_0: ::core::marker::PhantomData,
AFIO: stm32f103xx::AFIO.borrow(cs),
DWT: stm32f103xx::DWT.borrow(cs),
GPIOA: stm32f103xx::GPIOA.borrow(cs),
GPIOC: stm32f103xx::GPIOC.borrow(cs),
RCC: stm32f103xx::RCC.borrow(cs),
TIM2: stm32f103xx::TIM2.borrow(cs),
USART1: stm32f103xx::USART1.borrow(cs),
},
init::Resources {
_0: ::core::marker::PhantomData,
SLEEP_CYCLES: ::Static::ref_mut(
&mut *_resource::SLEEP_CYCLES.get(),
),
},
);
let _scb = stm32f103xx::SCB.borrow(cs);
let _nvic = stm32f103xx::NVIC.borrow(cs);
_nvic.set_priority(
stm32f103xx::interrupt::Interrupt::TIM2,
::_logical2hw(1),
);
_nvic.set_priority(
stm32f103xx::interrupt::Interrupt::USART1,
::_logical2hw(1),
);
if true {
_nvic.enable(stm32f103xx::interrupt::Interrupt::TIM2);
}
if true {
_nvic.enable(stm32f103xx::interrupt::Interrupt::USART1);
}
});
#[allow(unused_unsafe)]
static mut LOCAL: idle::Local = unsafe { idle::Local {} };
unsafe {
idle(
&::Threshold::new(0),
&mut LOCAL,
&idle::Peripherals { DWT: _peripheral::DWT::new() },
&mut idle::Resources {
SLEEP_CYCLES: _resource::SLEEP_CYCLES::new(),
},
)
}
}
fn init(p: init::Peripherals, _r: init::Resources) {
let timer = Timer(p.TIM2);
let serial = Serial(p.USART1);
p.DWT.enable_cycle_counter();
led::init(p.GPIOC, p.RCC);
timer.init(FREQUENCY.invert(), p.RCC);
timer.resume();
serial.init(BAUD_RATE.invert(), p.AFIO, None, p.GPIOA, p.RCC);
}
fn idle(
_t: &Threshold,
_l: &'static mut idle::Local,
p: &idle::Peripherals,
r: &mut idle::Resources,
) -> ! {
loop {
rtfm::atomic(|t| {
let (before, after) = p.DWT.claim(t, |dwt, _| {
let before = dwt.cyccnt.read();
rtfm::wfi();
let after = dwt.cyccnt.read();
(before, after)
});
let elapsed = after.wrapping_sub(before);
r.SLEEP_CYCLES
.claim_mut(t, |sleep_cycles, _| { **sleep_cycles += elapsed; })
})
}
}
fn blinky(
t: &Threshold,
l: &mut TIM2::Local,
p: &TIM2::Peripherals,
r: &mut TIM2::Resources,
) {
p.TIM2.claim(t, |tim2, _| {
let timer = Timer(tim2);
timer.wait().unwrap();
});
*l.state = !*l.state;
if *l.state {
Green.on()
} else {
Green.off()
}
let curr = p.DWT.claim(t, |dwt, _| dwt.cyccnt.read());
let sleep_cycles = r.SLEEP_CYCLES
.claim_mut(t, |sleep_cycles, _| mem::replace(&mut **sleep_cycles, 0));
if let Some(prev) = l.snapshot.take() {
let elapsed = prev.wrapping_sub(curr);
let mut buffer = Aligned([0; 8]);
LittleEndian::write_u32(&mut buffer[..4], sleep_cycles);
LittleEndian::write_u32(&mut (*buffer)[4..], elapsed);
p.ITM
.claim(t, |itm, _| { itm::write_aligned(&itm.stim[0], &buffer); });
}
*l.snapshot = Some(curr);
}
fn loopback(
t: &Threshold,
_l: &mut USART1::Local,
p: &USART1::Peripherals,
_r: &mut USART1::Resources,
) {
p.USART1.claim(t, |usart1, _| {
let serial = Serial(usart1);
let byte = serial.read().unwrap();
serial.write(byte).unwrap()
});
}
Raw
2-asm.s
Disassembly of section .text:
08000130 <cortex_m_rt::reset_handler>:
8000130: b580 push {r7, lr}
8000132: 466f mov r7, sp
8000134: f240 0000 movw r0, #0
8000138: f240 0104 movw r1, #4
800013c: f2c2 0000 movt r0, #8192 ; 0x2000
8000140: f2c2 0100 movt r1, #8192 ; 0x2000
8000144: 1a09 subs r1, r1, r0
8000146: f021 0103 bic.w r1, r1, #3
800014a: f000 f965 bl 8000418 <__aeabi_memclr4>
800014e: f240 0008 movw r0, #8
8000152: f240 0114 movw r1, #20
8000156: f2c2 0000 movt r0, #8192 ; 0x2000
800015a: f2c2 0100 movt r1, #8192 ; 0x2000
800015e: 1a09 subs r1, r1, r0
8000160: f021 0203 bic.w r2, r1, #3
8000164: f240 412c movw r1, #1068 ; 0x42c
8000168: f6c0 0100 movt r1, #2048 ; 0x800
800016c: f000 f94a bl 8000404 <__aeabi_memcpy4>
8000170: f000 f898 bl 80002a4 <main>
8000174: bf30 wfi
8000176: e7fd b.n 8000174 <cortex_m_rt::reset_handler+0x44>
08000178 <core::result::unwrap_failed>:
8000178: b580 push {r7, lr}
800017a: 466f mov r7, sp
800017c: f000 f941 bl 8000402 <core::panicking::panic_fmt>
08000180 <core::result::unwrap_failed>:
8000180: b580 push {r7, lr}
8000182: 466f mov r7, sp
8000184: f000 f93d bl 8000402 <core::panicking::panic_fmt>
08000188 <TIM2>:
8000188: b580 push {r7, lr}
800018a: 466f mov r7, sp
800018c: b082 sub sp, #8
800018e: 2110 movs r1, #16
8000190: f2c4 0100 movt r1, #16384 ; 0x4000
8000194: 6808 ldr r0, [r1, #0]
8000196: f010 0f01 tst.w r0, #1
800019a: d042 beq.n 8000222 <TIM2+0x9a>
800019c: 6808 ldr r0, [r1, #0]
800019e: f020 0001 bic.w r0, r0, #1
80001a2: 6008 str r0, [r1, #0]
80001a4: f240 0008 movw r0, #8
80001a8: f2c2 0000 movt r0, #8192 ; 0x2000
80001ac: 7a02 ldrb r2, [r0, #8]
80001ae: f082 0301 eor.w r3, r2, #1
80001b2: 2a00 cmp r2, #0
80001b4: f44f 3288 mov.w r2, #69632 ; 0x11000
80001b8: 7203 strb r3, [r0, #8]
80001ba: f04f 5300 mov.w r3, #536870912 ; 0x20000000
80001be: bf18 it ne
80001c0: f44f 5300 movne.w r3, #8192 ; 0x2000
80001c4: 508b str r3, [r1, r2]
80001c6: f241 0104 movw r1, #4100 ; 0x1004
80001ca: f240 0300 movw r3, #0
80001ce: f2ce 0100 movt r1, #57344 ; 0xe000
80001d2: f2c2 0300 movt r3, #8192 ; 0x2000
80001d6: f8d1 c000 ldr.w ip, [r1]
80001da: 2100 movs r1, #0
80001dc: f8d3 e000 ldr.w lr, [r3]
80001e0: 6019 str r1, [r3, #0]
80001e2: e9d0 2300 ldrd r2, r3, [r0]
80001e6: e9c0 1100 strd r1, r1, [r0]
80001ea: 2a01 cmp r2, #1
80001ec: d114 bne.n 8000218 <TIM2+0x90>
80001ee: f04f 4260 mov.w r2, #3758096384 ; 0xe0000000
80001f2: eba3 010c sub.w r1, r3, ip
80001f6: f8cd e000 str.w lr, [sp]
80001fa: 9101 str r1, [sp, #4]
80001fc: 6811 ldr r1, [r2, #0]
80001fe: 2901 cmp r1, #1
8000200: d1fc bne.n 80001fc <TIM2+0x74>
8000202: 9900 ldr r1, [sp, #0]
8000204: f04f 4260 mov.w r2, #3758096384 ; 0xe0000000
8000208: 6011 str r1, [r2, #0]
800020a: 6811 ldr r1, [r2, #0]
800020c: 2901 cmp r1, #1
800020e: d1fc bne.n 800020a <TIM2+0x82>
8000210: 9901 ldr r1, [sp, #4]
8000212: f04f 4260 mov.w r2, #3758096384 ; 0xe0000000
8000216: 6011 str r1, [r2, #0]
8000218: 2101 movs r1, #1
800021a: e9c0 1c00 strd r1, ip, [r0]
800021e: b002 add sp, #8
8000220: bd80 pop {r7, pc}
8000222: f7ff ffad bl 8000180 <core::result::unwrap_failed>
08000226 <USART1>:
8000226: b580 push {r7, lr}
8000228: 466f mov r7, sp
800022a: f643 0000 movw r0, #14336 ; 0x3800
800022e: f2c4 0001 movt r0, #16385 ; 0x4001
8000232: 6801 ldr r1, [r0, #0]
8000234: f011 0f08 tst.w r1, #8
8000238: d115 bne.n 8000266 <USART1+0x40>
800023a: 074a lsls r2, r1, #29
800023c: d416 bmi.n 800026c <USART1+0x46>
800023e: 078a lsls r2, r1, #30
8000240: d41a bmi.n 8000278 <USART1+0x52>
8000242: 0689 lsls r1, r1, #26
8000244: d51d bpl.n 8000282 <USART1+0x5c>
8000246: 7901 ldrb r1, [r0, #4]
8000248: 6802 ldr r2, [r0, #0]
800024a: f012 0f08 tst.w r2, #8
800024e: d11d bne.n 800028c <USART1+0x66>
8000250: 0753 lsls r3, r2, #29
8000252: d41f bmi.n 8000294 <USART1+0x6e>
8000254: 0793 lsls r3, r2, #30
8000256: d421 bmi.n 800029c <USART1+0x76>
8000258: 0612 lsls r2, r2, #24
800025a: bf44 itt mi
800025c: 7101 strbmi r1, [r0, #4]
800025e: bd80 popmi {r7, pc}
8000260: 2001 movs r0, #1
8000262: f7ff ff89 bl 8000178 <core::result::unwrap_failed>
8000266: f44f 7000 mov.w r0, #512 ; 0x200
800026a: e001 b.n 8000270 <USART1+0x4a>
800026c: f44f 7080 mov.w r0, #256 ; 0x100
8000270: 2100 movs r1, #0
8000272: 4308 orrs r0, r1
8000274: f7ff ff80 bl 8000178 <core::result::unwrap_failed>
8000278: 2100 movs r1, #0
800027a: 2000 movs r0, #0
800027c: 4308 orrs r0, r1
800027e: f7ff ff7b bl 8000178 <core::result::unwrap_failed>
8000282: 2000 movs r0, #0
8000284: 2101 movs r1, #1
8000286: 4308 orrs r0, r1
8000288: f7ff ff76 bl 8000178 <core::result::unwrap_failed>
800028c: f44f 7000 mov.w r0, #512 ; 0x200
8000290: f7ff ff72 bl 8000178 <core::result::unwrap_failed>
8000294: f44f 7080 mov.w r0, #256 ; 0x100
8000298: f7ff ff6e bl 8000178 <core::result::unwrap_failed>
800029c: 2000 movs r0, #0
800029e: f7ff ff6b bl 8000178 <core::result::unwrap_failed>
...
080002a4 <main>:
80002a4: b5b0 push {r4, r5, r7, lr}
80002a6: af02 add r7, sp, #8
80002a8: f89f 0124 ldrb.w r0, [pc, #292] ; 80003d0 <__rustc_debug_gdb_scripts_section__>
80002ac: f3ef 8c10 mrs ip, PRIMASK
80002b0: b672 cpsid i
80002b2: f44f 5100 mov.w r1, #8192 ; 0x2000
80002b6: f44f 5e80 mov.w lr, #4096 ; 0x1000
80002ba: 2401 movs r4, #1
80002bc: f241 0000 movw r0, #4096 ; 0x1000
80002c0: f01c 0f01 tst.w ip, #1
80002c4: f2ce 0000 movt r0, #57344 ; 0xe000
80002c8: 6802 ldr r2, [r0, #0]
80002ca: f042 0201 orr.w r2, r2, #1
80002ce: 6002 str r2, [r0, #0]
80002d0: f241 0218 movw r2, #4120 ; 0x1018
80002d4: f2c4 0202 movt r2, #16386 ; 0x4002
80002d8: 6813 ldr r3, [r2, #0]
80002da: f043 0310 orr.w r3, r3, #16
80002de: 6013 str r3, [r2, #0]
80002e0: f241 0310 movw r3, #4112 ; 0x1010
80002e4: f2c4 0301 movt r3, #16385 ; 0x4001
80002e8: 6019 str r1, [r3, #0]
80002ea: f240 0304 movw r3, #4
80002ee: f2c4 0301 movt r3, #16385 ; 0x4001
80002f2: f853 100e ldr.w r1, [r3, lr]
80002f6: f364 5117 bfi r1, r4, #20, #4
80002fa: f04f 047a mov.w r4, #122 ; 0x7a
80002fe: f843 100e str.w r1, [r3, lr]
8000302: f04f 0e00 mov.w lr, #0
8000306: 6851 ldr r1, [r2, #4]
8000308: f041 0101 orr.w r1, r1, #1
800030c: 6051 str r1, [r2, #4]
800030e: f240 010c movw r1, #12
8000312: f2c4 0100 movt r1, #16384 ; 0x4000
8000316: 61cc str r4, [r1, #28]
8000318: f64f 6410 movw r4, #65040 ; 0xfe10
800031c: 620c str r4, [r1, #32]
800031e: f04f 4480 mov.w r4, #1073741824 ; 0x40000000
8000322: f8c4 e000 str.w lr, [r4]
8000326: 680d ldr r5, [r1, #0]
8000328: f045 0501 orr.w r5, r5, #1
800032c: 600d str r5, [r1, #0]
800032e: 6821 ldr r1, [r4, #0]
8000330: f041 0101 orr.w r1, r1, #1
8000334: 6021 str r1, [r4, #0]
8000336: f244 0405 movw r4, #16389 ; 0x4005
800033a: 6811 ldr r1, [r2, #0]
800033c: ea41 0104 orr.w r1, r1, r4
8000340: 6011 str r1, [r2, #0]
8000342: f04f 0249 mov.w r2, #73 ; 0x49
8000346: 6819 ldr r1, [r3, #0]
8000348: f021 0104 bic.w r1, r1, #4
800034c: 6019 str r1, [r3, #0]
800034e: f8d3 1800 ldr.w r1, [r3, #2048] ; 0x800
8000352: f362 110b bfi r1, r2, #4, #8
8000356: f04f 0245 mov.w r2, #69 ; 0x45
800035a: f8c3 1800 str.w r1, [r3, #2048] ; 0x800
800035e: f643 0108 movw r1, #14344 ; 0x3808
8000362: f24e 4325 movw r3, #58405 ; 0xe425
8000366: f2c4 0101 movt r1, #16385 ; 0x4001
800036a: f2ce 0300 movt r3, #57344 ; 0xe000
800036e: f8c1 e008 str.w lr, [r1, #8]
8000372: 600a str r2, [r1, #0]
8000374: f04f 02c0 mov.w r2, #192 ; 0xc0
8000378: 60ca str r2, [r1, #12]
800037a: f242 020c movw r2, #8204 ; 0x200c
800037e: 604a str r2, [r1, #4]
8000380: f24e 1104 movw r1, #57604 ; 0xe104
8000384: f04f 02f0 mov.w r2, #240 ; 0xf0
8000388: f2ce 0100 movt r1, #57344 ; 0xe000
800038c: f881 2318 strb.w r2, [r1, #792] ; 0x318
8000390: 701a strb r2, [r3, #0]
8000392: f44f 4251 mov.w r2, #53504 ; 0xd100
8000396: f04f 5380 mov.w r3, #268435456 ; 0x10000000
800039a: 5083 str r3, [r0, r2]
800039c: f04f 0220 mov.w r2, #32
80003a0: 600a str r2, [r1, #0]
80003a2: d100 bne.n 80003a6 <main+0x102>
80003a4: b662 cpsie i
80003a6: f240 0100 movw r1, #0
80003aa: f2c2 0100 movt r1, #8192 ; 0x2000
80003ae: e000 b.n 80003b2 <main+0x10e>
80003b0: b662 cpsie i
80003b2: f3ef 8210 mrs r2, PRIMASK
80003b6: b672 cpsid i
80003b8: 6843 ldr r3, [r0, #4]
80003ba: bf30 wfi
80003bc: 6845 ldr r5, [r0, #4]
80003be: f012 0f01 tst.w r2, #1
80003c2: eba5 0303 sub.w r3, r5, r3
80003c6: 680d ldr r5, [r1, #0]
80003c8: 442b add r3, r5
80003ca: 600b str r3, [r1, #0]
80003cc: d1f1 bne.n 80003b2 <main+0x10e>
80003ce: e7ef b.n 80003b0 <main+0x10c>
080003d0 <__rustc_debug_gdb_scripts_section__>:
80003d0: 62646701 rsbvs r6, r4, #262144 ; 0x40000
80003d4: 616f6c5f cmnvs pc, pc, asr ip ; <UNPREDICTABLE>
80003d8: 75725f64 ldrbvc r5, [r2, #-3940]! ; 0xfffff09c
80003dc: 705f7473 subsvc r7, pc, r3, ror r4 ; <UNPREDICTABLE>
80003e0: 74746572 ldrbtvc r6, [r4], #-1394 ; 0xfffffa8e
80003e4: 72705f79 rsbsvc r5, r0, #484 ; 0x1e4
80003e8: 65746e69 ldrbvs r6, [r4, #-3689]! ; 0xfffff197
80003ec: 702e7372 eorvc r7, lr, r2, ror r3
80003f0: 00000079 andeq r0, r0, r9, ror r0
080003f4 <ADC>:
80003f4: f3ef 8008 mrs r0, MSP
80003f8: 6941 ldr r1, [r0, #20]
80003fa: f000 b800 b.w 80003fe <cortex_m_rt::default_handler>
080003fe <cortex_m_rt::default_handler>:
80003fe: be00 bkpt 0x0000
8000400: e7fe b.n 8000400 <cortex_m_rt::default_handler+0x2>
08000402 <core::panicking::panic_fmt>:
8000402: defe udf #254 ; 0xfe
08000404 <__aeabi_memcpy4>:
8000404: 2a00 cmp r2, #0
8000406: bf08 it eq
8000408: 4770 bxeq lr
800040a: f811 3b01 ldrb.w r3, [r1], #1
800040e: 3a01 subs r2, #1
8000410: f800 3b01 strb.w r3, [r0], #1
8000414: d1f9 bne.n 800040a <__aeabi_memcpy4+0x6>
8000416: 4770 bx lr
08000418 <__aeabi_memclr4>:
8000418: 2900 cmp r1, #0
800041a: bf08 it eq
800041c: 4770 bxeq lr
800041e: 2200 movs r2, #0
8000420: f800 2b01 strb.w r2, [r0], #1
8000424: 3901 subs r1, #1
8000426: d1fb bne.n 8000420 <__aeabi_memclr4+0x8>
8000428: 4770 bx lr
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