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japaric/0+lto.asm Secret

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0+lto.asm
08000510 <register::access>:
8000510: b580 push {r7, lr}
8000512: b088 sub sp, #32
8000514: 4601 mov r1, r0
8000516: 9103 str r1, [sp, #12]
8000518: f000 f985 bl 8000826 <<stm32f30x::Gpioe as core::ops::Deref>::deref>
800051c: 9002 str r0, [sp, #8]
800051e: e7ff b.n 8000520 <register::access+0x10>
8000520: 9802 ldr r0, [sp, #8]
8000522: f7ff fe31 bl 8000188 <<core::cell::UnsafeCell<T>>::get>
8000526: f7ff fe34 bl 8000192 <core::ptr::read_volatile>
800052a: 9004 str r0, [sp, #16]
800052c: 9005 str r0, [sp, #20]
800052e: a804 add r0, sp, #16
8000530: 9006 str r0, [sp, #24]
8000532: a805 add r0, sp, #20
8000534: 9007 str r0, [sp, #28]
8000536: 9806 ldr r0, [sp, #24]
8000538: 9907 ldr r1, [sp, #28]
800053a: f000 f80e bl 800055a <register::access::{{closure}}>
800053e: 9905 ldr r1, [sp, #20]
8000540: f8dd e008 ldr.w lr, [sp, #8]
8000544: 9001 str r0, [sp, #4]
8000546: 4670 mov r0, lr
8000548: 9100 str r1, [sp, #0]
800054a: f7ff fe1d bl 8000188 <<core::cell::UnsafeCell<T>>::get>
800054e: 9900 ldr r1, [sp, #0]
8000550: f7ff fe2a bl 80001a8 <core::ptr::write_volatile>
8000554: e7ff b.n 8000556 <register::access+0x46>
8000556: b008 add sp, #32
8000558: bd80 pop {r7, pc}
0800055a <register::access::{{closure}}>:
800055a: b095 sub sp, #84 ; 0x54
800055c: 4608 mov r0, r1
800055e: 9105 str r1, [sp, #20]
8000560: 9905 ldr r1, [sp, #20]
8000562: 9104 str r1, [sp, #16]
8000564: 9904 ldr r1, [sp, #16]
8000566: 9103 str r1, [sp, #12]
8000568: 9002 str r0, [sp, #8]
800056a: e7ff b.n 800056c <register::access::{{closure}}+0x12>
800056c: 9803 ldr r0, [sp, #12]
800056e: 9007 str r0, [sp, #28]
8000570: 9807 ldr r0, [sp, #28]
8000572: 9006 str r0, [sp, #24]
8000574: 9806 ldr r0, [sp, #24]
8000576: 9008 str r0, [sp, #32]
8000578: 9808 ldr r0, [sp, #32]
800057a: 9009 str r0, [sp, #36] ; 0x24
800057c: 2001 movs r0, #1
800057e: f88d 002b strb.w r0, [sp, #43] ; 0x2b
8000582: 9809 ldr r0, [sp, #36] ; 0x24
8000584: f89d 102b ldrb.w r1, [sp, #43] ; 0x2b
8000588: 900c str r0, [sp, #48] ; 0x30
800058a: 980c ldr r0, [sp, #48] ; 0x30
800058c: 900b str r0, [sp, #44] ; 0x2c
800058e: f88d 1037 strb.w r1, [sp, #55] ; 0x37
8000592: 980b ldr r0, [sp, #44] ; 0x2c
8000594: 900e str r0, [sp, #56] ; 0x38
8000596: f89d 0037 ldrb.w r0, [sp, #55] ; 0x37
800059a: f88d 003f strb.w r0, [sp, #63] ; 0x3f
800059e: 980e ldr r0, [sp, #56] ; 0x38
80005a0: 9010 str r0, [sp, #64] ; 0x40
80005a2: f89d 003f ldrb.w r0, [sp, #63] ; 0x3f
80005a6: 4601 mov r1, r0
80005a8: 2800 cmp r0, #0
80005aa: 9101 str r1, [sp, #4]
80005ac: d008 beq.n 80005c0 <register::access::{{closure}}+0x66>
80005ae: e7ff b.n 80005b0 <register::access::{{closure}}+0x56>
80005b0: 9801 ldr r0, [sp, #4]
80005b2: 2801 cmp r0, #1
80005b4: d008 beq.n 80005c8 <register::access::{{closure}}+0x6e>
80005b6: e7ff b.n 80005b8 <register::access::{{closure}}+0x5e>
80005b8: 9801 ldr r0, [sp, #4]
80005ba: 2802 cmp r0, #2
80005bc: d008 beq.n 80005d0 <register::access::{{closure}}+0x76>
80005be: e00b b.n 80005d8 <register::access::{{closure}}+0x7e>
80005c0: 2000 movs r0, #0
80005c2: f88d 0047 strb.w r0, [sp, #71] ; 0x47
80005c6: e00b b.n 80005e0 <register::access::{{closure}}+0x86>
80005c8: 2001 movs r0, #1
80005ca: f88d 0047 strb.w r0, [sp, #71] ; 0x47
80005ce: e007 b.n 80005e0 <register::access::{{closure}}+0x86>
80005d0: 2002 movs r0, #2
80005d2: f88d 0047 strb.w r0, [sp, #71] ; 0x47
80005d6: e003 b.n 80005e0 <register::access::{{closure}}+0x86>
80005d8: 2003 movs r0, #3
80005da: f88d 0047 strb.w r0, [sp, #71] ; 0x47
80005de: e7ff b.n 80005e0 <register::access::{{closure}}+0x86>
80005e0: f89d 0047 ldrb.w r0, [sp, #71] ; 0x47
80005e4: 9910 ldr r1, [sp, #64] ; 0x40
80005e6: 9113 str r1, [sp, #76] ; 0x4c
80005e8: 9913 ldr r1, [sp, #76] ; 0x4c
80005ea: 9112 str r1, [sp, #72] ; 0x48
80005ec: 9912 ldr r1, [sp, #72] ; 0x48
80005ee: 9114 str r1, [sp, #80] ; 0x50
80005f0: 9914 ldr r1, [sp, #80] ; 0x50
80005f2: 680a ldr r2, [r1, #0]
80005f4: f422 2240 bic.w r2, r2, #786432 ; 0xc0000
80005f8: 600a str r2, [r1, #0]
80005fa: f000 0003 and.w r0, r0, #3
80005fe: 9914 ldr r1, [sp, #80] ; 0x50
8000600: 680a ldr r2, [r1, #0]
8000602: ea42 4080 orr.w r0, r2, r0, lsl #18
8000606: 6008 str r0, [r1, #0]
8000608: 9814 ldr r0, [sp, #80] ; 0x50
800060a: 9000 str r0, [sp, #0]
800060c: e7ff b.n 800060e <register::access::{{closure}}+0xb4>
800060e: 9800 ldr r0, [sp, #0]
8000610: b015 add sp, #84 ; 0x54
8000612: 4770 bx lr
Raw
0.asm
08000554 <register::access>:
8000554: b580 push {r7, lr}
8000556: 466f mov r7, sp
8000558: b094 sub sp, #80 ; 0x50
800055a: 4601 mov r1, r0
800055c: 9003 str r0, [sp, #12]
800055e: 9803 ldr r0, [sp, #12]
8000560: 9004 str r0, [sp, #16]
8000562: 9804 ldr r0, [sp, #16]
8000564: 9102 str r1, [sp, #8]
8000566: f000 f9f8 bl 800095a <<stm32f30x::Gpioe as core::ops::Deref>::deref>
800056a: 9001 str r0, [sp, #4]
800056c: e7ff b.n 800056e <register::access+0x1a>
800056e: 9801 ldr r0, [sp, #4]
8000570: 9005 str r0, [sp, #20]
8000572: 9905 ldr r1, [sp, #20]
8000574: 9107 str r1, [sp, #28]
8000576: 9907 ldr r1, [sp, #28]
8000578: 910e str r1, [sp, #56] ; 0x38
800057a: 990e ldr r1, [sp, #56] ; 0x38
800057c: 910f str r1, [sp, #60] ; 0x3c
800057e: 980f ldr r0, [sp, #60] ; 0x3c
8000580: f7ff fe02 bl 8000188 <<core::cell::UnsafeCell<T>>::get>
8000584: f7ff fe09 bl 800019a <core::ptr::read_volatile>
8000588: 9009 str r0, [sp, #36] ; 0x24
800058a: 9809 ldr r0, [sp, #36] ; 0x24
800058c: 900a str r0, [sp, #40] ; 0x28
800058e: 9809 ldr r0, [sp, #36] ; 0x24
8000590: 900b str r0, [sp, #44] ; 0x2c
8000592: a80a add r0, sp, #40 ; 0x28
8000594: 900c str r0, [sp, #48] ; 0x30
8000596: a80b add r0, sp, #44 ; 0x2c
8000598: 900d str r0, [sp, #52] ; 0x34
800059a: 980c ldr r0, [sp, #48] ; 0x30
800059c: 990d ldr r1, [sp, #52] ; 0x34
800059e: f000 f815 bl 80005cc <register::access::{{closure}}>
80005a2: 9907 ldr r1, [sp, #28]
80005a4: f8dd e02c ldr.w lr, [sp, #44] ; 0x2c
80005a8: 9110 str r1, [sp, #64] ; 0x40
80005aa: f8cd e044 str.w lr, [sp, #68] ; 0x44
80005ae: 9910 ldr r1, [sp, #64] ; 0x40
80005b0: 9112 str r1, [sp, #72] ; 0x48
80005b2: 9911 ldr r1, [sp, #68] ; 0x44
80005b4: 9113 str r1, [sp, #76] ; 0x4c
80005b6: 9912 ldr r1, [sp, #72] ; 0x48
80005b8: 9000 str r0, [sp, #0]
80005ba: 4608 mov r0, r1
80005bc: f7ff fde4 bl 8000188 <<core::cell::UnsafeCell<T>>::get>
80005c0: 9913 ldr r1, [sp, #76] ; 0x4c
80005c2: f7ff fdf9 bl 80001b8 <core::ptr::write_volatile>
80005c6: e7ff b.n 80005c8 <register::access+0x74>
80005c8: b014 add sp, #80 ; 0x50
80005ca: bd80 pop {r7, pc}
080005cc <register::access::{{closure}}>:
80005cc: b0a0 sub sp, #128 ; 0x80
80005ce: 460a mov r2, r1
80005d0: 4603 mov r3, r0
80005d2: 9005 str r0, [sp, #20]
80005d4: 9106 str r1, [sp, #24]
80005d6: 9806 ldr r0, [sp, #24]
80005d8: 9007 str r0, [sp, #28]
80005da: 9807 ldr r0, [sp, #28]
80005dc: 900a str r0, [sp, #40] ; 0x28
80005de: 980a ldr r0, [sp, #40] ; 0x28
80005e0: 900c str r0, [sp, #48] ; 0x30
80005e2: 980c ldr r0, [sp, #48] ; 0x30
80005e4: 900b str r0, [sp, #44] ; 0x2c
80005e6: 980b ldr r0, [sp, #44] ; 0x2c
80005e8: 9009 str r0, [sp, #36] ; 0x24
80005ea: 9809 ldr r0, [sp, #36] ; 0x24
80005ec: 9008 str r0, [sp, #32]
80005ee: 9203 str r2, [sp, #12]
80005f0: 9302 str r3, [sp, #8]
80005f2: e7ff b.n 80005f4 <register::access::{{closure}}+0x28>
80005f4: 9808 ldr r0, [sp, #32]
80005f6: 900e str r0, [sp, #56] ; 0x38
80005f8: 980e ldr r0, [sp, #56] ; 0x38
80005fa: 900d str r0, [sp, #52] ; 0x34
80005fc: 980d ldr r0, [sp, #52] ; 0x34
80005fe: 900f str r0, [sp, #60] ; 0x3c
8000600: 980f ldr r0, [sp, #60] ; 0x3c
8000602: 9010 str r0, [sp, #64] ; 0x40
8000604: 2001 movs r0, #1
8000606: f88d 0047 strb.w r0, [sp, #71] ; 0x47
800060a: 9810 ldr r0, [sp, #64] ; 0x40
800060c: f89d 1047 ldrb.w r1, [sp, #71] ; 0x47
8000610: 9013 str r0, [sp, #76] ; 0x4c
8000612: 9813 ldr r0, [sp, #76] ; 0x4c
8000614: 9012 str r0, [sp, #72] ; 0x48
8000616: f88d 1053 strb.w r1, [sp, #83] ; 0x53
800061a: 9812 ldr r0, [sp, #72] ; 0x48
800061c: 9015 str r0, [sp, #84] ; 0x54
800061e: f89d 0053 ldrb.w r0, [sp, #83] ; 0x53
8000622: f88d 005b strb.w r0, [sp, #91] ; 0x5b
8000626: 9815 ldr r0, [sp, #84] ; 0x54
8000628: 9017 str r0, [sp, #92] ; 0x5c
800062a: f10d 005b add.w r0, sp, #91 ; 0x5b
800062e: 9018 str r0, [sp, #96] ; 0x60
8000630: 9818 ldr r0, [sp, #96] ; 0x60
8000632: 901a str r0, [sp, #104] ; 0x68
8000634: 981a ldr r0, [sp, #104] ; 0x68
8000636: 7800 ldrb r0, [r0, #0]
8000638: 4601 mov r1, r0
800063a: 2800 cmp r0, #0
800063c: 9101 str r1, [sp, #4]
800063e: d008 beq.n 8000652 <register::access::{{closure}}+0x86>
8000640: e7ff b.n 8000642 <register::access::{{closure}}+0x76>
8000642: 9801 ldr r0, [sp, #4]
8000644: 2801 cmp r0, #1
8000646: d008 beq.n 800065a <register::access::{{closure}}+0x8e>
8000648: e7ff b.n 800064a <register::access::{{closure}}+0x7e>
800064a: 9801 ldr r0, [sp, #4]
800064c: 2802 cmp r0, #2
800064e: d008 beq.n 8000662 <register::access::{{closure}}+0x96>
8000650: e00b b.n 800066a <register::access::{{closure}}+0x9e>
8000652: 2000 movs r0, #0
8000654: f88d 0067 strb.w r0, [sp, #103] ; 0x67
8000658: e00b b.n 8000672 <register::access::{{closure}}+0xa6>
800065a: 2001 movs r0, #1
800065c: f88d 0067 strb.w r0, [sp, #103] ; 0x67
8000660: e007 b.n 8000672 <register::access::{{closure}}+0xa6>
8000662: 2002 movs r0, #2
8000664: f88d 0067 strb.w r0, [sp, #103] ; 0x67
8000668: e003 b.n 8000672 <register::access::{{closure}}+0xa6>
800066a: 2003 movs r0, #3
800066c: f88d 0067 strb.w r0, [sp, #103] ; 0x67
8000670: e7ff b.n 8000672 <register::access::{{closure}}+0xa6>
8000672: f89d 0067 ldrb.w r0, [sp, #103] ; 0x67
8000676: 9917 ldr r1, [sp, #92] ; 0x5c
8000678: 911c str r1, [sp, #112] ; 0x70
800067a: 991c ldr r1, [sp, #112] ; 0x70
800067c: 911b str r1, [sp, #108] ; 0x6c
800067e: f88d 0077 strb.w r0, [sp, #119] ; 0x77
8000682: 981b ldr r0, [sp, #108] ; 0x6c
8000684: 901e str r0, [sp, #120] ; 0x78
8000686: f89d 0077 ldrb.w r0, [sp, #119] ; 0x77
800068a: f88d 007f strb.w r0, [sp, #127] ; 0x7f
800068e: 981e ldr r0, [sp, #120] ; 0x78
8000690: 6801 ldr r1, [r0, #0]
8000692: f421 2140 bic.w r1, r1, #786432 ; 0xc0000
8000696: 6001 str r1, [r0, #0]
8000698: f89d 007f ldrb.w r0, [sp, #127] ; 0x7f
800069c: f000 0003 and.w r0, r0, #3
80006a0: 991e ldr r1, [sp, #120] ; 0x78
80006a2: 680a ldr r2, [r1, #0]
80006a4: ea42 4080 orr.w r0, r2, r0, lsl #18
80006a8: 6008 str r0, [r1, #0]
80006aa: 981e ldr r0, [sp, #120] ; 0x78
80006ac: 9000 str r0, [sp, #0]
80006ae: e7ff b.n 80006b0 <register::access::{{closure}}+0xe4>
80006b0: 9800 ldr r0, [sp, #0]
80006b2: b020 add sp, #128 ; 0x80
80006b4: 4770 bx lr
Raw
1+lto.asm
08000456 <register::access>:
8000456: b510 push {r4, lr}
8000458: b082 sub sp, #8
800045a: f241 0000 movw r0, #4096 ; 0x1000
800045e: f6c4 0000 movt r0, #18432 ; 0x4800
8000462: f000 f892 bl 800058a <<stm32f30x::Gpioe as core::ops::Deref>::deref>
8000466: f7ff fe8f bl 8000188 <<core::cell::UnsafeCell<T>>::get>
800046a: 4604 mov r4, r0
800046c: f7ff fe8d bl 800018a <core::ptr::read_volatile>
8000470: 9001 str r0, [sp, #4]
8000472: a801 add r0, sp, #4
8000474: f000 f806 bl 8000484 <register::access::{{closure}}>
8000478: 9901 ldr r1, [sp, #4]
800047a: 4620 mov r0, r4
800047c: f7ff fe87 bl 800018e <core::ptr::write_volatile>
8000480: b002 add sp, #8
8000482: bd10 pop {r4, pc}
08000484 <register::access::{{closure}}>:
8000484: 6801 ldr r1, [r0, #0]
8000486: 2201 movs r2, #1
8000488: f362 4193 bfi r1, r2, #18, #2
800048c: 6001 str r1, [r0, #0]
800048e: 4770 bx lr
Raw
1.asm
08000456 <register::access>:
8000456: b510 push {r4, lr}
8000458: b082 sub sp, #8
800045a: f241 0000 movw r0, #4096 ; 0x1000
800045e: f6c4 0000 movt r0, #18432 ; 0x4800
8000462: f000 f892 bl 800058a <<stm32f30x::Gpioe as core::ops::Deref>::deref>
8000466: f7ff fe8f bl 8000188 <<core::cell::UnsafeCell<T>>::get>
800046a: 4604 mov r4, r0
800046c: f7ff fe8d bl 800018a <core::ptr::read_volatile>
8000470: 9001 str r0, [sp, #4]
8000472: a801 add r0, sp, #4
8000474: f000 f806 bl 8000484 <register::access::{{closure}}>
8000478: 9901 ldr r1, [sp, #4]
800047a: 4620 mov r0, r4
800047c: f7ff fe87 bl 800018e <core::ptr::write_volatile>
8000480: b002 add sp, #8
8000482: bd10 pop {r4, pc}
08000484 <register::access::{{closure}}>:
8000484: 6801 ldr r1, [r0, #0]
8000486: 2201 movs r2, #1
8000488: f362 4193 bfi r1, r2, #18, #2
800048c: 6001 str r1, [r0, #0]
800048e: 4770 bx lr
Raw
2+lto.asm
08000434 <register::access>:
8000434: f241 0000 movw r0, #4096 ; 0x1000
8000438: 2201 movs r2, #1
800043a: f6c4 0000 movt r0, #18432 ; 0x4800
800043e: 6801 ldr r1, [r0, #0]
8000440: f362 4193 bfi r1, r2, #18, #2
8000444: 6001 str r1, [r0, #0]
8000446: 4770 bx lr
Raw
2.asm
08000444 <register::access>:
8000444: b580 push {r7, lr}
8000446: f241 0000 movw r0, #4096 ; 0x1000
800044a: f6c4 0000 movt r0, #18432 ; 0x4800
800044e: f000 f87b bl 8000548 <<stm32f30x::Gpioe as core::ops::Deref>::deref>
8000452: 6801 ldr r1, [r0, #0]
8000454: 2201 movs r2, #1
8000456: f362 4193 bfi r1, r2, #18, #2
800045a: 6001 str r1, [r0, #0]
800045c: bd80 pop {r7, pc}
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