0-example.rs

#![deny(warnings)]
#![feature(const_fn)]
#![feature(plugin)]
#![no_std]
#![plugin(rtfm_macros)]

extern crate blue_pill;
extern crate cortex_m;
#[macro_use(task)]
extern crate cortex_m_rtfm as rtfm;
extern crate embedded_hal as hal;

use blue_pill::{Timer, Serial};
use blue_pill::led::{self, Green};
use blue_pill::time::Hertz;
use hal::prelude::*;
use rtfm::Threshold;

const BAUD_RATE: Hertz = Hertz(115_200);
const FREQUENCY: Hertz = Hertz(1);

rtfm! {
    device: blue_pill::stm32f103xx,

    resources: {
        SLEEP_CYCLES: u32 = 0;
    },

    tasks: {
        TIM2: {
            enabled: true,
            priority: 1,
            resources: [DWT, ITM, TIM2, SLEEP_CYCLES],
        },

        USART1: {
            enabled: true,
            priority: 1,
            resources: [USART1],
        },
    },

    init: {
        path: init,
        resources: [AFIO, GPIOA, GPIOC, TIM2, RCC, USART1],
    },

    idle: {
        local: {},
        path: idle,
        resources: [DWT, SLEEP_CYCLES],
    },
}

fn init(r: init::Resources) {
    let timer = Timer(r.TIM2);
    let serial = Serial(r.USART1);

    led::init(r.GPIOC, r.RCC);

    serial.init(BAUD_RATE.invert(), r.AFIO, None, r.GPIOA, r.RCC);

    timer.init(FREQUENCY.invert(), r.RCC);
    timer.resume();
}

fn idle(_t: Threshold, mut r: idle::Resources) -> ! {
    loop {
        rtfm::atomic(|cs| {
            let dwt = r.DWT.borrow(cs);
            let sleep_cycles = r.SLEEP_CYCLES.borrow_mut(cs);

            let before = dwt.cyccnt.read();
            rtfm::wfi();
            let after = dwt.cyccnt.read();

            let elapsed = after.wrapping_sub(before);
            **sleep_cycles += elapsed;
        });

        // tasks are serviced here
    }
}

task!(TIM2, blinky, Local {
    previous: Option<u32> = None;
    state: bool = false;
});

fn blinky(_t: Threshold, l: &mut Local, r: TIM2::Resources) {
    let timer = Timer(r.TIM2);

    timer.wait().unwrap();

    l.state = !l.state;
    if l.state {
        Green.on();
    } else {
        Green.off();
    }

    let current = r.DWT.cyccnt.read();
    if let Some(previous) = l.previous {
        let sleep_cycles = **r.SLEEP_CYCLES;
        **r.SLEEP_CYCLES = 0;

        let elapsed = current.wrapping_sub(previous);

        while !r.ITM.stim[0].is_fifo_ready() {}
        r.ITM.stim[0].write_u32(sleep_cycles);

        while !r.ITM.stim[0].is_fifo_ready() {}
        r.ITM.stim[0].write_u32(elapsed);
    }
    l.previous = Some(current);
}

task!(USART1, loopback);

fn loopback(_t: Threshold, r: USART1::Resources) {
    let serial = Serial(r.USART1);

    let byte = serial.read().unwrap();
    serial.write(byte).unwrap();
}

1-expanded.rs

#![feature(prelude_import)]
#![no_std]
#![deny(warnings)]
#![feature(const_fn)]
#![feature(plugin)]
#![no_std]
#![plugin(rtfm_macros)]
#[prelude_import]
use core::prelude::v1::*;
#[macro_use]
extern crate core as core;

extern crate blue_pill;
extern crate cortex_m;
#[macro_use(task)]
extern crate cortex_m_rtfm as rtfm;
extern crate embedded_hal as hal;

use blue_pill::{Timer, Serial};
use blue_pill::led::{self, Green};
use blue_pill::time::Hertz;
use hal::prelude::*;
use rtfm::Threshold;

const BAUD_RATE: Hertz = Hertz(115200);
const FREQUENCY: Hertz = Hertz(1);

mod init {
    #[allow(non_snake_case)]
    pub struct Resources<'a> {
        pub RCC: &'a mut ::blue_pill::stm32f103xx::RCC,
        pub TIM2: &'a mut ::blue_pill::stm32f103xx::TIM2,
        pub GPIOC: &'a mut ::blue_pill::stm32f103xx::GPIOC,
        pub AFIO: &'a mut ::blue_pill::stm32f103xx::AFIO,
        pub GPIOA: &'a mut ::blue_pill::stm32f103xx::GPIOA,
        pub USART1: &'a mut ::blue_pill::stm32f103xx::USART1,
    }
    impl<'a> Resources<'a> {
        pub unsafe fn new() -> Self {
            Resources {
                RCC: &mut *::blue_pill::stm32f103xx::RCC.get(),
                TIM2: &mut *::blue_pill::stm32f103xx::TIM2.get(),
                GPIOC: &mut *::blue_pill::stm32f103xx::GPIOC.get(),
                AFIO: &mut *::blue_pill::stm32f103xx::AFIO.get(),
                GPIOA: &mut *::blue_pill::stm32f103xx::GPIOA.get(),
                USART1: &mut *::blue_pill::stm32f103xx::USART1.get(),
            }
        }
    }
}
mod idle {
    #[allow(non_snake_case)]
    pub struct Resources {
        pub SLEEP_CYCLES: super::_resource::SLEEP_CYCLES,
        pub DWT: super::_resource::DWT,
    }
    impl Resources {
        pub unsafe fn new() -> Self {
            Resources {
                SLEEP_CYCLES: super::_resource::SLEEP_CYCLES::new(),
                DWT: super::_resource::DWT::new(),
            }
        }
    }
}
static DWT: rtfm::Peripheral<blue_pill::stm32f103xx::DWT> =
    rtfm::Peripheral::new(blue_pill::stm32f103xx::DWT);
static SLEEP_CYCLES: rtfm::Resource<u32> = rtfm::Resource::new(0);
mod _resource {
    #[allow(non_camel_case_types)]
    pub struct DWT {
        _0: (),
    }
    impl DWT {
        pub unsafe fn new() -> Self {
            DWT { _0: () }
        }
    }
    #[allow(non_camel_case_types)]
    pub struct SLEEP_CYCLES {
        _0: (),
    }
    impl SLEEP_CYCLES {
        pub unsafe fn new() -> Self {
            SLEEP_CYCLES { _0: () }
        }
    }
}
#[allow(dead_code)]
impl _resource::DWT {
    pub fn borrow<'cs>(
        &'cs self,
        _cs: &'cs rtfm::CriticalSection,
    ) -> &'cs blue_pill::stm32f103xx::DWT {
        unsafe { &*DWT.get() }
    }
    pub fn claim<R, F>(&self, t: &mut rtfm::Threshold, f: F) -> R
    where
        F: FnOnce(&blue_pill::stm32f103xx::DWT, &mut rtfm::Threshold) -> R,
    {
        unsafe {
            DWT.claim(
                // tasks are serviced here
                1u8,
                blue_pill::stm32f103xx::NVIC_PRIO_BITS,
                t,
                f,
            )
        }
    }
}
#[allow(dead_code)]
impl _resource::SLEEP_CYCLES {
    pub fn borrow<'cs>(
        &'cs self,
        _cs: &'cs rtfm::CriticalSection,
    ) -> &'cs rtfm::Static<u32> {
        unsafe { rtfm::Static::ref_(&*SLEEP_CYCLES.get()) }
    }
    pub fn borrow_mut<'cs>(
        &'cs mut self,
        _cs: &'cs rtfm::CriticalSection,
    ) -> &'cs mut rtfm::Static<u32> {
        unsafe { rtfm::Static::ref_mut(&mut *SLEEP_CYCLES.get()) }
    }
    pub fn claim<R, F>(&self, t: &mut rtfm::Threshold, f: F) -> R
    where
        F: FnOnce(&rtfm::Static<u32>, &mut rtfm::Threshold) -> R,
    {
        unsafe {
            SLEEP_CYCLES
                .claim(1u8, blue_pill::stm32f103xx::NVIC_PRIO_BITS, t, f)
        }
    }
    pub fn claim_mut<R, F>(&mut self, t: &mut rtfm::Threshold, f: F) -> R
    where
        F: FnOnce(&mut rtfm::Static<u32>, &mut rtfm::Threshold) -> R,
    {
        unsafe {
            SLEEP_CYCLES
                .claim_mut(1u8, blue_pill::stm32f103xx::NVIC_PRIO_BITS, t, f)
        }
    }
}
#[allow(dead_code)]
#[allow(non_snake_case)]
mod TIM2 {
    #[deny(dead_code)]
    pub const TIM2: u8 = 1u8;
    #[deny(const_err)]
    const CHECK_PRIORITY: (u8, u8) = (
        1u8 - 1,
        (1 << ::blue_pill::stm32f103xx::NVIC_PRIO_BITS) - 1u8,
    );
    #[allow(non_snake_case)]
    pub struct Resources<'a> {
        pub TIM2: &'a mut ::blue_pill::stm32f103xx::TIM2,
        pub ITM: &'a mut ::blue_pill::stm32f103xx::ITM,
        pub SLEEP_CYCLES: &'a mut ::rtfm::Static<u32>,
        pub DWT: &'a mut ::blue_pill::stm32f103xx::DWT,
    }
    impl<'a> Resources<'a> {
        pub unsafe fn new() -> Self {
            Resources {
                TIM2: &mut *::blue_pill::stm32f103xx::TIM2.get(),
                ITM: &mut *::blue_pill::stm32f103xx::ITM.get(),
                SLEEP_CYCLES: ::rtfm::Static::ref_mut(
                    &mut *super::SLEEP_CYCLES.get(),
                ),
                DWT: &mut *::blue_pill::stm32f103xx::DWT.get(),
            }
        }
    }
}
#[allow(dead_code)]
#[allow(non_snake_case)]
mod USART1 {
    #[deny(dead_code)]
    pub const USART1: u8 = 1u8;
    #[deny(const_err)]
    const CHECK_PRIORITY: (u8, u8) = (
        1u8 - 1,
        (1 << ::blue_pill::stm32f103xx::NVIC_PRIO_BITS) - 1u8,
    );
    #[allow(non_snake_case)]
    pub struct Resources<'a> {
        pub USART1: &'a mut ::blue_pill::stm32f103xx::USART1,
    }
    impl<'a> Resources<'a> {
        pub unsafe fn new() -> Self {
            Resources { USART1: &mut *::blue_pill::stm32f103xx::USART1.get() }
        }
    }
}
fn main() {
    let init: fn(init::Resources) = init;
    rtfm::atomic(|cs| unsafe {
        init(init::Resources::new());
        let nvic = blue_pill::stm32f103xx::NVIC.borrow(cs);
        let prio_bits = blue_pill::stm32f103xx::NVIC_PRIO_BITS;
        let hw = ((1 << prio_bits) - 1u8) << (8 - prio_bits);
        nvic.set_priority(blue_pill::stm32f103xx::Interrupt::TIM2, hw);
        nvic.enable(blue_pill::stm32f103xx::Interrupt::TIM2);
        let prio_bits = blue_pill::stm32f103xx::NVIC_PRIO_BITS;
        let hw = ((1 << prio_bits) - 1u8) << (8 - prio_bits);
        nvic.set_priority(blue_pill::stm32f103xx::Interrupt::USART1, hw);
        nvic.enable(blue_pill::stm32f103xx::Interrupt::USART1);
    });
    let idle: fn(rtfm::Threshold, idle::Resources) -> ! = idle;
    idle(unsafe { rtfm::Threshold::new(0) }, unsafe {
        idle::Resources::new()
    });
}
fn init(r: init::Resources) {
    let timer = Timer(r.TIM2);
    let serial = Serial(r.USART1);
    led::init(r.GPIOC, r.RCC);
    serial.init(BAUD_RATE.invert(), r.AFIO, None, r.GPIOA, r.RCC);
    timer.init(FREQUENCY.invert(), r.RCC);
    timer.resume();
}
fn idle(_t: Threshold, mut r: idle::Resources) -> ! {
    loop {
        rtfm::atomic(|cs| {
            let dwt = r.DWT.borrow(cs);
            let sleep_cycles = r.SLEEP_CYCLES.borrow_mut(cs);
            let before = dwt.cyccnt.read();
            rtfm::wfi();
            let after = dwt.cyccnt.read();
            let elapsed = after.wrapping_sub(before);
            **sleep_cycles += elapsed;
        });
    }
}
struct Local {
    previous: Option<u32>,
    state: bool,
}
#[allow(non_snake_case)]
#[no_mangle]
pub unsafe extern "C" fn TIM2() {
    let f: fn(::Threshold, &mut Local, ::TIM2::Resources) = blinky;
    static mut LOCAL: Local = Local {
        previous: None,
        state: false,
    };
    f(
        ::Threshold::new(::TIM2::TIM2),
        &mut LOCAL,
        ::TIM2::Resources::new(),
    );
}
fn blinky(_t: Threshold, l: &mut Local, r: TIM2::Resources) {
    let timer = Timer(r.TIM2);
    timer.wait().unwrap();
    l.state = !l.state;
    if l.state {
        Green.on();
    } else {
        Green.off();
    }
    let current = r.DWT.cyccnt.read();
    if let Some(previous) = l.previous {
        let sleep_cycles = **r.SLEEP_CYCLES;
        **r.SLEEP_CYCLES = 0;
        let elapsed = current.wrapping_sub(previous);
        while !r.ITM.stim[0].is_fifo_ready() {}
        r.ITM.stim[0].write_u32(sleep_cycles);
        while !r.ITM.stim[0].is_fifo_ready() {}
        r.ITM.stim[0].write_u32(elapsed);
    }
    l.previous = Some(current);
}
#[allow(non_snake_case)]
#[no_mangle]
pub unsafe extern "C" fn USART1() {
    let f: fn(::Threshold, ::USART1::Resources) = loopback;
    f(
        ::Threshold::new(::USART1::USART1),
        ::USART1::Resources::new(),
    );
}
fn loopback(_t: Threshold, r: USART1::Resources) {
    let serial = Serial(r.USART1);
    let byte = serial.read().unwrap();
    serial.write(byte).unwrap();
}

2-asm.s

08000130 <cortex_m_rt::reset_handler>:
 8000130:	b580      	push	{r7, lr}
 8000132:	466f      	mov	r7, sp
 8000134:	f240 0000 	movw	r0, #0
 8000138:	f240 0104 	movw	r1, #4
 800013c:	f2c2 0000 	movt	r0, #8192	; 0x2000
 8000140:	f2c2 0100 	movt	r1, #8192	; 0x2000
 8000144:	1a09      	subs	r1, r1, r0
 8000146:	f021 0103 	bic.w	r1, r1, #3
 800014a:	f000 fa13 	bl	8000574 <__aeabi_memclr4>
 800014e:	f240 0004 	movw	r0, #4
 8000152:	f240 0110 	movw	r1, #16
 8000156:	f2c2 0000 	movt	r0, #8192	; 0x2000
 800015a:	f2c2 0100 	movt	r1, #8192	; 0x2000
 800015e:	1a09      	subs	r1, r1, r0
 8000160:	f021 0203 	bic.w	r2, r1, #3
 8000164:	f240 517c 	movw	r1, #1404	; 0x57c
 8000168:	f6c0 0100 	movt	r1, #2048	; 0x800
 800016c:	f000 f9ba 	bl	80004e4 <__aeabi_memcpy4>
 8000170:	f000 f88f 	bl	8000292 <main>
 8000174:	bf30      	wfi
 8000176:	e7fd      	b.n	8000174 <cortex_m_rt::reset_handler+0x44>

08000178 <core::result::unwrap_failed>:
 8000178:	b580      	push	{r7, lr}
 800017a:	466f      	mov	r7, sp
 800017c:	f000 f9a7 	bl	80004ce <core::panicking::panic_fmt>

08000180 <core::result::unwrap_failed>:
 8000180:	b580      	push	{r7, lr}
 8000182:	466f      	mov	r7, sp
 8000184:	f000 f9a3 	bl	80004ce <core::panicking::panic_fmt>

08000188 <TIM2>:
 8000188:	b5d0      	push	{r4, r6, r7, lr}
 800018a:	af02      	add	r7, sp, #8
 800018c:	2110      	movs	r1, #16
 800018e:	f2c4 0100 	movt	r1, #16384	; 0x4000
 8000192:	6808      	ldr	r0, [r1, #0]
 8000194:	f010 0f01 	tst.w	r0, #1
 8000198:	d03b      	beq.n	8000212 <TIM2+0x8a>
 800019a:	6808      	ldr	r0, [r1, #0]
 800019c:	f020 0001 	bic.w	r0, r0, #1
 80001a0:	6008      	str	r0, [r1, #0]
 80001a2:	f240 0004 	movw	r0, #4
 80001a6:	f2c2 0000 	movt	r0, #8192	; 0x2000
 80001aa:	7a02      	ldrb	r2, [r0, #8]
 80001ac:	f082 0301 	eor.w	r3, r2, #1
 80001b0:	2a00      	cmp	r2, #0
 80001b2:	f44f 3288 	mov.w	r2, #69632	; 0x11000
 80001b6:	7203      	strb	r3, [r0, #8]
 80001b8:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 80001bc:	bf08      	it	eq
 80001be:	f04f 5300 	moveq.w	r3, #536870912	; 0x20000000
 80001c2:	508b      	str	r3, [r1, r2]
 80001c4:	f241 0104 	movw	r1, #4100	; 0x1004
 80001c8:	f2ce 0100 	movt	r1, #57344	; 0xe000
 80001cc:	6809      	ldr	r1, [r1, #0]
 80001ce:	6802      	ldr	r2, [r0, #0]
 80001d0:	2a01      	cmp	r2, #1
 80001d2:	d11a      	bne.n	800020a <TIM2+0x82>
 80001d4:	f240 0e00 	movw	lr, #0
 80001d8:	f8d0 c004 	ldr.w	ip, [r0, #4]
 80001dc:	2200      	movs	r2, #0
 80001de:	f2c2 0e00 	movt	lr, #8192	; 0x2000
 80001e2:	f8de 4000 	ldr.w	r4, [lr]
 80001e6:	f8ce 2000 	str.w	r2, [lr]
 80001ea:	f04f 4260 	mov.w	r2, #3758096384	; 0xe0000000
 80001ee:	6813      	ldr	r3, [r2, #0]
 80001f0:	2b01      	cmp	r3, #1
 80001f2:	d1fc      	bne.n	80001ee <TIM2+0x66>
 80001f4:	f04f 4260 	mov.w	r2, #3758096384	; 0xe0000000
 80001f8:	6014      	str	r4, [r2, #0]
 80001fa:	6813      	ldr	r3, [r2, #0]
 80001fc:	2b01      	cmp	r3, #1
 80001fe:	d1fc      	bne.n	80001fa <TIM2+0x72>
 8000200:	eba1 020c 	sub.w	r2, r1, ip
 8000204:	f04f 4360 	mov.w	r3, #3758096384	; 0xe0000000
 8000208:	601a      	str	r2, [r3, #0]
 800020a:	2201      	movs	r2, #1
 800020c:	e9c0 2100 	strd	r2, r1, [r0]
 8000210:	bdd0      	pop	{r4, r6, r7, pc}
 8000212:	f7ff ffb1 	bl	8000178 <core::result::unwrap_failed>

08000216 <USART1>:
 8000216:	b580      	push	{r7, lr}
 8000218:	466f      	mov	r7, sp
 800021a:	f643 0000 	movw	r0, #14336	; 0x3800
 800021e:	f2c4 0001 	movt	r0, #16385	; 0x4001
 8000222:	6801      	ldr	r1, [r0, #0]
 8000224:	f011 0f08 	tst.w	r1, #8
 8000228:	d115      	bne.n	8000256 <USART1+0x40>
 800022a:	074a      	lsls	r2, r1, #29
 800022c:	d416      	bmi.n	800025c <USART1+0x46>
 800022e:	078a      	lsls	r2, r1, #30
 8000230:	d41a      	bmi.n	8000268 <USART1+0x52>
 8000232:	0689      	lsls	r1, r1, #26
 8000234:	d51d      	bpl.n	8000272 <USART1+0x5c>
 8000236:	7901      	ldrb	r1, [r0, #4]
 8000238:	6802      	ldr	r2, [r0, #0]
 800023a:	f012 0f08 	tst.w	r2, #8
 800023e:	d11d      	bne.n	800027c <USART1+0x66>
 8000240:	0753      	lsls	r3, r2, #29
 8000242:	d41f      	bmi.n	8000284 <USART1+0x6e>
 8000244:	0793      	lsls	r3, r2, #30
 8000246:	d421      	bmi.n	800028c <USART1+0x76>
 8000248:	0612      	lsls	r2, r2, #24
 800024a:	bf44      	itt	mi
 800024c:	7101      	strbmi	r1, [r0, #4]
 800024e:	bd80      	popmi	{r7, pc}
 8000250:	2001      	movs	r0, #1
 8000252:	f7ff ff95 	bl	8000180 <core::result::unwrap_failed>
 8000256:	f44f 7000 	mov.w	r0, #512	; 0x200
 800025a:	e001      	b.n	8000260 <USART1+0x4a>
 800025c:	f44f 7080 	mov.w	r0, #256	; 0x100
 8000260:	2100      	movs	r1, #0
 8000262:	4308      	orrs	r0, r1
 8000264:	f7ff ff8c 	bl	8000180 <core::result::unwrap_failed>
 8000268:	2100      	movs	r1, #0
 800026a:	2000      	movs	r0, #0
 800026c:	4308      	orrs	r0, r1
 800026e:	f7ff ff87 	bl	8000180 <core::result::unwrap_failed>
 8000272:	2000      	movs	r0, #0
 8000274:	2101      	movs	r1, #1
 8000276:	4308      	orrs	r0, r1
 8000278:	f7ff ff82 	bl	8000180 <core::result::unwrap_failed>
 800027c:	f44f 7000 	mov.w	r0, #512	; 0x200
 8000280:	f7ff ff7e 	bl	8000180 <core::result::unwrap_failed>
 8000284:	f44f 7080 	mov.w	r0, #256	; 0x100
 8000288:	f7ff ff7a 	bl	8000180 <core::result::unwrap_failed>
 800028c:	2000      	movs	r0, #0
 800028e:	f7ff ff77 	bl	8000180 <core::result::unwrap_failed>

08000292 <main>:
 8000292:	b580      	push	{r7, lr}
 8000294:	466f      	mov	r7, sp
 8000296:	f240 1030 	movw	r0, #304	; 0x130
 800029a:	f241 0118 	movw	r1, #4120	; 0x1018
 800029e:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 80002a2:	f44f 5e80 	mov.w	lr, #4096	; 0x1000
 80002a6:	f6c0 0000 	movt	r0, #2048	; 0x800
 80002aa:	f2c4 0102 	movt	r1, #16386	; 0x4002
 80002ae:	7800      	ldrb	r0, [r0, #0]
 80002b0:	f3ef 8c10 	mrs	ip, PRIMASK
 80002b4:	b672      	cpsid	i
 80002b6:	680a      	ldr	r2, [r1, #0]
 80002b8:	f01c 0f01 	tst.w	ip, #1
 80002bc:	f042 0210 	orr.w	r2, r2, #16
 80002c0:	600a      	str	r2, [r1, #0]
 80002c2:	f241 0210 	movw	r2, #4112	; 0x1010
 80002c6:	f2c4 0201 	movt	r2, #16385	; 0x4001
 80002ca:	6013      	str	r3, [r2, #0]
 80002cc:	f240 0304 	movw	r3, #4
 80002d0:	f04f 0201 	mov.w	r2, #1
 80002d4:	f2c4 0301 	movt	r3, #16385	; 0x4001
 80002d8:	f853 000e 	ldr.w	r0, [r3, lr]
 80002dc:	f362 5017 	bfi	r0, r2, #20, #4
 80002e0:	f244 0205 	movw	r2, #16389	; 0x4005
 80002e4:	f843 000e 	str.w	r0, [r3, lr]
 80002e8:	6808      	ldr	r0, [r1, #0]
 80002ea:	ea40 0002 	orr.w	r0, r0, r2
 80002ee:	f04f 0249 	mov.w	r2, #73	; 0x49
 80002f2:	6008      	str	r0, [r1, #0]
 80002f4:	6818      	ldr	r0, [r3, #0]
 80002f6:	f020 0004 	bic.w	r0, r0, #4
 80002fa:	6018      	str	r0, [r3, #0]
 80002fc:	f8d3 0800 	ldr.w	r0, [r3, #2048]	; 0x800
 8000300:	f362 100b 	bfi	r0, r2, #4, #8
 8000304:	f04f 0200 	mov.w	r2, #0
 8000308:	f8c3 0800 	str.w	r0, [r3, #2048]	; 0x800
 800030c:	f643 0008 	movw	r0, #14344	; 0x3808
 8000310:	f04f 0345 	mov.w	r3, #69	; 0x45
 8000314:	f2c4 0001 	movt	r0, #16385	; 0x4001
 8000318:	6082      	str	r2, [r0, #8]
 800031a:	6003      	str	r3, [r0, #0]
 800031c:	f04f 03c0 	mov.w	r3, #192	; 0xc0
 8000320:	60c3      	str	r3, [r0, #12]
 8000322:	f242 030c 	movw	r3, #8204	; 0x200c
 8000326:	6043      	str	r3, [r0, #4]
 8000328:	6848      	ldr	r0, [r1, #4]
 800032a:	f040 0001 	orr.w	r0, r0, #1
 800032e:	6048      	str	r0, [r1, #4]
 8000330:	f240 000c 	movw	r0, #12
 8000334:	f04f 017a 	mov.w	r1, #122	; 0x7a
 8000338:	f2c4 0000 	movt	r0, #16384	; 0x4000
 800033c:	61c1      	str	r1, [r0, #28]
 800033e:	f64f 6110 	movw	r1, #65040	; 0xfe10
 8000342:	6201      	str	r1, [r0, #32]
 8000344:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
 8000348:	600a      	str	r2, [r1, #0]
 800034a:	6802      	ldr	r2, [r0, #0]
 800034c:	f042 0201 	orr.w	r2, r2, #1
 8000350:	6002      	str	r2, [r0, #0]
 8000352:	f04f 0220 	mov.w	r2, #32
 8000356:	6808      	ldr	r0, [r1, #0]
 8000358:	f040 0001 	orr.w	r0, r0, #1
 800035c:	6008      	str	r0, [r1, #0]
 800035e:	f24e 4025 	movw	r0, #58405	; 0xe425
 8000362:	f04f 01f0 	mov.w	r1, #240	; 0xf0
 8000366:	f2ce 0000 	movt	r0, #57344	; 0xe000
 800036a:	7001      	strb	r1, [r0, #0]
 800036c:	f24e 1000 	movw	r0, #57600	; 0xe100
 8000370:	f2ce 0000 	movt	r0, #57344	; 0xe000
 8000374:	6042      	str	r2, [r0, #4]
 8000376:	f880 131c 	strb.w	r1, [r0, #796]	; 0x31c
 800037a:	f04f 5180 	mov.w	r1, #268435456	; 0x10000000
 800037e:	6001      	str	r1, [r0, #0]
 8000380:	d100      	bne.n	8000384 <main+0xf2>
 8000382:	b662      	cpsie	i
 8000384:	f241 0c04 	movw	ip, #4100	; 0x1004
 8000388:	f240 0100 	movw	r1, #0
 800038c:	f2ce 0c00 	movt	ip, #57344	; 0xe000
 8000390:	f2c2 0100 	movt	r1, #8192	; 0x2000
 8000394:	e000      	b.n	8000398 <main+0x106>
 8000396:	b662      	cpsie	i
 8000398:	f3ef 8210 	mrs	r2, PRIMASK
 800039c:	b672      	cpsid	i
 800039e:	f8dc 3000 	ldr.w	r3, [ip]
 80003a2:	bf30      	wfi
 80003a4:	f8dc 0000 	ldr.w	r0, [ip]
 80003a8:	f012 0f01 	tst.w	r2, #1
 80003ac:	eba0 0003 	sub.w	r0, r0, r3
 80003b0:	680b      	ldr	r3, [r1, #0]
 80003b2:	4418      	add	r0, r3
 80003b4:	6008      	str	r0, [r1, #0]
 80003b6:	d1ef      	bne.n	8000398 <main+0x106>
 80003b8:	e7ed      	b.n	8000396 <main+0x104>

080003ba <WWDG>:
 80003ba:	f000 b874 	b.w	80004a6 <DEFAULT_HANDLER>

080003be <PVD>:
 80003be:	f000 b872 	b.w	80004a6 <DEFAULT_HANDLER>

080003c2 <TAMPER>:
 80003c2:	f000 b870 	b.w	80004a6 <DEFAULT_HANDLER>

080003c6 <RTC>:
 80003c6:	f000 b86e 	b.w	80004a6 <DEFAULT_HANDLER>

080003ca <FLASH>:
 80003ca:	f000 b86c 	b.w	80004a6 <DEFAULT_HANDLER>

080003ce <RCC>:
 80003ce:	f000 b86a 	b.w	80004a6 <DEFAULT_HANDLER>

080003d2 <EXTI0>:
 80003d2:	f000 b868 	b.w	80004a6 <DEFAULT_HANDLER>

080003d6 <EXTI1>:
 80003d6:	f000 b866 	b.w	80004a6 <DEFAULT_HANDLER>

080003da <EXTI2>:
 80003da:	f000 b864 	b.w	80004a6 <DEFAULT_HANDLER>

080003de <EXTI3>:
 80003de:	f000 b862 	b.w	80004a6 <DEFAULT_HANDLER>

080003e2 <EXTI4>:
 80003e2:	f000 b860 	b.w	80004a6 <DEFAULT_HANDLER>

080003e6 <DMA1_CHANNEL1>:
 80003e6:	f000 b85e 	b.w	80004a6 <DEFAULT_HANDLER>

080003ea <DMA1_CHANNEL2>:
 80003ea:	f000 b85c 	b.w	80004a6 <DEFAULT_HANDLER>

080003ee <DMA1_CHANNEL3>:
 80003ee:	f000 b85a 	b.w	80004a6 <DEFAULT_HANDLER>

080003f2 <DMA1_CHANNEL4>:
 80003f2:	f000 b858 	b.w	80004a6 <DEFAULT_HANDLER>

080003f6 <DMA1_CHANNEL5>:
 80003f6:	f000 b856 	b.w	80004a6 <DEFAULT_HANDLER>

080003fa <DMA1_CHANNEL6>:
 80003fa:	f000 b854 	b.w	80004a6 <DEFAULT_HANDLER>

080003fe <DMA1_CHANNEL7>:
 80003fe:	f000 b852 	b.w	80004a6 <DEFAULT_HANDLER>

08000402 <ADC>:
 8000402:	f000 b850 	b.w	80004a6 <DEFAULT_HANDLER>

08000406 <CAN1_TX>:
 8000406:	f000 b84e 	b.w	80004a6 <DEFAULT_HANDLER>

0800040a <CAN1_RX0>:
 800040a:	f000 b84c 	b.w	80004a6 <DEFAULT_HANDLER>

0800040e <CAN1_RX1>:
 800040e:	f000 b84a 	b.w	80004a6 <DEFAULT_HANDLER>

08000412 <CAN1_SCE>:
 8000412:	f000 b848 	b.w	80004a6 <DEFAULT_HANDLER>

08000416 <EXTI9_5>:
 8000416:	f000 b846 	b.w	80004a6 <DEFAULT_HANDLER>

0800041a <TIM1_BRK_TIM9>:
 800041a:	f000 b844 	b.w	80004a6 <DEFAULT_HANDLER>

0800041e <TIM1_UP_TIM10>:
 800041e:	f000 b842 	b.w	80004a6 <DEFAULT_HANDLER>

08000422 <TIM1_TRG_COM_TIM11>:
 8000422:	f000 b840 	b.w	80004a6 <DEFAULT_HANDLER>

08000426 <TIM1_CC>:
 8000426:	f000 b83e 	b.w	80004a6 <DEFAULT_HANDLER>

0800042a <TIM3>:
 800042a:	f000 b83c 	b.w	80004a6 <DEFAULT_HANDLER>

0800042e <TIM4>:
 800042e:	f000 b83a 	b.w	80004a6 <DEFAULT_HANDLER>

08000432 <I2C1_EV>:
 8000432:	f000 b838 	b.w	80004a6 <DEFAULT_HANDLER>

08000436 <I2C1_ER>:
 8000436:	f000 b836 	b.w	80004a6 <DEFAULT_HANDLER>

0800043a <I2C2_EV>:
 800043a:	f000 b834 	b.w	80004a6 <DEFAULT_HANDLER>

0800043e <I2C2_ER>:
 800043e:	f000 b832 	b.w	80004a6 <DEFAULT_HANDLER>

08000442 <SPI1>:
 8000442:	f000 b830 	b.w	80004a6 <DEFAULT_HANDLER>

08000446 <SPI2>:
 8000446:	f000 b82e 	b.w	80004a6 <DEFAULT_HANDLER>

0800044a <USART2>:
 800044a:	f000 b82c 	b.w	80004a6 <DEFAULT_HANDLER>

0800044e <USART3>:
 800044e:	f000 b82a 	b.w	80004a6 <DEFAULT_HANDLER>

08000452 <EXTI15_10>:
 8000452:	f000 b828 	b.w	80004a6 <DEFAULT_HANDLER>

08000456 <RTCALARM>:
 8000456:	f000 b826 	b.w	80004a6 <DEFAULT_HANDLER>

0800045a <USB_FS_WKUP>:
 800045a:	f000 b824 	b.w	80004a6 <DEFAULT_HANDLER>

0800045e <TIM8_BRK_TIM12>:
 800045e:	f000 b822 	b.w	80004a6 <DEFAULT_HANDLER>

08000462 <TIM8_UP_TIM13>:
 8000462:	f000 b820 	b.w	80004a6 <DEFAULT_HANDLER>

08000466 <TIM8_TRG_COM_TIM14>:
 8000466:	f000 b81e 	b.w	80004a6 <DEFAULT_HANDLER>

0800046a <TIM8_CC>:
 800046a:	f000 b81c 	b.w	80004a6 <DEFAULT_HANDLER>

0800046e <ADC3>:
 800046e:	f000 b81a 	b.w	80004a6 <DEFAULT_HANDLER>

08000472 <FSMC>:
 8000472:	f000 b818 	b.w	80004a6 <DEFAULT_HANDLER>

08000476 <SDIO>:
 8000476:	f000 b816 	b.w	80004a6 <DEFAULT_HANDLER>

0800047a <TIM5>:
 800047a:	f000 b814 	b.w	80004a6 <DEFAULT_HANDLER>

0800047e <SPI3>:
 800047e:	f000 b812 	b.w	80004a6 <DEFAULT_HANDLER>

08000482 <UART4>:
 8000482:	f000 b810 	b.w	80004a6 <DEFAULT_HANDLER>

08000486 <UART5>:
 8000486:	f000 b80e 	b.w	80004a6 <DEFAULT_HANDLER>

0800048a <TIM6>:
 800048a:	f000 b80c 	b.w	80004a6 <DEFAULT_HANDLER>

0800048e <TIM7>:
 800048e:	f000 b80a 	b.w	80004a6 <DEFAULT_HANDLER>

08000492 <DMA2_CHANNEL1>:
 8000492:	f000 b808 	b.w	80004a6 <DEFAULT_HANDLER>

08000496 <DMA2_CHANNEL2>:
 8000496:	f000 b806 	b.w	80004a6 <DEFAULT_HANDLER>

0800049a <DMA2_CHANNEL3>:
 800049a:	f000 b804 	b.w	80004a6 <DEFAULT_HANDLER>

0800049e <DMA2_CHANNEL4_5>:
 800049e:	f000 b802 	b.w	80004a6 <DEFAULT_HANDLER>

080004a2 <cortex_m_rt::default_handler>:
 80004a2:	be00      	bkpt	0x0000
 80004a4:	e7fe      	b.n	80004a4 <cortex_m_rt::default_handler+0x2>

080004a6 <DEFAULT_HANDLER>:
 80004a6:	f3ef 8008 	mrs	r0, MSP
 80004aa:	f7ff bffa 	b.w	80004a2 <cortex_m_rt::default_handler>

080004ae <NMI>:
 80004ae:	f7ff bffa 	b.w	80004a6 <DEFAULT_HANDLER>

080004b2 <HARD_FAULT>:
 80004b2:	f7ff bff8 	b.w	80004a6 <DEFAULT_HANDLER>

080004b6 <MEM_MANAGE>:
 80004b6:	f7ff bff6 	b.w	80004a6 <DEFAULT_HANDLER>

080004ba <BUS_FAULT>:
 80004ba:	f7ff bff4 	b.w	80004a6 <DEFAULT_HANDLER>

080004be <USAGE_FAULT>:
 80004be:	f7ff bff2 	b.w	80004a6 <DEFAULT_HANDLER>

080004c2 <SVCALL>:
 80004c2:	f7ff bff0 	b.w	80004a6 <DEFAULT_HANDLER>

080004c6 <PENDSV>:
 80004c6:	f7ff bfee 	b.w	80004a6 <DEFAULT_HANDLER>

080004ca <SYS_TICK>:
 80004ca:	f7ff bfec 	b.w	80004a6 <DEFAULT_HANDLER>

080004ce <core::panicking::panic_fmt>:
 80004ce:	defe      	udf	#254	; 0xfe

080004d0 <__aeabi_memcpy>:
 80004d0:	2a00      	cmp	r2, #0
 80004d2:	bf08      	it	eq
 80004d4:	4770      	bxeq	lr
 80004d6:	f811 3b01 	ldrb.w	r3, [r1], #1
 80004da:	3a01      	subs	r2, #1
 80004dc:	f800 3b01 	strb.w	r3, [r0], #1
 80004e0:	d1f9      	bne.n	80004d6 <__aeabi_memcpy+0x6>
 80004e2:	4770      	bx	lr

080004e4 <__aeabi_memcpy4>:
 80004e4:	468c      	mov	ip, r1
 80004e6:	4603      	mov	r3, r0
 80004e8:	2a04      	cmp	r2, #4
 80004ea:	d316      	bcc.n	800051a <__aeabi_memcpy4+0x36>
 80004ec:	b5b0      	push	{r4, r5, r7, lr}
 80004ee:	af02      	add	r7, sp, #8
 80004f0:	f1a2 0e04 	sub.w	lr, r2, #4
 80004f4:	f02e 0403 	bic.w	r4, lr, #3
 80004f8:	1d20      	adds	r0, r4, #4
 80004fa:	eb0c 0100 	add.w	r1, ip, r0
 80004fe:	4418      	add	r0, r3
 8000500:	f85c 5b04 	ldr.w	r5, [ip], #4
 8000504:	3a04      	subs	r2, #4
 8000506:	2a03      	cmp	r2, #3
 8000508:	f843 5b04 	str.w	r5, [r3], #4
 800050c:	d8f8      	bhi.n	8000500 <__aeabi_memcpy4+0x1c>
 800050e:	ebae 0204 	sub.w	r2, lr, r4
 8000512:	e8bd 40b0 	ldmia.w	sp!, {r4, r5, r7, lr}
 8000516:	f7ff bfdb 	b.w	80004d0 <__aeabi_memcpy>
 800051a:	4618      	mov	r0, r3
 800051c:	4661      	mov	r1, ip
 800051e:	f7ff bfd7 	b.w	80004d0 <__aeabi_memcpy>

08000522 <__aeabi_memset>:
 8000522:	2900      	cmp	r1, #0
 8000524:	bf08      	it	eq
 8000526:	4770      	bxeq	lr
 8000528:	f800 2b01 	strb.w	r2, [r0], #1
 800052c:	3901      	subs	r1, #1
 800052e:	d1fb      	bne.n	8000528 <__aeabi_memset+0x6>
 8000530:	4770      	bx	lr

08000532 <__aeabi_memset4>:
 8000532:	4613      	mov	r3, r2
 8000534:	2904      	cmp	r1, #4
 8000536:	b2da      	uxtb	r2, r3
 8000538:	bf38      	it	cc
 800053a:	f7ff bff2 	bcc.w	8000522 <__aeabi_memset>
 800053e:	b5b0      	push	{r4, r5, r7, lr}
 8000540:	af02      	add	r7, sp, #8
 8000542:	f1a1 0e04 	sub.w	lr, r1, #4
 8000546:	ea42 6303 	orr.w	r3, r2, r3, lsl #24
 800054a:	f02e 0503 	bic.w	r5, lr, #3
 800054e:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000552:	1944      	adds	r4, r0, r5
 8000554:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
 8000558:	f104 0c04 	add.w	ip, r4, #4
 800055c:	3904      	subs	r1, #4
 800055e:	f840 3b04 	str.w	r3, [r0], #4
 8000562:	2903      	cmp	r1, #3
 8000564:	d8fa      	bhi.n	800055c <__aeabi_memset4+0x2a>
 8000566:	ebae 0105 	sub.w	r1, lr, r5
 800056a:	e8bd 40b0 	ldmia.w	sp!, {r4, r5, r7, lr}
 800056e:	4660      	mov	r0, ip
 8000570:	f7ff bfd7 	b.w	8000522 <__aeabi_memset>

08000574 <__aeabi_memclr4>:
 8000574:	2200      	movs	r2, #0
 8000576:	f7ff bfdc 	b.w	8000532 <__aeabi_memset4>