Euclidean GCD in hardware

euclidean_gcd.v

`default_nettype none

module euclidean_gcd(
  input  wire clk,
  input  wire start,
  input  wire [31:0] A,
  input  wire [31:0] B,
  output reg  [31:0] R,
  output wire valid_out
);

reg working = 0;

reg [31:0] X;
reg [31:0] Y;

assign valid_out = ~working;

always @(posedge clk) begin
  if(!working) begin
    if(start) begin
      X <= A;
      Y <= B;
      working <= 1;
    end
  end else begin // working
    if(X == Y) begin
        R <= X;
        working <= 0;
    end else if (X > Y) begin
        X <= X - Y;
    end else begin // X < Y
        Y <= Y - X;
    end
  end
end // always


endmodule