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Murax arty_a7 Vivado 2018.3
Raw
1_synth_runme.log
*** Running vivado
with args -log toplevel.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source toplevel.tcl
****** Vivado v2018.3 (64-bit)
**** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source toplevel.tcl -notrace
Command: synth_design -top toplevel -part xc7a35ticsg324-1L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 2535
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1352.465 ; gain = 0.000 ; free physical = 10878 ; free virtual = 12774
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'toplevel' [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:3]
INFO: [Synth 8-6157] synthesizing module 'Murax' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5804]
INFO: [Synth 8-6157] synthesizing module 'BufferCC_3_' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1047]
INFO: [Synth 8-6155] done synthesizing module 'BufferCC_3_' (1#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1047]
INFO: [Synth 8-6157] synthesizing module 'MuraxMasterArbiter' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1061]
INFO: [Synth 8-6155] done synthesizing module 'MuraxMasterArbiter' (2#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1061]
INFO: [Synth 8-6157] synthesizing module 'VexRiscv' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1154]
INFO: [Synth 8-6157] synthesizing module 'StreamFifoLowLatency' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:534]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifoLowLatency' (3#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:534]
WARNING: [Synth 8-6014] Unused sequential element IBusSimplePlugin_injector_nextPcCalc_valids_3_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:3095]
WARNING: [Synth 8-6014] Unused sequential element IBusSimplePlugin_injector_nextPcCalc_valids_4_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:3096]
WARNING: [Synth 8-6014] Unused sequential element IBusSimplePlugin_injector_nextPcCalc_valids_5_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:3097]
WARNING: [Synth 8-6014] Unused sequential element execute_CsrPlugin_wfiWake_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:3886]
WARNING: [Synth 8-6014] Unused sequential element _zz_57__reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:3091]
WARNING: [Synth 8-6014] Unused sequential element _zz_59__reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:3093]
WARNING: [Synth 8-6014] Unused sequential element IBusSimplePlugin_injector_formal_rawInDecode_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4122]
WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_mcycle_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4133]
WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_minstret_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4135]
WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_FORMAL_PC_NEXT_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2678]
WARNING: [Synth 8-6014] Unused sequential element execute_to_memory_FORMAL_PC_NEXT_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2677]
WARNING: [Synth 8-6014] Unused sequential element memory_to_writeBack_FORMAL_PC_NEXT_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2676]
WARNING: [Synth 8-6014] Unused sequential element memory_to_writeBack_MEMORY_STORE_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2749]
WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_BYPASSABLE_EXECUTE_STAGE_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2693]
WARNING: [Synth 8-6014] Unused sequential element execute_to_memory_PC_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2657]
WARNING: [Synth 8-6014] Unused sequential element memory_to_writeBack_PC_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2777]
WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_CSR_READ_OPCODE_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2743]
WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_BYPASSABLE_MEMORY_STAGE_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2646]
WARNING: [Synth 8-6014] Unused sequential element execute_to_memory_BYPASSABLE_MEMORY_STAGE_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:2696]
WARNING: [Synth 8-6014] Unused sequential element DebugPlugin_firstCycle_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4321]
WARNING: [Synth 8-6014] Unused sequential element DebugPlugin_secondCycle_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4325]
WARNING: [Synth 8-6014] Unused sequential element DebugPlugin_godmode_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4342]
WARNING: [Synth 8-3936] Found unconnected internal register 'execute_CsrPlugin_writeData_reg' and it is trimmed from '32' to '13' bits. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1975]
INFO: [Synth 8-6155] done synthesizing module 'VexRiscv' (4#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1154]
INFO: [Synth 8-6157] synthesizing module 'JtagBridge' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4395]
INFO: [Synth 8-6157] synthesizing module 'FlowCCByToggle' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:660]
INFO: [Synth 8-6157] synthesizing module 'BufferCC_1_' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:106]
INFO: [Synth 8-6155] done synthesizing module 'BufferCC_1_' (5#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:106]
INFO: [Synth 8-6155] done synthesizing module 'FlowCCByToggle' (6#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:660]
INFO: [Synth 8-6155] done synthesizing module 'JtagBridge' (7#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4395]
INFO: [Synth 8-6157] synthesizing module 'SystemDebugger' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4687]
INFO: [Synth 8-6155] done synthesizing module 'SystemDebugger' (8#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4687]
INFO: [Synth 8-6157] synthesizing module 'MuraxPipelinedMemoryBusRam' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4766]
INFO: [Synth 8-3876] $readmem data file 'Murax.v_toplevel_system_ram_ram_symbol0.bin' is read successfully [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4792]
INFO: [Synth 8-3876] $readmem data file 'Murax.v_toplevel_system_ram_ram_symbol1.bin' is read successfully [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4793]
INFO: [Synth 8-3876] $readmem data file 'Murax.v_toplevel_system_ram_ram_symbol2.bin' is read successfully [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4794]
INFO: [Synth 8-3876] $readmem data file 'Murax.v_toplevel_system_ram_ram_symbol3.bin' is read successfully [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4795]
INFO: [Synth 8-6155] done synthesizing module 'MuraxPipelinedMemoryBusRam' (9#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4766]
INFO: [Synth 8-6157] synthesizing module 'PipelinedMemoryBusToApbBridge' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4839]
WARNING: [Synth 8-6014] Unused sequential element io_pipelinedMemoryBus_cmd_halfPipe_regs_payload_mask_reg was removed. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4889]
INFO: [Synth 8-6155] done synthesizing module 'PipelinedMemoryBusToApbBridge' (10#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4839]
INFO: [Synth 8-6157] synthesizing module 'Apb3Gpio' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4960]
INFO: [Synth 8-6157] synthesizing module 'BufferCC_2_' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:720]
INFO: [Synth 8-6155] done synthesizing module 'BufferCC_2_' (11#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:720]
INFO: [Synth 8-6155] done synthesizing module 'Apb3Gpio' (12#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4960]
INFO: [Synth 8-6157] synthesizing module 'Apb3UartCtrl' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5052]
INFO: [Synth 8-6157] synthesizing module 'UartCtrl' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:735]
INFO: [Synth 8-6157] synthesizing module 'UartCtrlTx' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:121]
INFO: [Synth 8-6155] done synthesizing module 'UartCtrlTx' (13#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:121]
INFO: [Synth 8-6157] synthesizing module 'UartCtrlRx' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:330]
INFO: [Synth 8-6157] synthesizing module 'BufferCC' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:85]
WARNING: [Synth 8-5788] Register buffers_0_reg in module BufferCC is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/vm/fpga/Spinal/VexRiscv/Murax.v:96]
WARNING: [Synth 8-5788] Register buffers_1_reg in module BufferCC is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/vm/fpga/Spinal/VexRiscv/Murax.v:93]
INFO: [Synth 8-6155] done synthesizing module 'BufferCC' (14#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:85]
INFO: [Synth 8-6155] done synthesizing module 'UartCtrlRx' (15#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:330]
INFO: [Synth 8-6155] done synthesizing module 'UartCtrl' (16#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:735]
INFO: [Synth 8-6157] synthesizing module 'StreamFifo' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:819]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifo' (17#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:819]
INFO: [Synth 8-6155] done synthesizing module 'Apb3UartCtrl' (18#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5052]
INFO: [Synth 8-6157] synthesizing module 'MuraxApb3Timer' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5268]
INFO: [Synth 8-6157] synthesizing module 'Prescaler' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:966]
INFO: [Synth 8-6155] done synthesizing module 'Prescaler' (19#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:966]
INFO: [Synth 8-6157] synthesizing module 'Timer' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:983]
INFO: [Synth 8-6155] done synthesizing module 'Timer' (20#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:983]
INFO: [Synth 8-6157] synthesizing module 'InterruptCtrl' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1028]
INFO: [Synth 8-6155] done synthesizing module 'InterruptCtrl' (21#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:1028]
INFO: [Synth 8-6155] done synthesizing module 'MuraxApb3Timer' (22#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5268]
INFO: [Synth 8-6157] synthesizing module 'Apb3Decoder' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5671]
INFO: [Synth 8-6155] done synthesizing module 'Apb3Decoder' (23#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5671]
INFO: [Synth 8-6157] synthesizing module 'Apb3Router' [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5717]
INFO: [Synth 8-6155] done synthesizing module 'Apb3Router' (24#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5717]
INFO: [Synth 8-6155] done synthesizing module 'Murax' (25#1) [/home/vm/fpga/Spinal/VexRiscv/Murax.v:5804]
INFO: [Synth 8-6155] done synthesizing module 'toplevel' (26#1) [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:3]
WARNING: [Synth 8-3331] design Apb3Router has unconnected port resetCtrl_systemReset
WARNING: [Synth 8-3331] design Prescaler has unconnected port resetCtrl_systemReset
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[31]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[30]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[29]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[28]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[27]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[26]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[25]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[24]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[23]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[22]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[21]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[20]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[19]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[18]
WARNING: [Synth 8-3331] design MuraxApb3Timer has unconnected port io_apb_PWDATA[17]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[31]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[30]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[29]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[28]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[27]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[26]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[25]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[24]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[23]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[22]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[21]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[20]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[19]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[18]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[17]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[16]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[15]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[14]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[13]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[12]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[11]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[10]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[9]
WARNING: [Synth 8-3331] design Apb3UartCtrl has unconnected port io_apb_PWDATA[8]
WARNING: [Synth 8-3331] design BufferCC_2_ has unconnected port resetCtrl_systemReset
WARNING: [Synth 8-3331] design PipelinedMemoryBusToApbBridge has unconnected port io_pipelinedMemoryBus_cmd_payload_mask[3]
WARNING: [Synth 8-3331] design PipelinedMemoryBusToApbBridge has unconnected port io_pipelinedMemoryBus_cmd_payload_mask[2]
WARNING: [Synth 8-3331] design PipelinedMemoryBusToApbBridge has unconnected port io_pipelinedMemoryBus_cmd_payload_mask[1]
WARNING: [Synth 8-3331] design PipelinedMemoryBusToApbBridge has unconnected port io_pipelinedMemoryBus_cmd_payload_mask[0]
WARNING: [Synth 8-3331] design PipelinedMemoryBusToApbBridge has unconnected port io_apb_PSLVERROR
WARNING: [Synth 8-3331] design SystemDebugger has unconnected port io_remote_rsp_ready
WARNING: [Synth 8-3331] design BufferCC_1_ has unconnected port resetCtrl_mainClkReset
WARNING: [Synth 8-3331] design JtagBridge has unconnected port io_remote_cmd_ready
WARNING: [Synth 8-3331] design VexRiscv has unconnected port debug_bus_cmd_payload_address[1]
WARNING: [Synth 8-3331] design VexRiscv has unconnected port debug_bus_cmd_payload_address[0]
WARNING: [Synth 8-3331] design VexRiscv has unconnected port dBus_rsp_error
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1368.074 ; gain = 15.609 ; free physical = 10874 ; free virtual = 12772
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[31] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[30] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[29] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[28] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[27] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[26] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[25] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[24] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[23] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[22] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[21] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[20] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[19] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[18] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[17] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[16] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[15] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[14] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[13] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
WARNING: [Synth 8-3295] tying undriven pin core:io_gpioA_read[12] to constant 0 [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/toplevel.v:53]
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1368.074 ; gain = 15.609 ; free physical = 10878 ; free virtual = 12776
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1368.074 ; gain = 15.609 ; free physical = 10878 ; free virtual = 12776
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc]
Finished Parsing XDC File [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toplevel_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/toplevel_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1694.488 ; gain = 0.000 ; free physical = 10584 ; free virtual = 12518
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1694.488 ; gain = 0.000 ; free physical = 10585 ; free virtual = 12519
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1694.488 ; gain = 0.000 ; free physical = 10585 ; free virtual = 12519
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1694.488 ; gain = 0.000 ; free physical = 10585 ; free virtual = 12519
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1694.488 ; gain = 342.023 ; free physical = 10665 ; free virtual = 12600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35ticsg324-1L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1694.488 ; gain = 342.023 ; free physical = 10665 ; free virtual = 12600
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1694.488 ; gain = 342.023 ; free physical = 10667 ; free virtual = 12602
---------------------------------------------------------------------------------
INFO: [Synth 8-5544] ROM "CsrPlugin_mstatus_MIE" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "decode_REGFILE_WRITE_VALID" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "CsrPlugin_mstatus_MIE" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "decode_REGFILE_WRITE_VALID" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "decode_arbitration_haltItself" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "IBusSimplePlugin_injectionPort_ready" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_165_" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CsrPlugin_interrupt_code" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "execute_to_memory_BRANCH_CALC" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register '_zz_108__reg' in module 'VexRiscv'
INFO: [Synth 8-802] inferred FSM for state register 'jtag_tap_fsm_state_reg' in module 'JtagBridge'
INFO: [Synth 8-5544] ROM "jtag_writeArea_source_valid" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "jtag_tap_instruction" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "jtag_tap_instructionShift" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "jtag_tap_instruction" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "jtag_readArea_shifter" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_zz_1_0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "dispatcher_headerLoaded" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
WARNING: [Synth 8-3936] Found unconnected internal register 'io_pipelinedMemoryBus_cmd_halfPipe_regs_payload_address_reg' and it is trimmed from '32' to '20' bits. [/home/vm/fpga/Spinal/VexRiscv/Murax.v:4887]
INFO: [Synth 8-802] inferred FSM for state register 'stateMachine_state_reg' in module 'UartCtrlTx'
INFO: [Synth 8-5544] ROM "stateMachine_state" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "stateMachine_state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'stateMachine_state_reg' in module 'UartCtrlRx'
INFO: [Synth 8-5544] ROM "stateMachine_validReg" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "stateMachine_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "stateMachine_state" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "stateMachine_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 000 | 000
iSTATE0 | 001 | 001
iSTATE1 | 010 | 010
iSTATE2 | 011 | 011
iSTATE3 | 100 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register '_zz_108__reg' using encoding 'sequential' in module 'VexRiscv'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0000 | 0000
*
iSTATE1 | 0001 | 0001
iSTATE7 | 0010 | 1001
iSTATE0 | 0011 | 0010
iSTATE | 0100 | 0011
iSTATE11 | 0101 | 0100
iSTATE9 | 0110 | 0101
iSTATE6 | 0111 | 0110
iSTATE5 | 1000 | 0111
iSTATE8 | 1001 | 1000
iSTATE4 | 1010 | 1010
iSTATE3 | 1011 | 1011
iSTATE14 | 1100 | 1100
iSTATE13 | 1101 | 1101
iSTATE12 | 1110 | 1110
iSTATE10 | 1111 | 1111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'jtag_tap_fsm_state_reg' using encoding 'sequential' in module 'JtagBridge'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 000 | 000
iSTATE3 | 001 | 001
iSTATE | 010 | 010
iSTATE0 | 011 | 011
iSTATE1 | 100 | 100
*
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'stateMachine_state_reg' using encoding 'sequential' in module 'UartCtrlTx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 000 | 000
iSTATE | 001 | 001
iSTATE0 | 010 | 010
iSTATE1 | 011 | 011
iSTATE3 | 100 | 100
*
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'stateMachine_state_reg' using encoding 'sequential' in module 'UartCtrlRx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1694.488 ; gain = 342.023 ; free physical = 10658 ; free virtual = 12593
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
3 Input 32 Bit Adders := 1
2 Input 32 Bit Adders := 2
2 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 2
2 Input 4 Bit Adders := 4
3 Input 4 Bit Adders := 4
4 Input 3 Bit Adders := 1
3 Input 3 Bit Adders := 1
2 Input 3 Bit Adders := 5
2 Input 1 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
2 Input 1 Bit XORs := 2
+---Registers :
67 Bit Registers := 1
34 Bit Registers := 1
33 Bit Registers := 1
32 Bit Registers := 30
20 Bit Registers := 1
16 Bit Registers := 3
8 Bit Registers := 8
6 Bit Registers := 1
5 Bit Registers := 2
4 Bit Registers := 8
3 Bit Registers := 7
2 Bit Registers := 14
1 Bit Registers := 107
+---RAMs :
8K Bit RAMs := 4
1024 Bit RAMs := 1
128 Bit RAMs := 2
+---Muxes :
2 Input 34 Bit Muxes := 1
2 Input 32 Bit Muxes := 28
4 Input 32 Bit Muxes := 3
5 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 3
10 Input 32 Bit Muxes := 1
2 Input 25 Bit Muxes := 1
2 Input 13 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
5 Input 8 Bit Muxes := 1
2 Input 5 Bit Muxes := 3
2 Input 4 Bit Muxes := 20
4 Input 4 Bit Muxes := 2
5 Input 4 Bit Muxes := 1
16 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 6
2 Input 3 Bit Muxes := 14
2 Input 2 Bit Muxes := 6
10 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 165
5 Input 1 Bit Muxes := 16
4 Input 1 Bit Muxes := 6
7 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 3
10 Input 1 Bit Muxes := 13
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module BufferCC_3_
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module MuraxMasterArbiter
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module StreamFifoLowLatency
Detailed RTL Component Info :
+---Registers :
33 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
Module VexRiscv
Detailed RTL Component Info :
+---Adders :
3 Input 32 Bit Adders := 1
2 Input 32 Bit Adders := 2
2 Input 5 Bit Adders := 1
4 Input 3 Bit Adders := 1
3 Input 3 Bit Adders := 1
2 Input 1 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
+---Registers :
32 Bit Registers := 20
5 Bit Registers := 2
4 Bit Registers := 2
3 Bit Registers := 2
2 Bit Registers := 8
1 Bit Registers := 51
+---RAMs :
1024 Bit RAMs := 1
+---Muxes :
2 Input 32 Bit Muxes := 21
4 Input 32 Bit Muxes := 3
5 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 2
2 Input 25 Bit Muxes := 1
2 Input 13 Bit Muxes := 2
2 Input 5 Bit Muxes := 3
4 Input 4 Bit Muxes := 1
5 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 4
2 Input 1 Bit Muxes := 101
5 Input 1 Bit Muxes := 4
4 Input 1 Bit Muxes := 1
7 Input 1 Bit Muxes := 1
Module BufferCC_1_
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module FlowCCByToggle
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module JtagBridge
Detailed RTL Component Info :
+---Registers :
34 Bit Registers := 1
32 Bit Registers := 2
4 Bit Registers := 2
1 Bit Registers := 4
+---Muxes :
2 Input 34 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
16 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 16
2 Input 1 Bit Muxes := 9
4 Input 1 Bit Muxes := 3
Module SystemDebugger
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
67 Bit Registers := 1
8 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 6
Module MuraxPipelinedMemoryBusRam
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 4
1 Bit Registers := 1
+---RAMs :
8K Bit RAMs := 4
Module PipelinedMemoryBusToApbBridge
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 2
20 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 1 Bit Muxes := 3
Module BufferCC_2_
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 2
Module Apb3Gpio
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 2
+---Muxes :
4 Input 1 Bit Muxes := 2
Module UartCtrlTx
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
3 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
2 Input 3 Bit Muxes := 5
5 Input 3 Bit Muxes := 2
2 Input 1 Bit Muxes := 3
5 Input 1 Bit Muxes := 6
Module BufferCC
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module UartCtrlRx
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
8 Bit Registers := 1
3 Bit Registers := 2
1 Bit Registers := 6
+---Muxes :
2 Input 8 Bit Muxes := 1
5 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 7
5 Input 3 Bit Muxes := 3
2 Input 1 Bit Muxes := 6
5 Input 1 Bit Muxes := 6
Module StreamFifo
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 2
3 Input 4 Bit Adders := 2
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 2
+---RAMs :
128 Bit RAMs := 1
+---Muxes :
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module Apb3UartCtrl
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 3
Module Timer
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module InterruptCtrl
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module MuraxApb3Timer
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 3
2 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
10 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
10 Input 2 Bit Muxes := 1
10 Input 1 Bit Muxes := 13
2 Input 1 Bit Muxes := 15
Module Apb3Decoder
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 2
Module Apb3Router
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module Murax
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
6 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 10
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-5544] ROM "core/systemDebugger_1_/dispatcher_headerLoaded" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
WARNING: [Synth 8-3331] design VexRiscv has unconnected port debug_bus_cmd_payload_address[1]
WARNING: [Synth 8-3331] design VexRiscv has unconnected port debug_bus_cmd_payload_address[0]
WARNING: [Synth 8-3331] design VexRiscv has unconnected port dBus_rsp_error
INFO: [Synth 8-3971] The signal core/system_cpu/RegFilePlugin_regFile_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3886] merging instance 'core/system_cpu/CsrPlugin_interrupt_code_reg[0]' (FDSE) to 'core/system_cpu/CsrPlugin_interrupt_code_reg[1]'
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\core/system_cpu/CsrPlugin_interrupt_code_reg[1] )
INFO: [Synth 8-3886] merging instance 'core/system_cpu/CsrPlugin_mcause_exceptionCode_reg[0]' (FDE) to 'core/system_cpu/CsrPlugin_mcause_exceptionCode_reg[1]'
INFO: [Synth 8-3886] merging instance 'core/system_cpu/decode_to_execute_ALU_BITWISE_CTRL_reg[1]' (FDE) to 'core/system_cpu/decode_to_execute_INSTRUCTION_reg[12]'
INFO: [Synth 8-3886] merging instance 'core/system_cpu/IBusSimplePlugin_fetchPc_pcReg_reg[0]' (FDCE) to 'core/system_cpu/IBusSimplePlugin_fetchPc_pcReg_reg[1]'
INFO: [Synth 8-3886] merging instance 'core/system_cpu/_zz_54__reg[1]' (FDE) to 'core/system_cpu/_zz_54__reg[0]'
INFO: [Synth 8-3886] merging instance 'core/system_cpu/CsrPlugin_interrupt_targetPrivilege_reg[0]' (FDSE) to 'core/system_cpu/CsrPlugin_interrupt_targetPrivilege_reg[1]'
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\core/system_cpu/CsrPlugin_interrupt_targetPrivilege_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\core/system_cpu/IBusSimplePlugin_fetchPc_pcReg_reg[1] )
INFO: [Synth 8-3886] merging instance 'core/system_cpu/_zz_56__reg[1]' (FDE) to 'core/system_cpu/_zz_56__reg[0]'
INFO: [Synth 8-3886] merging instance 'core/system_cpu/decode_to_execute_INSTRUCTION_reg[5]' (FDE) to 'core/system_cpu/decode_to_execute_MEMORY_STORE_reg'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\core/system_cpu/CsrPlugin_hadException_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\core/jtagBridge_1_/system_rsp_payload_error_reg )
INFO: [Synth 8-3886] merging instance 'core/system_cpu/execute_to_memory_INSTRUCTION_reg[5]' (FDE) to 'core/system_cpu/execute_to_memory_MEMORY_STORE_reg'
INFO: [Synth 8-3886] merging instance 'core/system_cpu/CsrPlugin_mcause_interrupt_reg' (FDE) to 'core/system_cpu/CsrPlugin_mcause_exceptionCode_reg[1]'
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\core/system_cpu/CsrPlugin_mcause_exceptionCode_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\core/system_cpu/_zz_54__reg[0] )
INFO: [Synth 8-3886] merging instance 'core/system_cpu/decode_to_execute_PC_reg[0]' (FDE) to 'core/system_cpu/decode_to_execute_PC_reg[1]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\core/system_cpu/_zz_56__reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\core/system_cpu/decode_to_execute_PC_reg[1] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1694.488 ; gain = 342.023 ; free physical = 10624 ; free virtual = 12566
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Preliminary Mapping Report (see note below)
+----------------------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+----------------------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|MuraxPipelinedMemoryBusRam: | ram_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MuraxPipelinedMemoryBusRam: | ram_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MuraxPipelinedMemoryBusRam: | ram_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MuraxPipelinedMemoryBusRam: | ram_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
+----------------------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-------------------------------------------------------------------------------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-------------------------------------------------------------------------------------+-----------+----------------------+--------------+
|toplevel | core/system_uartCtrl/bridge_write_streamUnbuffered_queueWithOccupancy/logic_ram_reg | Implied | 16 x 8 | RAM32M x 2 |
|toplevel | core/system_uartCtrl/uartCtrl_1__io_read_queueWithOccupancy/logic_ram_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-------------------------------------------------------------------------------------+-----------+----------------------+--------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
INFO: [Synth 8-6837] The timing for the instance core/system_cpu/i_/i_/i_/core/system_cpu/RegFilePlugin_regFile_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance core/system_cpu/i_/i_/i_/core/system_cpu/RegFilePlugin_regFile_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance i_85/core/system_ram/ram_symbol0_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance i_86/core/system_ram/ram_symbol1_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance i_87/core/system_ram/ram_symbol2_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance i_88/core/system_ram/ram_symbol3_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 1694.488 ; gain = 342.023 ; free physical = 10484 ; free virtual = 12441
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1766.957 ; gain = 414.492 ; free physical = 10395 ; free virtual = 12360
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+----------------------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+----------------------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|MuraxPipelinedMemoryBusRam: | ram_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MuraxPipelinedMemoryBusRam: | ram_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MuraxPipelinedMemoryBusRam: | ram_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MuraxPipelinedMemoryBusRam: | ram_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
+----------------------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Distributed RAM: Final Mapping Report
+------------+-------------------------------------------------------------------------------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-------------------------------------------------------------------------------------+-----------+----------------------+--------------+
|toplevel | core/system_uartCtrl/bridge_write_streamUnbuffered_queueWithOccupancy/logic_ram_reg | Implied | 16 x 8 | RAM32M x 2 |
|toplevel | core/system_uartCtrl/uartCtrl_1__io_read_queueWithOccupancy/logic_ram_reg | Implied | 16 x 8 | RAM32M x 2 |
+------------+-------------------------------------------------------------------------------------+-----------+----------------------+--------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-6837] The timing for the instance core/system_cpu/RegFilePlugin_regFile_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance core/system_cpu/RegFilePlugin_regFile_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance core/system_ram/ram_symbol0_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance core/system_ram/ram_symbol1_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance core/system_ram/ram_symbol2_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-6837] The timing for the instance core/system_ram/ram_symbol3_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+------------+-------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+------------+-------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|toplevel | core/systemDebugger_1_/dispatcher_dataShifter_reg[64] | 3 | 1 | NO | NO | YES | 1 | 0 |
|toplevel | core/systemDebugger_1_/dispatcher_dataShifter_reg[7] | 27 | 1 | NO | NO | YES | 0 | 1 |
+------------+-------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----------+------+
| |Cell |Count |
+------+-----------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 50|
|3 |LUT1 | 6|
|4 |LUT2 | 75|
|5 |LUT3 | 231|
|6 |LUT4 | 155|
|7 |LUT5 | 205|
|8 |LUT6 | 465|
|9 |MUXF7 | 6|
|10 |RAM32M | 4|
|11 |RAMB18E1 | 2|
|12 |RAMB18E1_1 | 1|
|13 |RAMB18E1_2 | 1|
|14 |RAMB18E1_3 | 1|
|15 |RAMB18E1_4 | 1|
|16 |SRL16E | 1|
|17 |SRLC32E | 1|
|18 |FDCE | 219|
|19 |FDPE | 10|
|20 |FDRE | 998|
|21 |FDSE | 36|
|22 |IBUF | 15|
|23 |OBUF | 6|
+------+-----------+------+
Report Instance Areas:
+------+-------------------------------------------------------+------------------------------+------+
| |Instance |Module |Cells |
+------+-------------------------------------------------------+------------------------------+------+
|1 |top | | 2491|
|2 | core |Murax | 2468|
|3 | apb3Router_1_ |Apb3Router | 5|
|4 | io_asyncReset_buffercc |BufferCC_3_ | 3|
|5 | jtagBridge_1_ |JtagBridge | 180|
|6 | flowCCByToggle_1_ |FlowCCByToggle | 16|
|7 | inputArea_target_buffercc |BufferCC_1_ | 3|
|8 | systemDebugger_1_ |SystemDebugger | 67|
|9 | system_apbBridge |PipelinedMemoryBusToApbBridge | 212|
|10 | system_cpu |VexRiscv | 1362|
|11 | IBusSimplePlugin_rspJoin_rspBuffer_c |StreamFifoLowLatency | 146|
|12 | system_gpioACtrl |Apb3Gpio | 113|
|13 | io_gpio_read_buffercc |BufferCC_2_ | 36|
|14 | system_mainBusArbiter |MuraxMasterArbiter | 3|
|15 | system_ram |MuraxPipelinedMemoryBusRam | 9|
|16 | system_timer |MuraxApb3Timer | 188|
|17 | interruptCtrl_1_ |InterruptCtrl | 7|
|18 | prescaler_1_ |Prescaler | 31|
|19 | timerA |Timer | 37|
|20 | timerB |Timer_1 | 37|
|21 | system_uartCtrl |Apb3UartCtrl | 233|
|22 | bridge_write_streamUnbuffered_queueWithOccupancy |StreamFifo | 48|
|23 | uartCtrl_1_ |UartCtrl | 139|
|24 | rx |UartCtrlRx | 58|
|25 | io_rxd_buffercc |BufferCC | 3|
|26 | tx |UartCtrlTx | 33|
|27 | uartCtrl_1__io_read_queueWithOccupancy |StreamFifo_0 | 44|
+------+-------------------------------------------------------+------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.965 ; gain = 422.500 ; free physical = 10389 ; free virtual = 12354
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1774.965 ; gain = 96.086 ; free physical = 10440 ; free virtual = 12405
Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1774.973 ; gain = 422.500 ; free physical = 10440 ; free virtual = 12405
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 66 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1774.973 ; gain = 0.000 ; free physical = 10388 ; free virtual = 12354
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 4 instances were transformed.
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances
INFO: [Common 17-83] Releasing license: Synthesis
147 Infos, 103 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 1774.973 ; gain = 422.898 ; free physical = 10484 ; free virtual = 12450
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1774.973 ; gain = 0.000 ; free physical = 10484 ; free virtual = 12450
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/synth_1/toplevel.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file toplevel_utilization_synth.rpt -pb toplevel_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Feb 11 19:17:15 2020...
Raw
2_impl_runme.log
*** Running vivado
with args -log toplevel.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source toplevel.tcl -notrace
****** Vivado v2018.3 (64-bit)
**** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source toplevel.tcl -notrace
Command: link_design -top toplevel -part xc7a35ticsg324-1L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 66 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc]
Finished Parsing XDC File [/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/arty_a7.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1499.086 ; gain = 0.000 ; free physical = 10627 ; free virtual = 12593
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 4 instances were transformed.
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1546.102 ; gain = 47.016 ; free physical = 10620 ; free virtual = 12587
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: f85815e0
Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2001.602 ; gain = 455.500 ; free physical = 10231 ; free virtual = 12214
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: f98676f0
Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12146
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: c96e4105
Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12146
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 11cb466ae
Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12146
INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 11cb466ae
Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12146
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: e9270bba
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12147
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 14c50d67c
Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12147
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 4 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12147
Ending Logic Optimization Task | Checksum: ebc28b40
Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2079.602 ; gain = 0.000 ; free physical = 10164 ; free virtual = 12147
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.592 | TNS=0.000 |
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 6 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 4 newly gated: 2 Total Ports: 12
Ending PowerOpt Patch Enables Task | Checksum: b878a0da
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10144 ; free virtual = 12131
Ending Power Optimization Task | Checksum: b878a0da
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.85 . Memory (MB): peak = 2346.918 ; gain = 267.316 ; free physical = 10150 ; free virtual = 12137
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: b878a0da
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10150 ; free virtual = 12137
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10150 ; free virtual = 12137
Ending Netlist Obfuscation Task | Checksum: ad9ee1a3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10150 ; free virtual = 12137
INFO: [Common 17-83] Releasing license: Implementation
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2346.918 ; gain = 847.832 ; free physical = 10151 ; free virtual = 12137
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10151 ; free virtual = 12137
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10149 ; free virtual = 12137
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10148 ; free virtual = 12136
INFO: [Common 17-1381] The checkpoint '/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/toplevel_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file toplevel_drc_opted.rpt -pb toplevel_drc_opted.pb -rpx toplevel_drc_opted.rpx
Command: report_drc -file toplevel_drc_opted.rpt -pb toplevel_drc_opted.pb -rpx toplevel_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/toplevel_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 4 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_apbBridge/pipelinedMemoryBusStage_rsp_regNext_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/CsrPlugin_interrupt_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/DebugPlugin_haltIt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/DebugPlugin_stepIt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/FSM_sequential__zz_108__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/FSM_sequential__zz_108__reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/FSM_sequential__zz_108__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/IBusSimplePlugin_rspJoin_rspBuffer_c/risingOccupancy_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/_zz_55__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/_zz_95__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/execute_LightShifterPlugin_isActive_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/execute_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_mainBusArbiter/rspTarget_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_ram/_zz_1__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10100 ; free virtual = 12111
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 79959c28
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10100 ; free virtual = 12111
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10100 ; free virtual = 12111
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d807986a
Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.40 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10095 ; free virtual = 12109
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1a99889ed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.65 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10089 ; free virtual = 12104
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1a99889ed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10089 ; free virtual = 12104
Phase 1 Placer Initialization | Checksum: 1a99889ed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10089 ; free virtual = 12104
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1384fc860
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10087 ; free virtual = 12102
Phase 2.2 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10074 ; free virtual = 12090
Summary of Physical Synthesis Optimizations
============================================
----------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
----------------------------------------------------------------------------------------------------------------------------------------
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
----------------------------------------------------------------------------------------------------------------------------------------
Phase 2.2 Physical Synthesis In Placer | Checksum: fc1dbfed
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10073 ; free virtual = 12090
Phase 2 Global Placement | Checksum: 1299d3ced
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10073 ; free virtual = 12090
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1299d3ced
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10073 ; free virtual = 12090
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 134a97e09
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10073 ; free virtual = 12091
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 12ecc15b1
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10073 ; free virtual = 12091
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 9478d4f2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10073 ; free virtual = 12091
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 12857d0ec
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 11925929e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1c3c2d15b
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 3 Detail Placement | Checksum: 1c3c2d15b
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1bb05914d
Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
Phase 4.1.1.1 BUFG Insertion | Checksum: 1bb05914d
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.553. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 125be45e5
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 4.1 Post Commit Optimization | Checksum: 125be45e5
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 125be45e5
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 125be45e5
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 4.4 Final Placement Cleanup | Checksum: 1d9e61909
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d9e61909
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12089
Ending Placer Task | Checksum: 1cbca8db9
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10076 ; free virtual = 12094
INFO: [Common 17-83] Releasing license: Implementation
58 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10076 ; free virtual = 12094
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10074 ; free virtual = 12094
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10071 ; free virtual = 12092
INFO: [Common 17-1381] The checkpoint '/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/toplevel_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file toplevel_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10057 ; free virtual = 12078
INFO: [runtcl-4] Executing : report_utilization -file toplevel_utilization_placed.rpt -pb toplevel_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file toplevel_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10066 ; free virtual = 12087
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.250 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
67 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10035 ; free virtual = 12055
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10031 ; free virtual = 12053
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 10027 ; free virtual = 12050
INFO: [Common 17-1381] The checkpoint '/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/toplevel_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
Checksum: PlaceDB: cc88eb3e ConstDB: 0 ShapeSum: ff41a27b RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1891b8242
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9934 ; free virtual = 11955
Post Restoration Checksum: NetGraph: aa19cb67 NumContArr: df01b6db Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 1891b8242
Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9935 ; free virtual = 11956
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 1891b8242
Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9920 ; free virtual = 11941
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 1891b8242
Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9920 ; free virtual = 11941
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1bdd41b51
Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9911 ; free virtual = 11931
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.756 | TNS=0.000 | WHS=-0.156 | THS=-27.965|
Phase 2 Router Initialization | Checksum: 270163739
Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9911 ; free virtual = 11932
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 140f07e03
Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9911 ; free virtual = 11933
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 309
Number of Nodes with overlaps = 40
Number of Nodes with overlaps = 17
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.415 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 15dbdb349
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 4 Rip-up And Reroute | Checksum: 15dbdb349
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 15b79ddc6
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.508 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 5.1 Delay CleanUp | Checksum: 15b79ddc6
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 15b79ddc6
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 5 Delay and Skew Optimization | Checksum: 15b79ddc6
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: d5128089
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.508 | TNS=0.000 | WHS=0.016 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 165845f86
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 6 Post Hold Fix | Checksum: 165845f86
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.770948 %
Global Horizontal Routing Utilization = 0.739849 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 19efa7bb3
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9910 ; free virtual = 11931
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 19efa7bb3
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9909 ; free virtual = 11930
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 14688cbf4
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9909 ; free virtual = 11930
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.508 | TNS=0.000 | WHS=0.016 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 14688cbf4
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9909 ; free virtual = 11930
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9926 ; free virtual = 11947
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
82 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9926 ; free virtual = 11947
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9926 ; free virtual = 11947
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9922 ; free virtual = 11945
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2346.918 ; gain = 0.000 ; free physical = 9920 ; free virtual = 11945
INFO: [Common 17-1381] The checkpoint '/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/toplevel_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file toplevel_drc_routed.rpt -pb toplevel_drc_routed.pb -rpx toplevel_drc_routed.rpx
Command: report_drc -file toplevel_drc_routed.rpt -pb toplevel_drc_routed.pb -rpx toplevel_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/toplevel_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file toplevel_methodology_drc_routed.rpt -pb toplevel_methodology_drc_routed.pb -rpx toplevel_methodology_drc_routed.rpx
Command: report_methodology -file toplevel_methodology_drc_routed.rpt -pb toplevel_methodology_drc_routed.pb -rpx toplevel_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 4 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/toplevel_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file toplevel_power_routed.rpt -pb toplevel_power_summary_routed.pb -rpx toplevel_power_routed.rpx
Command: report_power -file toplevel_power_routed.rpt -pb toplevel_power_summary_routed.pb -rpx toplevel_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
94 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file toplevel_route_status.rpt -pb toplevel_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file toplevel_timing_summary_routed.rpt -pb toplevel_timing_summary_routed.pb -rpx toplevel_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file toplevel_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file toplevel_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file toplevel_bus_skew_routed.rpt -pb toplevel_bus_skew_routed.pb -rpx toplevel_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
Command: write_bitstream -force toplevel.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_apbBridge/pipelinedMemoryBusStage_rsp_regNext_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/CsrPlugin_interrupt_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/DebugPlugin_haltIt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/DebugPlugin_stepIt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/FSM_sequential__zz_108__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/FSM_sequential__zz_108__reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/FSM_sequential__zz_108__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/IBusSimplePlugin_rspJoin_rspBuffer_c/risingOccupancy_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/_zz_55__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/_zz_95__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/execute_LightShifterPlugin_isActive_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/execute_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_cpu/memory_to_writeBack_INSTRUCTION_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_mainBusArbiter/rspTarget_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 core/system_cpu/RegFilePlugin_regFile_reg_1 has an input control pin core/system_cpu/RegFilePlugin_regFile_reg_1/ADDRARDADDR[9] (net: core/system_cpu/decode_RegFilePlugin_regFileReadAddress1[4]) which is driven by a register (core/system_ram/_zz_1__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 22 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./toplevel.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/vm/fpga/Spinal/VexRiscv/scripts/Murax/arty_a7/build/vivado_project/fpga.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Feb 11 19:20:21 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.3/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
114 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:09 ; elapsed = 00:02:20 . Memory (MB): peak = 2636.621 ; gain = 278.664 ; free physical = 9781 ; free virtual = 11925
INFO: [Common 17-206] Exiting Vivado at Tue Feb 11 19:20:21 2020...
Raw
3_toplevel_utilization_placed.rpt
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
| Date : Tue Feb 11 19:17:42 2020
| Host : vmarchlinux running 64-bit Arch Linux
| Command : report_utilization -file toplevel_utilization_placed.rpt -pb toplevel_utilization_placed.pb
| Design : toplevel
| Device : 7a35ticsg324-1L
| Design State : Fully Placed
-------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs | 1003 | 0 | 20800 | 4.82 |
| LUT as Logic | 985 | 0 | 20800 | 4.74 |
| LUT as Memory | 18 | 0 | 9600 | 0.19 |
| LUT as Distributed RAM | 16 | 0 | | |
| LUT as Shift Register | 2 | 0 | | |
| Slice Registers | 1267 | 0 | 41600 | 3.05 |
| Register as Flip Flop | 1267 | 0 | 41600 | 3.05 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 6 | 0 | 16300 | 0.04 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+----------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 10 | Yes | - | Set |
| 219 | Yes | - | Reset |
| 36 | Yes | Set | - |
| 1002 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 380 | 0 | 8150 | 4.66 |
| SLICEL | 225 | 0 | | |
| SLICEM | 155 | 0 | | |
| LUT as Logic | 985 | 0 | 20800 | 4.74 |
| using O5 output only | 0 | | | |
| using O6 output only | 830 | | | |
| using O5 and O6 | 155 | | | |
| LUT as Memory | 18 | 0 | 9600 | 0.19 |
| LUT as Distributed RAM | 16 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 0 | | | |
| using O5 and O6 | 16 | | | |
| LUT as Shift Register | 2 | 0 | | |
| using O5 output only | 1 | | | |
| using O6 output only | 1 | | | |
| using O5 and O6 | 0 | | | |
| Slice Registers | 1267 | 0 | 41600 | 3.05 |
| Register driven from within the Slice | 570 | | | |
| Register driven from outside the Slice | 697 | | | |
| LUT in front of the register is unused | 391 | | | |
| LUT in front of the register is used | 306 | | | |
| Unique Control Sets | 44 | | 8150 | 0.54 |
+--------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 3 | 0 | 50 | 6.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 6 | 0 | 100 | 6.00 |
| RAMB18E1 only | 6 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 21 | 21 | 210 | 10.00 |
| IOB Master Pads | 9 | | | |
| IOB Slave Pads | 11 | | | |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 1002 | Flop & Latch |
| LUT6 | 465 | LUT |
| LUT3 | 231 | LUT |
| FDCE | 219 | Flop & Latch |
| LUT5 | 205 | LUT |
| LUT4 | 155 | LUT |
| LUT2 | 79 | LUT |
| CARRY4 | 50 | CarryLogic |
| FDSE | 36 | Flop & Latch |
| RAMD32 | 24 | Distributed Memory |
| IBUF | 15 | IO |
| FDPE | 10 | Flop & Latch |
| RAMS32 | 8 | Distributed Memory |
| RAMB18E1 | 6 | Block Memory |
| OBUF | 6 | IO |
| MUXF7 | 6 | MuxFx |
| LUT1 | 5 | LUT |
| BUFG | 2 | Clock |
| SRLC32E | 1 | Distributed Memory |
| SRL16E | 1 | Distributed Memory |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
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