sevenseg.vhd

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-- Engineer: J. Lievisse Adriaanse <jasper@humppa.nl>
-- 
-- Create Date:    12:03:42 05/25/2014 
-- Design Name: 
-- Module Name:    sevenseg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sevenseg is
	Port (
		anodes 	: out STD_LOGIC_VECTOR (3 downto 0);
		sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
		dp			: out	STD_LOGIC;
		switches	: in	STD_LOGIC_VECTOR (7 downto 0)
	);
end sevenseg;

architecture Behavioral of sevenseg is

begin
	anodes 	<= "1110";
	dp			<= switches(7);
	
	seg_process: process(switches(3 downto 0))
	begin
		-- Decode the 4-bit binary number set by the switches
		-- and display the hex number on the first 7 segment display.
		Case switches(3 downto 0) Is
			When "0000" =>
				sevenseg <= "1000000"; -- 0
			When "0001" =>
				sevenseg <= "1111001"; -- 1
			When "0010" =>
				sevenseg <= "0100100"; -- 2
			When "0011" =>
				sevenseg <= "0110000"; -- 3
			When "0100" =>
				sevenseg <= "0011001"; -- 4
			When "0101" =>
				sevenseg <= "0010010"; -- 5
			When "0110" =>
				sevenseg <= "0000010"; -- 6
			When "0111" =>
				sevenseg <= "1111000"; -- 7
			When "1000" =>
				sevenseg <= "0000000"; -- 8
			When "1001" =>
				sevenseg <= "0010000"; -- 9
			When "1010" =>
				sevenseg <= "0001000"; -- A
			When "1011" =>
				sevenseg <= "0000011"; -- b
			When "1100" =>
				sevenseg <= "1000110"; -- C
			When "1101" =>
				sevenseg <= "0100001"; -- d
			When "1110" =>
				sevenseg <= "0000110"; -- E
			When "1111" =>
				sevenseg <= "0001110"; -- F
			When Others =>
				sevenseg <= "1111111";
		end Case;
	end process;
end Behavioral;