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@jbaiter
Created Aug 8, 2011
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SPC Upload routine that doesn't crash, but whose data doesn't appear in the SMP RAM and which doesn't execute the desired offset according to the trace...
namespace spc
define spcaddr #$0100
define spcexec #$0100
// DESIGN:
// Base address for spc data is fixed
// Specific offset is handed via X register (16bit)
// First 2 bytes of spc data is length
// -> ACL to 8bit, LDA spc_length -> TAY
// -> Upload loop, via LDA {spc_data},X
upload:
phx
// IPL portmap outside transfer state:
// $2141 = command (transfer / run)
// $2142-3 = target address
// $2140 = trigger
rep #$20 // 16bit accumulator
sep #$10 // 8bit x/y
lda {spcaddr}
sta $2142
ldx #$01 // transfer
stx $2141
ldx #$cc
stx $2140
-; cpx $2140
bne {-}
init:
// IPL portmap inside transfer state:
// $2140 = sequence number
// $2141 = payload
// init counters
rep #$30 // 16bit registers
plx
lda $0e0000+x // get length
inx
inx // point on the beginning of data
tay // countdown
sep #$20 // 8bit accumulator
lda $0e0000+x // get first byte of data
sta $2141 // write to APU
inx
dey
lda #$00
-; sta $2140
cmp $2140
bne {-}
loop:
lda $0e0000+x // fill data byte
sta $2141 // write data...
lda $2140 // get sequence counter
inc // increment
sta $2140 // write back
-; cmp $2140 // wait for echo from IPL
bne {-}
inx // increment sequence counter...
dey
bne loop // if not, do it again
end:
rep #$20
lda {spcexec}
sta $2142 // set exec address
stz $2141 // command: run
ldx $2140
inx
inx
stx $2140 // send sequence end / execute
-; cpx $2140 // wait for last echo
bne {-}
sep #$20
rep #$10
rts
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