Skip to content

Instantly share code, notes, and snippets.

@jbqubit

jbqubit/dir_switch.vhd

Last active July 10, 2017 21:01
Show Gist options
  • Save jbqubit/2d99dac5ed61c4a924b398da6f2c9fbb to your computer and use it in GitHub Desktop.
Save jbqubit/2d99dac5ed61c4a924b398da6f2c9fbb to your computer and use it in GitHub Desktop.
Download ZIP
test code
Raw
dir_switch.vhd
-------------------------------------------------------------------------------
-- Title : FMC_LVDS direction controller
-- Project :
-------------------------------------------------------------------------------
-- File : dir_switch.vhd
-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
-- Company : Institute of Electronic Systems
-- License : BSD
-- Created : 2015-05-14
-- Last update: 2015-05-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This block allows you to set the directions in the FMC_LVDS board
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-05-14 1.0 WZab Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dir_switch is
generic (
CHAIN_LEN : integer := 32 -- Length of the bit stream
);
port (
-- system interface
clk : in std_logic;
rst_p : in std_logic;
-- Input with desired directions
dirs : in std_logic_vector(CHAIN_LEN-1 downto 0);
-- Output signals for the SPI-like chain
ser : out std_logic := '0';
srclk : out std_logic := '0';
rclk : out std_logic := '0');
end entity dir_switch;
architecture beh of dir_switch is
signal count : integer range 0 to CHAIN_LEN := 0;
signal step : integer range 0 to 1 := 0;
begin -- architecture beh
-- Signal rclk must be generated in oposite phase!
p1 : process (clk) is
begin -- process p1
if clk'event and clk = '1' then -- rising clock edge
if rst_p = '1' then -- asynchronous reset (active low)
count <= 0;
step <= 0;
else
if count < CHAIN_LEN then
if step = 0 then
ser <= dirs(count);
rclk <= '0';
srclk <= '0';
step <= 1;
else
srclk <= '1';
count <= count + 1;
step <= 0;
end if;
else
if step = 0 then
ser <= '0';
rclk <= '0';
srclk <= '0';
step <= 1;
else
rclk <= '1';
step <= 0;
count <= 0;
end if;
end if;
end if;
end if;
end process p1;
end architecture beh;
Raw
tester_top_wrapper.vhd
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Sun Feb 21 22:24:05 2016
--Host : wzab running 64-bit Debian GNU/Linux testing/unstable
--Command : generate_target tester_top_wrapper.bd
--Design : tester_top_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity tester_top_wrapper is
generic (
NUM_I2CS : integer := 1);
port (
-- PHY_RESET
-- PHY_TXD : out std_logic_vector(7 downto 0);
-- PHY_TXC_GTXCLK
-- PHY_TXCLK
-- PHY_TXCTL_TXEN
-- PHY_TXER
-- PHY_INT
-- PHY_MDC
-- PHY_CRS
-- PHY_RXCTL_RXDV
-- PHY_RXD : in std_logic_vector(7 downto 0);
-- PHY_RXCLK
-- PHY_RXER
-- PHY_COL
-- PHY_MDIO
-- FMC_LPC_CLK0_M2C_N : inout std_logic;
-- FMC_LPC_CLK1_M2C_P : inout std_logic;
-- FMC_LPC_CLK1_M2C_N : inout std_logic;
-- FMC_LPC_GBTCLK0_M2C_P : inout std_logic;
-- FMC_LPC_GBTCLK0_M2C_N : inout std_logic;
FMC_LPC_LA_P : inout std_logic_vector(33 downto 0);
FMC_LPC_LA_N : inout std_logic_vector(33 downto 0);
-- FMC clocks
-- fmc1_clk0_m2c_p : in std_logic;
-- fmc1_clk0_m2c_n : in std_logic;
-- fmc1_clk1_m2c_p : in std_logic;
-- fmc1_clk1_m2c_n : in std_logic;
-- fmc1_gbtclk0_m2c_p : in std_logic;
-- fmc1_gbtclk0_m2c_n : in std_logic;
-- -- DP
-- fmc1_dp0_m2c_p : in std_logic;
-- fmc1_dp0_m2c_n : in std_logic;
-- fmc1_dp0_c2m_p : out std_logic;
-- fmc1_dp0_c2m_n : out std_logic;
IIC_SDA_MAIN : inout std_logic_vector(0 downto 0);
IIC_SCL_MAIN : inout std_logic_vector(0 downto 0);
IIC_MUX_RESET_B : out std_logic;
USB_TX : in std_logic;
USB_RX : out std_logic;
GPIO_SW_C : in std_logic;
GPIO_SW_N : in std_logic;
GPIO_LED_0_LS : out std_logic;
CPU_RESET : in std_logic;
GPIO_DIP_SW3 : in std_logic;
GPIO_DIP_SW2 : in std_logic;
GPIO_DIP_SW1 : in std_logic;
GPIO_DIP_SW0 : in std_logic;
USER_SMA_GPIO_P : out std_logic;
USER_SMA_GPIO_N : out std_logic;
SYSCLK_P : in std_logic;
SYSCLK_N : in std_logic
-- USER_CLOCK_N : in std_logic;
-- USER_CLOCK_P : in std_logic
);
end tester_top_wrapper;
architecture STRUCTURE of tester_top_wrapper is
component clk_wiz_0 is
port (
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
clk_out1 : out STD_LOGIC;
clk_out2: inout std_logic
);
end component clk_wiz_0;
component dir_switch is
port (
-- system interface
clk : in std_logic;
rst_p : in std_logic;
-- Input with desired directions
dirs : in std_logic_vector(31 downto 0);
-- Output signals for the SPI-like chain
ser : out std_logic := '0';
srclk : out std_logic := '0';
rclk : out std_logic := '0');
end component dir_switch;
component ila_0 is
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
);end component ila_0;
signal probe0,probe1,probe2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal probe3 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal CLK50,CLK300, TRI, SIG, RESET, ser ,srclk, rclk : std_logic;
signal FMC_LPC_LA_O : STD_LOGIC_VECTOR ( 33 downto 0 );
signal FMC_LPC_LA_I : STD_LOGIC_VECTOR ( 33 downto 0 );
signal dir,term_dis,dir_switch_dir : STD_LOGIC_VECTOR ( 31 downto 0 );
signal dir0,dir1,dir2,dir3: STD_LOGIC_VECTOR ( 7 downto 0 );
signal frq0_in : std_logic;
signal clk_frq0 : std_logic_vector(31 downto 0);
signal frq1_in : std_logic;
signal clk_frq1 : std_logic_vector(31 downto 0);
signal frq2_in : std_logic;
signal clk_frq2 : std_logic_vector(31 downto 0);
signal lpbck0, lpbck1, lpbck2, lpbck3 : std_logic_vector(31 downto 0);
signal uart_o : std_logic;
begin
IIC_MUX_RESET_B <= '1';
-- quick diagnostic feature to chceck UART loopback
GPIO_LED_0_LS <= not GPIO_SW_C;
process (GPIO_SW_C)
begin
if (GPIO_SW_C = '0') then
USB_RX <= uart_o ;
else
USB_RX <= USB_TX;
end if;
end process;
-- J1B processor for I2C control and optionally, clocks frequency measurement. Taken directly from CBM project
j1_env_1 : entity work.j1_env
generic map (
NUM_I2CS => NUM_I2CS)
port map (
clk => CLK50, -- boot_clk
rst_n => '1', -- was sys_rst(0), but didnt work!
scl => IIC_SCL_MAIN,
sda => IIC_SDA_MAIN,
uart_tx => uart_o,
uart_rx => USB_TX,
clk_0 => CLK50,
clk_1 => CLK50,
clk_2 => CLK50,
out0 => lpbck0,
out1 => lpbck1,
out2 => lpbck2,
out3 => lpbck3,
inp0 => lpbck0,
inp1 => lpbck1,
inp2 => lpbck2,
inp3 => lpbck3
);
RESET <= CPU_RESET;
-- we have 200MHz clock but need 50MHz
clk_wiz: component clk_wiz_0
port map (
clk_in1_n => SYSCLK_N,
clk_in1_p => SYSCLK_P,
clk_out1 => CLK50,
clk_out2 => CLK300
);
USER_SMA_GPIO_P <= CLK50;
-- LVDS bidir buffers
G_1 : for I in 0 to 31 generate
lvds_buf : IOBUFDS_INTERMDISABLE
GENERIC MAP (
DIFF_TERM => "true",
IBUF_LOW_PWR => "true",
IOSTANDARD => "LVDS_25",
USE_IBUFDISABLE => "false")
PORT MAP (
O => FMC_LPC_LA_I(I),
IO => FMC_LPC_LA_P(I),
IOB => FMC_LPC_LA_N(I),
INTERMDISABLE => term_dis(I),
I => FMC_LPC_LA_O(I),
IBUFDISABLE => '0',
T => dir(I) -- 3-state enable input, high=input, low=output
);
end generate G_1;
-- we use DIP switches to control LVDS buffers directions in groups of 8
dir0 <= (others => GPIO_DIP_SW0);
dir1 <= (others => GPIO_DIP_SW1);
dir2 <= (others => GPIO_DIP_SW2);
dir3 <= (others => GPIO_DIP_SW3);
dir <= dir3 & dir2 & dir1 & dir0;
term_dis <= not dir;
-- connect MSB inputs with LSB outputs and vice versa
FMC_LPC_LA_O(31 downto 16) <= FMC_LPC_LA_I(15 downto 0);
FMC_LPC_LA_O(15 downto 0) <= FMC_LPC_LA_I(31 downto 16);
-- simple state machnine that controls direction of LVDS buffers on FMC-VHDCI board
dir_switch_i: component dir_switch
port map (
clk => CLK50,
rst_p => RESET,
dirs => dir_switch_dir,
ser => ser,
srclk => srclk,
rclk => rclk
);
--swapped control lines to make the PCB routing easier
dir_switch_dir(31) <= not dir(30);
dir_switch_dir(30) <= not dir(31);
dir_switch_dir(29) <= not dir(28);
dir_switch_dir(28) <= not dir(29);
dir_switch_dir(27) <= not dir(26);
dir_switch_dir(26) <= not dir(27);
dir_switch_dir(25) <= not dir(24);
dir_switch_dir(24) <= not dir(25);
dir_switch_dir(23) <= not dir(22);
dir_switch_dir(22) <= not dir(23);
dir_switch_dir(21) <= not dir(20);
dir_switch_dir(20) <= not dir(21);
dir_switch_dir(19) <= not dir(18);
dir_switch_dir(18) <= not dir(19);
dir_switch_dir(17) <= not dir(16);
dir_switch_dir(16) <= not dir(17);
dir_switch_dir(15) <= not dir(14);
dir_switch_dir(14) <= not dir(15);
dir_switch_dir(13) <= not dir(12);
dir_switch_dir(12) <= not dir(13);
dir_switch_dir(11) <= not dir(10);
dir_switch_dir(10) <= not dir(11);
dir_switch_dir(9) <= not dir(8);
dir_switch_dir(8) <= not dir(9);
dir_switch_dir(7) <= not dir(6);
dir_switch_dir(6) <= not dir(7);
dir_switch_dir(5) <= not dir(4);
dir_switch_dir(4) <= not dir(5);
dir_switch_dir(3) <= not dir(2);
dir_switch_dir(2) <= not dir(3);
dir_switch_dir(1) <= not dir(0);
dir_switch_dir(0) <= not dir(1);
-- diagnostic output to verify SPI readout
USER_SMA_GPIO_N <= FMC_LPC_LA_N(33);
-- SPI lines
FMC_LPC_LA_P(33) <= ser;
FMC_LPC_LA_N(32) <= srclk;
FMC_LPC_LA_P(32) <= rclk;
---------------------------------------------------------------------------------------------------------------------------------------------
--------------------------- CHIPSCOPE ---------------------------------------------------------------------------------
chipscope1: ila_0
PORT MAP(
clk => CLK50,
probe0 => probe0,
probe1 => probe1,
probe2 => probe2,
probe3 => probe3
);
probe0 <= FMC_LPC_LA_I(31 downto 0);
probe1 <= FMC_LPC_LA_O(31 downto 0);
probe2 <= dir(31 downto 0);
probe3(0) <= ser;
probe3(1) <= srclk;
probe3(2) <= rclk;
probe3(3) <= FMC_LPC_LA_N(33);
probe3(4) <= GPIO_DIP_SW0;
probe3(5) <= GPIO_DIP_SW1;
probe3(6) <= GPIO_DIP_SW2;
probe3(7) <= GPIO_DIP_SW3;
probe3(8) <= RESET;
probe3(15 downto 9) <= (others => '0');
end STRUCTURE;
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment