gistfile1.txt

From c45fe2b951586f4e600700eee64e99be50182aec Mon Sep 17 00:00:00 2001
From: jbqubit <joe.britton.arl@gmail.com>
Date: Wed, 12 Jul 2017 18:53:29 -0400
Subject: [PATCH 1/1] add outline for fmc_lpc_to_vhdci_breakout

---
 artiq/coredevice/i2c.py                     | 11 ++++
 artiq/examples/phaser/device_db.py          | 80 +++++++++++++++++------------
 artiq/examples/phaser/repository/demo.py    | 57 ++++++++------------
 artiq/gateware/fmc_lpc_to_vhdci_breakout.py | 50 ++++++++++++++++++
 artiq/gateware/targets/phaser.py            | 46 ++++++++++++-----
 5 files changed, 163 insertions(+), 81 deletions(-)
 create mode 100644 artiq/gateware/fmc_lpc_to_vhdci_breakout.py

diff --git a/artiq/coredevice/i2c.py b/artiq/coredevice/i2c.py
index ce8ca33..4d76c2a 100644
--- a/artiq/coredevice/i2c.py
+++ b/artiq/coredevice/i2c.py
@@ -118,3 +118,14 @@ class TCA6424A:
 
         self._write24(0x8c, 0)  # set all directions to output
         self._write24(0x84, outputs_le)  # set levels
+
+class TCA9548A:
+    """todo: Driver for the TCA9548A I2C I/O expander."""
+    def __init__(self, dmgr, busno=0, address=0x44, core_device="core"):
+        self.core = dmgr.get(core_device)
+        self.busno = busno
+        self.address = address
+
+    @kernel
+    def set(self, outputs):
+        pass
\ No newline at end of file
diff --git a/artiq/examples/phaser/device_db.py b/artiq/examples/phaser/device_db.py
index 9e17103..1d21097 100644
--- a/artiq/examples/phaser/device_db.py
+++ b/artiq/examples/phaser/device_db.py
@@ -1,6 +1,7 @@
 # The RTIO channel numbers here are for Phaser on KC705.
 
-core_addr = "kc705aux.lab.m-labs.hk"
+core_addr = "192.168.1.71"
+vhdcistart = 0
 
 device_db = {
     "core": {
@@ -20,57 +21,72 @@ device_db = {
         "module": "artiq.coredevice.cache",
         "class": "CoreCache"
     },
-    "ttl_sma": {
+
+    "lpc_vhdci_port0_ttl0": {
         "type": "local",
         "module": "artiq.coredevice.ttl",
-        "class": "TTLInOut",
-        "arguments": {"channel": 0}
+        "class": "TTLOut",
+        "arguments": {"channel": vhdcistart + 0}
     },
-    "led": {
+    "lpc_vhdci_port0_ttl1": {
         "type": "local",
         "module": "artiq.coredevice.ttl",
         "class": "TTLOut",
-        "arguments": {"channel": 1}
+        "arguments": {"channel": vhdcistart + 1}
+    },
+    "lpc_vhdci_port0_ttl2": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": vhdcistart + 2}
     },
-    "sysref": {
+    "lpc_vhdci_port0_ttl3": {
         "type": "local",
         "module": "artiq.coredevice.ttl",
-        "class": "TTLInOut",
-        "arguments": {"channel": 2}
+        "class": "TTLOut",
+        "arguments": {"channel": vhdcistart + 3}
+    },
+    "lpc_vhdci_port0_ttl4": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": vhdcistart + 4}
     },
-    "converter_spi": {
+    "lpc_vhdci_port0_ttl5": {
         "type": "local",
-        "module": "artiq.coredevice.spi",
-        "class": "NRTSPIMaster",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": vhdcistart + 5}
     },
-    "ad9154_spi": {
+    "lpc_vhdci_port0_ttl6": {
         "type": "local",
-        "module": "artiq.coredevice.ad9154_spi",
-        "class": "AD9154",
-        "arguments": {"spi_device": "converter_spi", "chip_select": 1}
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": vhdcistart + 6}
     },
-    "sawg0": {
+    "lpc_vhdci_port0_ttl7": {
         "type": "local",
-        "module": "artiq.coredevice.sawg",
-        "class": "SAWG",
-        "arguments": {"channel_base": 3, "parallelism": 2}
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": vhdcistart + 7}
     },
-    "sawg1": {
+
+    "lpc_vhdci_i2c": {
         "type": "local",
-        "module": "artiq.coredevice.sawg",
-        "class": "SAWG",
-        "arguments": {"channel_base": 13, "parallelism": 2}
+        "module": "artiq.coredevice.i2c",
+        "class": "TCA9548A",
+        "arguments": {"address": 0x44}
     },
-    "sawg2": {
+    "sma_ttl_diff": {
         "type": "local",
-        "module": "artiq.coredevice.sawg",
-        "class": "SAWG",
-        "arguments": {"channel_base": 23, "parallelism": 2}
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 0}
     },
-    "sawg3": {
+    "led": {
         "type": "local",
-        "module": "artiq.coredevice.sawg",
-        "class": "SAWG",
-        "arguments": {"channel_base": 33, "parallelism": 2}
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 1}
     }
 }
diff --git a/artiq/examples/phaser/repository/demo.py b/artiq/examples/phaser/repository/demo.py
index ac61956..e643b22 100644
--- a/artiq/examples/phaser/repository/demo.py
+++ b/artiq/examples/phaser/repository/demo.py
@@ -5,46 +5,31 @@ class SAWGTest(EnvExperiment):
     def build(self):
         self.setattr_device("core")
         self.setattr_device("led")
-        self.setattr_device("ttl_sma")
+        self.setattr_device("sma_ttl_diff")
 
-        self.setattr_device("sawg0")
-        self.setattr_device("sawg1")
-        self.setattr_device("sawg2")
-        self.setattr_device("sawg3")
+        self.setattr_device("lpc_vhdci_port0_ttl0")
+        self.setattr_device("lpc_vhdci_port0_ttl1")
+        self.setattr_device("lpc_vhdci_port0_ttl2")
+        self.setattr_device("lpc_vhdci_port0_ttl3")
 
     @kernel
     def run(self):
         self.core.reset()
-        self.ttl_sma.output()
+        delay(10 * ms)
+        self.sma_ttl_diff.output()
+        self.led.output()
+        self.lpc_vhdci_port0_ttl0.output()
+        self.lpc_vhdci_port0_ttl1.output()
+        self.lpc_vhdci_port0_ttl2.output()
+        self.lpc_vhdci_port0_ttl3.output()
 
-        while True:
-            self.sawg0.amplitude1.set(0.)
-            self.sawg0.frequency0.set(0*MHz)
-            self.sawg1.amplitude1.set(0.)
-            self.sawg1.frequency0.set(0*MHz)
-            delay(20*ms)
+        delay(10*ms)
 
-            self.sawg0.amplitude1.set(.4)
-            self.sawg0.frequency0.set(10*MHz)
-            self.sawg0.phase0.set(0.)
-            self.sawg1.amplitude1.set(.4)
-            self.sawg1.frequency0.set(10*MHz)
-            self.sawg1.phase0.set(0.)
-            self.ttl_sma.pulse(200*ns)
-            self.sawg1.amplitude1.set(.1)
-            delay(200*ns)
-            self.sawg1.amplitude1.set(-.4)
-            self.ttl_sma.pulse(200*ns)
-            self.sawg1.amplitude1.set(.4)
-            delay(200*ns)
-            self.sawg1.phase0.set(.25)
-            self.ttl_sma.pulse(200*ns)
-            self.sawg1.phase0.set(.5)
-            delay(200*ns)
-            self.sawg0.phase0.set(.5)
-            self.ttl_sma.pulse(200*ns)
-            self.sawg1.frequency0.set(30*MHz)
-            delay(200*ns)
-            self.sawg1.frequency0.set(10*MHz)
-            self.sawg1.phase0.set(0.)
-            self.ttl_sma.pulse(200*ns)
+        while True:
+            self.sma_ttl_diff.pulse(500*ns)
+            self.lpc_vhdci_port0_ttl0.pulse(1*us)
+            self.lpc_vhdci_port0_ttl1.pulse(2 * us)
+            self.lpc_vhdci_port0_ttl2.pulse(3 * us)
+            self.lpc_vhdci_port0_ttl3.pulse(3 * us)
+            self.led.pulse(100*ms)
+            delay(100*ms)
diff --git a/artiq/gateware/fmc_lpc_to_vhdci_breakout.py b/artiq/gateware/fmc_lpc_to_vhdci_breakout.py
new file mode 100644
index 0000000..49c577f
--- /dev/null
+++ b/artiq/gateware/fmc_lpc_to_vhdci_breakout.py
@@ -0,0 +1,50 @@
+from migen.build.generic_platform import *
+
+
+fmc_lpc_to_vhdci_breakout_io = [
+    ("sma_ttl_diff", 0,
+     Subsignal("p", Pins("Y23")),
+     Subsignal("n", Pins("Y24")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 0,
+     Subsignal("p", Pins("LPC:LA00_CC_P")),
+     Subsignal("n", Pins("LPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 1,
+     Subsignal("p", Pins("LPC:LA01_CC_P")),
+     Subsignal("n", Pins("LPC:LA01_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 2,
+     Subsignal("p", Pins("LPC:LA02_P")),
+     Subsignal("n", Pins("LPC:LA02_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 3,
+     Subsignal("p", Pins("LPC:LA03_P")),
+     Subsignal("n", Pins("LPC:LA03_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 4,
+     Subsignal("p", Pins("LPC:LA04_P")),
+     Subsignal("n", Pins("LPC:LA04_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 5,
+     Subsignal("p", Pins("LPC:LA05_P")),
+     Subsignal("n", Pins("LPC:LA05_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 6,
+     Subsignal("p", Pins("LPC:LA06_P")),
+     Subsignal("n", Pins("LPC:LA06_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     ),
+    ("lpc_vhdci_ext0", 7,
+     Subsignal("p", Pins("LPC:LA07_P")),
+     Subsignal("n", Pins("LPC:LA07_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
+     )
+]
\ No newline at end of file
diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py
index fe14183..6edbe5d 100755
--- a/artiq/gateware/targets/phaser.py
+++ b/artiq/gateware/targets/phaser.py
@@ -23,6 +23,7 @@ from misoc.integration.builder import builder_args, builder_argdict
 from artiq.gateware.amp import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio
 from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
+from artiq.gateware.fmc_lpc_to_vhdci_breakout import fmc_lpc_to_vhdci_breakout_io
 from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
                                      sawg)
 from artiq import __version__ as artiq_version
@@ -177,6 +178,7 @@ class Phaser(MiniSoC, AMPSoC):
 
         platform = self.platform
         platform.add_extension(ad9154_fmc_ebz)
+        platform.add_extension(fmc_lpc_to_vhdci_breakout_io)
 
         self.submodules.leds = gpio.GPIOOut(Cat(
             platform.request("user_led", 0),
@@ -201,8 +203,15 @@ class Phaser(MiniSoC, AMPSoC):
 
         rtio_channels = []
 
-        phy = ttl_serdes_7series.InOut_8X(
-            platform.request("user_sma_gpio_n"))
+        # add FMC-LPC to VHDCI ext0 as 3U TTL BNC board
+        for i in range(8):
+            pads = platform.request("lpc_vhdci_ext0", i)
+            phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=64))
+
+        pads = platform.request("sma_ttl_diff", 0)
+        phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
 
@@ -210,17 +219,28 @@ class Phaser(MiniSoC, AMPSoC):
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        sysref_pads = platform.request("ad9154_sysref")
-        phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
-                                                   ofifo_depth=2))
-
-        self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
-        rtio_channels.extend(rtio.Channel.from_phy(phy)
-                             for sawg in self.ad9154.sawgs
-                             for phy in sawg.phys)
-
+        # speed compilation of gateware by removing sawg PHYs
+
+        # phy = ttl_serdes_7series.InOut_8X(
+        #     platform.request("user_sma_gpio_n"))
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
+        #
+        # phy = ttl_simple.Output(platform.request("user_led", 2))
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(phy))
+        #
+        # sysref_pads = platform.request("ad9154_sysref")
+        # phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
+        #                                            ofifo_depth=2))
+        #
+        # self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
+        # rtio_channels.extend(rtio.Channel.from_phy(phy)
+        #                      for sawg in self.ad9154.sawgs
+        #                      for phy in sawg.phys)
+        #
         self.config["HAS_RTIO_LOG"] = None
         self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
         rtio_channels.append(rtio.LogChannel())
-- 
1.9.1