add support for fmc_lpc_to_vhdci_breakout

gistfile1.txt

From 6e2d82e0946066273ec63b5b53a2d8089142a14e Mon Sep 17 00:00:00 2001
From: jbqubit <joe.britton.arl@gmail.com>
Date: Wed, 12 Jul 2017 18:53:29 -0400
Subject: [PATCH 1/1] add outline for fmc_lpc_to_vhdci_breakout

---
 artiq/coredevice/i2c.py                     | 11 ++++
 artiq/examples/phaser/device_db.py          | 54 +++++++++++++++++
 artiq/gateware/fmc_lpc_to_vhdci_breakout.py | 93 +++++++++++++++++++++++++++++
 artiq/gateware/targets/phaser.py            | 14 +++++
 4 files changed, 172 insertions(+)
 create mode 100644 artiq/gateware/fmc_lpc_to_vhdci_breakout.py

diff --git a/artiq/coredevice/i2c.py b/artiq/coredevice/i2c.py
index ce8ca33..4d76c2a 100644
--- a/artiq/coredevice/i2c.py
+++ b/artiq/coredevice/i2c.py
@@ -118,3 +118,14 @@ class TCA6424A:
 
         self._write24(0x8c, 0)  # set all directions to output
         self._write24(0x84, outputs_le)  # set levels
+
+class TCA9548A:
+    """todo: Driver for the TCA9548A I2C I/O expander."""
+    def __init__(self, dmgr, busno=0, address=0x44, core_device="core"):
+        self.core = dmgr.get(core_device)
+        self.busno = busno
+        self.address = address
+
+    @kernel
+    def set(self, outputs):
+        pass
\ No newline at end of file
diff --git a/artiq/examples/phaser/device_db.py b/artiq/examples/phaser/device_db.py
index 9e17103..a8a6509 100644
--- a/artiq/examples/phaser/device_db.py
+++ b/artiq/examples/phaser/device_db.py
@@ -1,6 +1,7 @@
 # The RTIO channel numbers here are for Phaser on KC705.
 
 core_addr = "kc705aux.lab.m-labs.hk"
+vhdcistart = 34
 
 device_db = {
     "core": {
@@ -72,5 +73,58 @@ device_db = {
         "module": "artiq.coredevice.sawg",
         "class": "SAWG",
         "arguments": {"channel_base": 33, "parallelism": 2}
+    },
+    "vhdci0port0ttl0": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 0}
+    },
+    "vhdci0port0ttl1": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 1}
+    },
+    "vhdci0port0ttl2": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 2}
+    },
+    "vhdci0port0tt3": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 3}
+    },
+    "vhdci0port0ttl4": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 4}
+    },
+    "vhdci0port0ttl5": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 5}
+    },
+    "vhdci0port0ttl6": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 6}
+    },
+    "vhdci0port0tt7": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": vhdcistart + 7}
+    },
+    "vhdci0i2c": {
+        "type": "local",
+        "module": "artiq.coredevice.i2c",
+        "class": "TCA9548A"
     }
 }
diff --git a/artiq/gateware/fmc_lpc_to_vhdci_breakout.py b/artiq/gateware/fmc_lpc_to_vhdci_breakout.py
new file mode 100644
index 0000000..db35858
--- /dev/null
+++ b/artiq/gateware/fmc_lpc_to_vhdci_breakout.py
@@ -0,0 +1,93 @@
+from migen.build.generic_platform import *
+
+fmc_lpc_to_vhdci_breakout_io = [
+        """
+    VHDCI0
+    - EXT0, EXT1, EXT2, EXT3 each is 8 differential pairs
+    - I2C
+    VHDCI1
+    - EXT0, EXT1, EXT2, EXT3 each is 8 differential pairs
+    - I2C
+    
+    TODO: replace all of "HPC:LA00_CC_P" with LPC:xxxxxx 
+    """
+
+    ("vhdci0ext0", 0,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext0", 1,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext0", 2,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext0", 3,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext0", 4,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext0", 5,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext0", 6,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext0", 7,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext1", 0,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext1", 1,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    # etc for pins 2-7
+    ("vhdci0ext2", 0,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext2", 1,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    # etc for pins 2-7
+    ("vhdci0ext3", 0,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    ("vhdci0ext3", 1,
+     Subsignal("p", Pins("HPC:LA00_CC_P")),
+     Subsignal("n", Pins("HPC:LA00_CC_N")),
+     IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"),
+     ),
+    # etc for pins 2-7
+    ("vhdci0i2c", 0,
+        Subsignal("scl", Pins("LPC:IIC_SCL")),
+        Subsignal("sda", Pins("LPC:IIC_SDA")),
+        IOStandard("LVCMOS25")),
+    # etc for vhdci1
+]
diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py
index fe14183..a53c7f7 100755
--- a/artiq/gateware/targets/phaser.py
+++ b/artiq/gateware/targets/phaser.py
@@ -23,6 +23,7 @@ from misoc.integration.builder import builder_args, builder_argdict
 from artiq.gateware.amp import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio
 from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
+from artiq.gateware.fmc_lpc_to_vhdci_breakout import fmc_lpc_to_vhdci_breakout_io
 from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
                                      sawg)
 from artiq import __version__ as artiq_version
@@ -177,6 +178,7 @@ class Phaser(MiniSoC, AMPSoC):
 
         platform = self.platform
         platform.add_extension(ad9154_fmc_ebz)
+        platform.add_extension(fmc_lpc_to_vhdci_breakout_io)
 
         self.submodules.leds = gpio.GPIOOut(Cat(
             platform.request("user_led", 0),
@@ -253,6 +255,18 @@ class Phaser(MiniSoC, AMPSoC):
             platform.add_false_path_constraints(
                 self.crg.cd_sys.clk, phy.transmitter.cd_tx.clk)
 
+        # add FMC-LPC to VHDCI port0, channel0
+        for i in range(8):
+            phy = ttl_serdes_7series.InOut_8X(
+                platform.request("vhdci0ext0", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=64))
+        # add FMC-LPC to VHDCI port0, spi
+        vhdci0i2c = platform.request("vhdci0i2c")
+        self.submodules.vhdci0i2c = gpio.GPIOTristate([vhdci0i2c.scl, vhdci0i2c.sda])
+        self.csr_devices.append("vhdci0i2c")
+        self.config["I2C_BUS_COUNT"] = self.config["I2C_BUS_COUNT"] + 1
+
 
 def main():
     parser = argparse.ArgumentParser(
-- 
1.9.1