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Things that Quartus flags as an error that Verilator does not

(Tested with Quartus 16 and Verilator 3.912)

  • Assign a value to an enumerated type without specifying width:

    typedef enum logic[3:0] {
       FOO = 0,
       BAR = 1
    } my_enum_t;

    Raises an error in Quartus:

    Error (10355): SystemVerilog Enumeration Type Declaration error at xxx.sv(2): encoded value for element "FOO" has width 32, which does not match the width of the enumeration's base type (2)
    

    Need to do:

    typedef enum logic[3:0] {
       FOO = 4'd0,
       BAR = 4'd1
    } my_enum_t;
  • Port direction is incorrect.

    module foo(output logic f);
        always_comb
            $display("f = %d", f);
    endmodule
    
    module bar();
        logic f;
        foo(.f(f));
    
        assign f = 2;
    endmodule
    

    Verilator is fine with this and treats f as an input in foo. Quartus displays an error

    Error (10028): Can't resolve multiple constant drivers for net "f" at...
    
  • Multiple assignments:

    assign foo = 0;
    
    assign foo = bar;

    Verilator does not raise an error. When bar changes, foo takes its value (last change wins). Quartus gives the error:

    Error (10028): Can't resolve multiple constant drivers for net "foo" at xxx.sv(yy)
    
  • Assigning a non-enum type to an enum variable

    	enum logic[1:0] {
        FOO,
     	BAR,
     	BAZ
     } e;
     
     always @(posedge clk)
     	e <= 2;
    Error (10928): SystemVerilog error at bug_test.sv(15): integer atom type cannot be assigned to enum type - enum target requires cast
    
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