test_radix4_booth_encoder.sv

//
// Copyright 2017 Jeff Bush
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//

`include "defines.svh"

import defines::*;

module test_radix4_booth_encoder(input clk, input reset);
    localparam OPERAND_WIDTH = 32;
    localparam RESULT_WIDTH = 64;
    localparam NUM_PARTIAL_PRODUCTS = OPERAND_WIDTH / 2;

    logic[OPERAND_WIDTH - 1:0] multiplier;
    logic[OPERAND_WIDTH - 1:0] multiplicand;
    logic[NUM_PARTIAL_PRODUCTS - 1:0][OPERAND_WIDTH:0] partial_product;
    logic[NUM_PARTIAL_PRODUCTS - 1:0] neg;
    int cycle;
    logic[RESULT_WIDTH - 1:0] result;

    radix4_booth_encoder radix4_booth_encoder(.*);

    always_comb
    begin
        result = 0;
        for (int pp_idx = 0; pp_idx < NUM_PARTIAL_PRODUCTS; pp_idx++)
        begin
            if (neg[pp_idx])
                result -= RESULT_WIDTH'($signed(partial_product[pp_idx])) << pp_idx * 2;
            else
                result += RESULT_WIDTH'($signed(partial_product[pp_idx])) << pp_idx * 2;
        end
    end

    always_ff @(posedge clk, posedge reset)
    begin
        if (reset)
        begin
            cycle <= 0;
        end
        else
        begin
            cycle <= cycle + 1;

            $display("result %d (%x)\n", $signed(result), result);
            unique case (cycle)
                0:
                begin
                    // one identity
                    multiplier <= 32'h1B65D66C;
                    multiplicand <= 32'h1;
                end

                1:  assert(result == 64'h1B65D66C);

                2:
                begin
                    // -1 * -1
                    multiplier <= 32'hffffffff;
                    multiplicand <= 32'hffffffff;
                end

                3: assert(result == 1);

                4:
                begin
                    multiplier <= -7;
                    multiplicand <= 6;
                end

                5: assert(result == -42);

                6:
                begin
                    multiplier <= 9;
                    multiplicand <= 8;
                end

                7: assert(result == 72);

                8:
                begin
                    multiplier <= 32'h1c67a408;
                    multiplicand <= 32'h0287d2e;
                end

                9: assert(result == 64'h47e1556f76170);

                10:
                begin
                    $display("PASS");
                    $finish;
                end
            endcase
        end
    end
endmodule