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April 10, 2018 20:20
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(peripheral | |
(group-name USART) | |
(register | |
(name CR1) | |
(offset 0x0) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Control register 1") | |
(field | |
(name M1) | |
(bit-offset 28) | |
(bit-width 1) | |
(description "Word length - Bit 1") | |
) | |
(field | |
(name EOBIE) | |
(bit-offset 27) | |
(bit-width 1) | |
(description "End of Block interrupt enable") | |
) | |
(field | |
(name RTOIE) | |
(bit-offset 26) | |
(bit-width 1) | |
(description "Receiver timeout interrupt enable") | |
) | |
(field | |
(name DEAT) | |
(bit-offset 21) | |
(bit-width 5) | |
(description "Driver Enable assertion time") | |
) | |
(field | |
(name DEDT) | |
(bit-offset 16) | |
(bit-width 5) | |
(description "Driver Enable deassertion time") | |
) | |
(field | |
(name OVER8) | |
(bit-offset 15) | |
(bit-width 1) | |
(description "Oversampling mode") | |
) | |
(field | |
(name CMIE) | |
(bit-offset 14) | |
(bit-width 1) | |
(description "Character match interrupt enable") | |
) | |
(field | |
(name MME) | |
(bit-offset 13) | |
(bit-width 1) | |
(description "Mute mode enable") | |
) | |
(field | |
(name M0) | |
(bit-offset 12) | |
(bit-width 1) | |
(description "Word length - Bit 0") | |
) | |
(field | |
(name WAKE) | |
(bit-offset 11) | |
(bit-width 1) | |
(description "Receiver wakeup method") | |
) | |
(field | |
(name PCE) | |
(bit-offset 10) | |
(bit-width 1) | |
(description "Parity control enable") | |
) | |
(field | |
(name PS) | |
(bit-offset 9) | |
(bit-width 1) | |
(description "Parity selection") | |
) | |
(field | |
(name PEIE) | |
(bit-offset 8) | |
(bit-width 1) | |
(description "PE interrupt enable") | |
) | |
(field | |
(name TXEIE) | |
(bit-offset 7) | |
(bit-width 1) | |
(description "interrupt enable") | |
) | |
(field | |
(name TCIE) | |
(bit-offset 6) | |
(bit-width 1) | |
(description "Transmission complete interrupt enable") | |
) | |
(field | |
(name RXNEIE) | |
(bit-offset 5) | |
(bit-width 1) | |
(description "RXNE interrupt enable") | |
) | |
(field | |
(name IDLEIE) | |
(bit-offset 4) | |
(bit-width 1) | |
(description "IDLE interrupt enable") | |
) | |
(field | |
(name TE) | |
(bit-offset 3) | |
(bit-width 1) | |
(description "Transmitter enable") | |
) | |
(field | |
(name RE) | |
(bit-offset 2) | |
(bit-width 1) | |
(description "Receiver enable") | |
) | |
(field | |
(name UESM) | |
(bit-offset 1) | |
(bit-width 1) | |
(description "USART enable in Stop mode") | |
) | |
(field | |
(name UE) | |
(bit-offset 0) | |
(bit-width 1) | |
(description "USART enable") | |
) | |
) | |
(register | |
(name CR2) | |
(offset 0x4) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Control register 2") | |
(field | |
(name ADD4) | |
(bit-offset 28) | |
(bit-width 4) | |
(description "Address of the USART node") | |
) | |
(field | |
(name ADD0) | |
(bit-offset 24) | |
(bit-width 4) | |
(description "Address of the USART node") | |
) | |
(field | |
(name RTOEN) | |
(bit-offset 23) | |
(bit-width 1) | |
(description "Receiver timeout enable") | |
) | |
(field | |
(name ABRMOD) | |
(bit-offset 21) | |
(bit-width 2) | |
(description "Auto baud rate mode") | |
) | |
(field | |
(name ABREN) | |
(bit-offset 20) | |
(bit-width 1) | |
(description "Auto baud rate enable") | |
) | |
(field | |
(name MSBFIRST) | |
(bit-offset 19) | |
(bit-width 1) | |
(description "Most significant bit first") | |
) | |
(field | |
(name DATAINV) | |
(bit-offset 18) | |
(bit-width 1) | |
(description "Binary data inversion") | |
) | |
(field | |
(name TXINV) | |
(bit-offset 17) | |
(bit-width 1) | |
(description "TX pin active level inversion") | |
) | |
(field | |
(name RXINV) | |
(bit-offset 16) | |
(bit-width 1) | |
(description "RX pin active level inversion") | |
) | |
(field | |
(name SWAP) | |
(bit-offset 15) | |
(bit-width 1) | |
(description "Swap TX/RX pins") | |
) | |
(field | |
(name LINEN) | |
(bit-offset 14) | |
(bit-width 1) | |
(description "LIN mode enable") | |
) | |
(field | |
(name STOP) | |
(bit-offset 12) | |
(bit-width 2) | |
(description "STOP bits") | |
) | |
(field | |
(name CLKEN) | |
(bit-offset 11) | |
(bit-width 1) | |
(description "Clock enable") | |
) | |
(field | |
(name CPOL) | |
(bit-offset 10) | |
(bit-width 1) | |
(description "Clock polarity") | |
) | |
(field | |
(name CPHA) | |
(bit-offset 9) | |
(bit-width 1) | |
(description "Clock phase") | |
) | |
(field | |
(name LBCL) | |
(bit-offset 8) | |
(bit-width 1) | |
(description "Last bit clock pulse") | |
) | |
(field | |
(name LBDIE) | |
(bit-offset 6) | |
(bit-width 1) | |
(description "LIN break detection interrupt enable") | |
) | |
(field | |
(name LBDL) | |
(bit-offset 5) | |
(bit-width 1) | |
(description "LIN break detection length") | |
) | |
(field | |
(name ADDM7) | |
(bit-offset 4) | |
(bit-width 1) | |
(description "7-bit Address Detection/4-bit Address Detection") | |
) | |
) | |
(register | |
(name CR3) | |
(offset 0x8) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Control register 3") | |
(field | |
(name WUFIE) | |
(bit-offset 22) | |
(bit-width 1) | |
(description "Wakeup from Stop mode interrupt enable") | |
) | |
(field | |
(name WUS) | |
(bit-offset 20) | |
(bit-width 2) | |
(description "Wakeup from Stop mode interrupt flag selection") | |
) | |
(field | |
(name SCARCNT) | |
(bit-offset 17) | |
(bit-width 3) | |
(description "Smartcard auto-retry count") | |
) | |
(field | |
(name DEP) | |
(bit-offset 15) | |
(bit-width 1) | |
(description "Driver enable polarity selection") | |
) | |
(field | |
(name DEM) | |
(bit-offset 14) | |
(bit-width 1) | |
(description "Driver enable mode") | |
) | |
(field | |
(name DDRE) | |
(bit-offset 13) | |
(bit-width 1) | |
(description "DMA Disable on Reception Error") | |
) | |
(field | |
(name OVRDIS) | |
(bit-offset 12) | |
(bit-width 1) | |
(description "Overrun Disable") | |
) | |
(field | |
(name ONEBIT) | |
(bit-offset 11) | |
(bit-width 1) | |
(description "One sample bit method enable") | |
) | |
(field | |
(name CTSIE) | |
(bit-offset 10) | |
(bit-width 1) | |
(description "CTS interrupt enable") | |
) | |
(field | |
(name CTSE) | |
(bit-offset 9) | |
(bit-width 1) | |
(description "CTS enable") | |
) | |
(field | |
(name RTSE) | |
(bit-offset 8) | |
(bit-width 1) | |
(description "RTS enable") | |
) | |
(field | |
(name DMAT) | |
(bit-offset 7) | |
(bit-width 1) | |
(description "DMA enable transmitter") | |
) | |
(field | |
(name DMAR) | |
(bit-offset 6) | |
(bit-width 1) | |
(description "DMA enable receiver") | |
) | |
(field | |
(name SCEN) | |
(bit-offset 5) | |
(bit-width 1) | |
(description "Smartcard mode enable") | |
) | |
(field | |
(name NACK) | |
(bit-offset 4) | |
(bit-width 1) | |
(description "Smartcard NACK enable") | |
) | |
(field | |
(name HDSEL) | |
(bit-offset 3) | |
(bit-width 1) | |
(description "Half-duplex selection") | |
) | |
(field | |
(name IRLP) | |
(bit-offset 2) | |
(bit-width 1) | |
(description "IrDA low-power") | |
) | |
(field | |
(name IREN) | |
(bit-offset 1) | |
(bit-width 1) | |
(description "IrDA mode enable") | |
) | |
(field | |
(name EIE) | |
(bit-offset 0) | |
(bit-width 1) | |
(description "Error interrupt enable") | |
) | |
) | |
(register | |
(name BRR) | |
(offset 0xc) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Baud rate register") | |
(field | |
(name DIV_Mantissa) | |
(bit-offset 4) | |
(bit-width 12) | |
(description "mantissa of USARTDIV") | |
) | |
(field | |
(name DIV_Fraction) | |
(bit-offset 0) | |
(bit-width 4) | |
(description "fraction of USARTDIV") | |
) | |
) | |
(register | |
(name GTPR) | |
(offset 0x10) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Guard time and prescaler register") | |
(field | |
(name GT) | |
(bit-offset 8) | |
(bit-width 8) | |
(description "Guard time value") | |
) | |
(field | |
(name PSC) | |
(bit-offset 0) | |
(bit-width 8) | |
(description "Prescaler value") | |
) | |
) | |
(register | |
(name RTOR) | |
(offset 0x14) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Receiver timeout register") | |
(field | |
(name BLEN) | |
(bit-offset 24) | |
(bit-width 8) | |
(description "Block Length") | |
) | |
(field | |
(name RTO) | |
(bit-offset 0) | |
(bit-width 24) | |
(description "Receiver timeout value") | |
) | |
) | |
(register | |
(name RQR) | |
(offset 0x18) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Request register") | |
(field | |
(name TXFRQ) | |
(bit-offset 4) | |
(bit-width 1) | |
(description "Transmit data flush request") | |
) | |
(field | |
(name RXFRQ) | |
(bit-offset 3) | |
(bit-width 1) | |
(description "Receive data flush request") | |
) | |
(field | |
(name MMRQ) | |
(bit-offset 2) | |
(bit-width 1) | |
(description "Mute mode request") | |
) | |
(field | |
(name SBKRQ) | |
(bit-offset 1) | |
(bit-width 1) | |
(description "Send break request") | |
) | |
(field | |
(name ABRRQ) | |
(bit-offset 0) | |
(bit-width 1) | |
(description "Auto baud rate request") | |
) | |
) | |
(register | |
(name ISR) | |
(offset 0x1c) | |
(size 0x20) | |
(access read-only) | |
(reset-value 0xc0) | |
(description "Interrupt & status register") | |
(field | |
(name REACK) | |
(bit-offset 22) | |
(bit-width 1) | |
(description "Receive enable acknowledge flag") | |
) | |
(field | |
(name TEACK) | |
(bit-offset 21) | |
(bit-width 1) | |
(description "Transmit enable acknowledge flag") | |
) | |
(field | |
(name WUF) | |
(bit-offset 20) | |
(bit-width 1) | |
(description "Wakeup from Stop mode flag") | |
) | |
(field | |
(name RWU) | |
(bit-offset 19) | |
(bit-width 1) | |
(description "Receiver wakeup from Mute mode") | |
) | |
(field | |
(name SBKF) | |
(bit-offset 18) | |
(bit-width 1) | |
(description "Send break flag") | |
) | |
(field | |
(name CMF) | |
(bit-offset 17) | |
(bit-width 1) | |
(description "character match flag") | |
) | |
(field | |
(name BUSY) | |
(bit-offset 16) | |
(bit-width 1) | |
(description "Busy flag") | |
) | |
(field | |
(name ABRF) | |
(bit-offset 15) | |
(bit-width 1) | |
(description "Auto baud rate flag") | |
) | |
(field | |
(name ABRE) | |
(bit-offset 14) | |
(bit-width 1) | |
(description "Auto baud rate error") | |
) | |
(field | |
(name EOBF) | |
(bit-offset 12) | |
(bit-width 1) | |
(description "End of block flag") | |
) | |
(field | |
(name RTOF) | |
(bit-offset 11) | |
(bit-width 1) | |
(description "Receiver timeout") | |
) | |
(field | |
(name CTS) | |
(bit-offset 10) | |
(bit-width 1) | |
(description "CTS flag") | |
) | |
(field | |
(name CTSIF) | |
(bit-offset 9) | |
(bit-width 1) | |
(description "CTS interrupt flag") | |
) | |
(field | |
(name LBDF) | |
(bit-offset 8) | |
(bit-width 1) | |
(description "LIN break detection flag") | |
) | |
(field | |
(name TXE) | |
(bit-offset 7) | |
(bit-width 1) | |
(description "Transmit data register empty") | |
) | |
(field | |
(name TC) | |
(bit-offset 6) | |
(bit-width 1) | |
(description "Transmission complete") | |
) | |
(field | |
(name RXNE) | |
(bit-offset 5) | |
(bit-width 1) | |
(description "Read data register not empty") | |
) | |
(field | |
(name IDLE) | |
(bit-offset 4) | |
(bit-width 1) | |
(description "Idle line detected") | |
) | |
(field | |
(name ORE) | |
(bit-offset 3) | |
(bit-width 1) | |
(description "Overrun error") | |
) | |
(field | |
(name NF) | |
(bit-offset 2) | |
(bit-width 1) | |
(description "Noise detected flag") | |
) | |
(field | |
(name FE) | |
(bit-offset 1) | |
(bit-width 1) | |
(description "Framing error") | |
) | |
(field | |
(name PE) | |
(bit-offset 0) | |
(bit-width 1) | |
(description "Parity error") | |
) | |
) | |
(register | |
(name ICR) | |
(offset 0x20) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Interrupt flag clear register") | |
(field | |
(name WUCF) | |
(bit-offset 20) | |
(bit-width 1) | |
(description "Wakeup from Stop mode clear flag") | |
) | |
(field | |
(name CMCF) | |
(bit-offset 17) | |
(bit-width 1) | |
(description "Character match clear flag") | |
) | |
(field | |
(name EOBCF) | |
(bit-offset 12) | |
(bit-width 1) | |
(description "End of timeout clear flag") | |
) | |
(field | |
(name RTOCF) | |
(bit-offset 11) | |
(bit-width 1) | |
(description "Receiver timeout clear flag") | |
) | |
(field | |
(name CTSCF) | |
(bit-offset 9) | |
(bit-width 1) | |
(description "CTS clear flag") | |
) | |
(field | |
(name LBDCF) | |
(bit-offset 8) | |
(bit-width 1) | |
(description "LIN break detection clear flag") | |
) | |
(field | |
(name TCCF) | |
(bit-offset 6) | |
(bit-width 1) | |
(description "Transmission complete clear flag") | |
) | |
(field | |
(name IDLECF) | |
(bit-offset 4) | |
(bit-width 1) | |
(description "Idle line detected clear flag") | |
) | |
(field | |
(name ORECF) | |
(bit-offset 3) | |
(bit-width 1) | |
(description "Overrun error clear flag") | |
) | |
(field | |
(name NCF) | |
(bit-offset 2) | |
(bit-width 1) | |
(description "Noise detected clear flag") | |
) | |
(field | |
(name FECF) | |
(bit-offset 1) | |
(bit-width 1) | |
(description "Framing error clear flag") | |
) | |
(field | |
(name PECF) | |
(bit-offset 0) | |
(bit-width 1) | |
(description "Parity error clear flag") | |
) | |
) | |
(register | |
(name RDR) | |
(offset 0x24) | |
(size 0x20) | |
(access read-only) | |
(reset-value 0x0) | |
(description "Receive data register") | |
(field | |
(name RDR) | |
(bit-offset 0) | |
(bit-width 9) | |
(description "Receive data value") | |
) | |
) | |
(register | |
(name TDR) | |
(offset 0x28) | |
(size 0x20) | |
(access read-write) | |
(reset-value 0x0) | |
(description "Transmit data register") | |
(field | |
(name TDR) | |
(bit-offset 0) | |
(bit-width 9) | |
(description "Transmit data value") | |
) | |
) | |
) |
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