cpu.v

module cpu;

reg [7:0] ax, bx, ix, pc;
reg [3:0] ir;
reg [7:0] mem [0:255];

// reset
initial begin
  ax <= 0;
  bx <= 0;
  ix <= 0;
  pc <= 0;
  ir <= 0;
end

// load memory
initial begin
  $readmemh ("mem.hex", mem);
  $display ("mem=%h %h %h %h...", mem[0], mem[1], mem[2], mem[3]);
end

always begin
  // fetch
  #1
  ir      <= mem[pc][7:4];
  ix[3:0] <= mem[pc][3:0];
  //phase   <= 2'h1;
  // incr
  #1
  pc <= pc + 1;
  //phase   <= 2'h2;
  // exec
  #1

  if (ir == 4'h9 && ix == 8'hfe)
    $finish;

  case (ir)
    4'h0: ax <= mem[ix];
    4'h1: bx <= mem[ix];
    4'h2: mem[ix] <= ax;
    4'h3: ax <= ix;
    4'h4: bx <= ix;
    4'h5: ax <= (pc + ix);
    4'h6: ax <= mem[ax + ix];
    4'h7: bx <= mem[bx + ix];
    4'h8: mem[ix] <= ax;
    4'h9: pc <= (pc + ix);
    4'ha: if (ax == 0)
            pc <= (pc + ix);
    4'hb: if (ax[7] == 1'b1)
            pc <= (pc + ix);
    4'hc: pc <= bx;
    4'hd: ax <= (ax + bx);
    4'he: ax <= (ax - bx);
    4'hf: ix <= (ix << 4);
  endcase

  verbose();

  if (ir != 4'hf)
    ix <= 0;
  //phase   <= 2'h0;
end

task verbose;
  case (ir)
    4'h0: $display ("cpu@%d LDAM         ax=0x%h         ix=0x%h         mem=0x%h     pc=0x%h", $stime, ax,     ix, mem[ix], pc);
    4'h1: $display ("cpu@%d LDBM                 bx=0x%h ix=0x%h         mem=0x%h     pc=0x%h", $stime,     bx, ix, mem[ix], pc);
    4'h2: $display ("cpu@%d STAM         ax=0x%h         ix=0x%h         mem=0x%h     pc=0x%h", $stime, ax,     ix, mem[ix], pc);
    4'h3: $display ("cpu@%d LDAC         ax=0x%h         ix=0x%h                      pc=0x%h", $stime, ax,     ix, pc);
    4'h4: $display ("cpu@%d LDBC                 bx=0x%h ix=0x%h                      pc=0x%h", $stime,     bx, ix, pc);
    4'h5: $display ("cpu@%d LDAP         ax=0x%h         ix=0x%h pc=0x%h                     ", $stime, ax,     ix, pc);
    4'h6: $display ("cpu@%d LDAI         ax=0x%h         ix=0x%h         mem=0x%h     pc=0x%h", $stime, ax,     ix, mem[ax + ix], pc);
    4'h7: $display ("cpu@%d LDBI                 bx=0x%h ix=0x%h         mem=0x%h     pc=0x%h", $stime,     bx, ix, mem[bx + ix], pc);
    4'h8: $display ("cpu@%d STAI         ax=0x%h bx=0x%h ix=0x%h         mem=0x%h     pc=0x%h", $stime, ax, bx, ix, mem[ix], pc);
    4'h9: $display ("cpu@%d BR                           ix=0x%h pc=0x%h                     ", $stime,         ix, pc);
    4'ha: $display ("cpu@%d BRZ          ax=0x%h         ix=0x%h pc=0x%h                     ", $stime, ax,     ix, pc);
    4'hb: $display ("cpu@%d BRN          ax=0x%h         ix=0x%h pc=0x%h                     ", $stime, ax,     ix, pc);
    4'hc: $display ("cpu@%d BRB                  bx=0x%h         pc=0x%h                     ", $stime,     bx,     pc);
    4'hd: $display ("cpu@%d ADD          ax=0x%h bx=0x%h                              pc=0x%h", $stime, ax, bx,     pc);
    4'he: $display ("cpu@%d SUB          ax=0x%h bx=0x%h                              pc=0x%h", $stime, ax, bx,     pc);
    4'hf: $display ("cpu@%d PFIX                         ix=0x%h                      pc=0x%h", $stime,         ix, pc);
  endcase
endtask

endmodule