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@jeasonstudio
Created March 12, 2017 13:28
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串并转换
module spps (clk, rst_n, en, si, po, flag, load, pi, so, sign );
input clk;
input rst_n;
input en;
input si;
input load;
input flag;
input [7:0] pi;
output reg so;
output reg [7:0] po;
output reg sign;
reg [7:0] r;
always@(posedge clk )
if(flag)
begin
if(~rst_n)
begin
r <= 16'h0;
end
else
begin
r = {r, si};
if(si||~si)
begin
po = (en) ? r :8'h0;
sign=(en)?1'b1:1'b0;
end
else
begin
po=8'hxxxxxxxx;
sign=1'b0;
end
end
end
else
begin
if(~rst_n) //锟斤拷锟诫串锟斤拷
begin
r <= 8'h0; //锟斤拷锟斤拷锟斤拷位锟脚猴拷rst_n为锟酵碉拷平锟斤拷锟斤拷0000
end
else if(load) //锟斤拷锟斤拷load锟脚猴拷为锟竭碉拷平锟斤拷锟斤拷锟斤拷锟斤拷锟斤拷锟脚猴拷
begin
r <= pi; //锟斤拷锟斤拷锟斤拷值r锟斤拷锟斤拷
end
else //锟斤拷锟斤拷load为锟酵碉拷平锟斤拷锟斤拷锟斤拷锟斤拷锟斤拷锟斤拷锟斤拷
begin
r <= {r, 1'bx}; //锟斤拷位锟侥达拷锟斤拷锟斤拷实锟街o拷锟斤拷锟斤拷r锟斤拷锟斤拷锟斤拷so锟斤拷锟斤拷锟斤拷r锟窖撅拷锟斤拷锟斤拷锟剿碉拷位锟斤拷为x
if(r[7]||~r[7]) //锟叫讹拷r锟侥达拷锟斤拷锟角凤拷锟窖撅拷全锟斤拷锟斤拷锟斤拷为x
begin
so = r[7];
if(r[6]||~r[6]) //锟斤拷r2没锟斤拷锟斤拷锟斤拷之前sign为0
sign=1'b0;
else //锟斤拷r3锟秸革拷锟斤拷锟斤拷锟斤拷瞬锟戒,sign锟斤拷为1
sign=1'b1;
end
else
begin
so=1'bx; //没锟斤拷锟脚猴拷锟斤拷锟斤拷时so锟斤拷为锟斤拷锟斤拷态
sign=0; //锟斤拷志锟斤拷锟铰癸拷锟斤拷
end
end
end
endmodule
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