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jeffy1009/0001-initial-port-of-u-boot-caam-code.patch

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port of u-boot CAAM code to OP-TEE
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0001-initial-port-of-u-boot-caam-code.patch
From f6e25ec9d9a5cbf6b482cc7d8306b6dc9e42ac8f Mon Sep 17 00:00:00 2001
From: Jangseop Shin <jsshin@sor.snu.ac.kr>
Date: Wed, 22 Feb 2017 18:20:08 +0900
Subject: [PATCH 1/5] initial port of u-boot caam code
---
core/arch/arm/plat-imx/caam_cmds.c | 37 ++
core/arch/arm/plat-imx/caam_cmds.h | 8 +
core/arch/arm/plat-imx/clock.c | 32 ++
core/arch/arm/plat-imx/clock.h | 72 +++
core/arch/arm/plat-imx/conf.mk | 5 +
core/arch/arm/plat-imx/crm_regs.h | 1098 ++++++++++++++++++++++++++++++++++++
core/arch/arm/plat-imx/imx-regs.h | 917 ++++++++++++++++++++++++++++++
core/arch/arm/plat-imx/sub.mk | 1 +
core/drivers/crypto/desc.h | 666 ++++++++++++++++++++++
core/drivers/crypto/desc_constr.h | 284 ++++++++++
core/drivers/crypto/error.c | 261 +++++++++
core/drivers/crypto/fsl_blob.c | 110 ++++
core/drivers/crypto/jobdesc.c | 274 +++++++++
core/drivers/crypto/jobdesc.h | 40 ++
core/drivers/crypto/jr.c | 489 ++++++++++++++++
core/drivers/crypto/jr.h | 99 ++++
core/drivers/crypto/misc.h | 16 +
core/drivers/crypto/sub.mk | 1 +
core/drivers/sub.mk | 2 +
core/include/fsl_sec.h | 267 +++++++++
20 files changed, 4679 insertions(+)
create mode 100644 core/arch/arm/plat-imx/caam_cmds.c
create mode 100644 core/arch/arm/plat-imx/caam_cmds.h
create mode 100644 core/arch/arm/plat-imx/clock.c
create mode 100644 core/arch/arm/plat-imx/clock.h
create mode 100644 core/arch/arm/plat-imx/crm_regs.h
create mode 100644 core/arch/arm/plat-imx/imx-regs.h
create mode 100644 core/drivers/crypto/desc.h
create mode 100644 core/drivers/crypto/desc_constr.h
create mode 100644 core/drivers/crypto/error.c
create mode 100644 core/drivers/crypto/fsl_blob.c
create mode 100644 core/drivers/crypto/jobdesc.c
create mode 100644 core/drivers/crypto/jobdesc.h
create mode 100644 core/drivers/crypto/jr.c
create mode 100644 core/drivers/crypto/jr.h
create mode 100644 core/drivers/crypto/misc.h
create mode 100644 core/drivers/crypto/sub.mk
create mode 100644 core/include/fsl_sec.h
diff --git a/core/arch/arm/plat-imx/caam_cmds.c b/core/arch/arm/plat-imx/caam_cmds.c
new file mode 100644
index 0000000..40332d0
--- /dev/null
+++ b/core/arch/arm/plat-imx/caam_cmds.c
@@ -0,0 +1,37 @@
+#include <caam_cmds.h>
+#include <clock.h>
+#include <imx-regs.h>
+#include <io.h>
+#include <stdint.h>
+#include <trace.h>
+#include "fsl_sec.h"
+
+/**
+* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
+* @src: - Address of data to be encapsulated
+* @dst: - Desination address of encapsulated data
+* @len: - Size of data to be encapsulated
+*
+* Returns zero on success,and negative on error.
+*/
+/*static*/ int blob_encap_dek(const uint8_t *src, uint8_t *dst, uint32_t len)
+{
+ int ret = 0;
+ uint32_t jr_size = 4;
+
+ uint32_t out_jr_size = read32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+ if (out_jr_size != jr_size) {
+ caam_clock_enable(1);
+ sec_init();
+ }
+
+ if (!((len == 128) | (len == 192) | (len == 256))) {
+ EMSG("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
+ return -1;
+ }
+
+ len /= 8;
+ ret = blob_dek(src, dst, len);
+
+ return ret;
+}
diff --git a/core/arch/arm/plat-imx/caam_cmds.h b/core/arch/arm/plat-imx/caam_cmds.h
new file mode 100644
index 0000000..4f3bbd9
--- /dev/null
+++ b/core/arch/arm/plat-imx/caam_cmds.h
@@ -0,0 +1,8 @@
+#ifndef CAAM_CMDS_H
+#define CAAM_CMDS_H
+
+#include <stdint.h>
+
+int blob_encap_dek(const uint8_t *src, uint8_t *dst, uint32_t len);
+
+#endif /* CAAM_CMDS_H */
diff --git a/core/arch/arm/plat-imx/clock.c b/core/arch/arm/plat-imx/clock.c
new file mode 100644
index 0000000..64bc93b
--- /dev/null
+++ b/core/arch/arm/plat-imx/clock.c
@@ -0,0 +1,32 @@
+#include <io.h>
+#include <clock.h>
+#include <crm_regs.h>
+#include <imx-regs.h>
+#include "fsl_sec.h"
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+void caam_clock_enable(unsigned char enable)
+{
+ uint32_t reg;
+
+ /* CG4 ~ CG6, CAAM clocks */
+ reg = read32((vaddr_t)&imx_ccm->CCGR0);
+ if (enable)
+ reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ else
+ reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ write32(reg, (vaddr_t)&imx_ccm->CCGR0);
+
+ /* EMI slow clk */
+ reg = read32((vaddr_t)&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ write32(reg, (vaddr_t)&imx_ccm->CCGR6);
+}
diff --git a/core/arch/arm/plat-imx/clock.h b/core/arch/arm/plat-imx/clock.h
new file mode 100644
index 0000000..29084a6
--- /dev/null
+++ b/core/arch/arm/plat-imx/clock.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef CLOCK_H
+#define CLOCK_H
+
+#include <stdint.h>
+
+#ifdef CONFIG_SYS_MX6_HCLK
+#define MXC_HCLK CONFIG_SYS_MX6_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX6_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_PER_CLK,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_CLK,
+ MXC_EMI_SLOW_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_ESDHC4_CLK,
+ MXC_SATA_CLK,
+ MXC_NFC_CLK,
+ MXC_I2C_CLK,
+};
+
+enum enet_freq {
+ ENET_25MHZ,
+ ENET_50MHZ,
+ ENET_100MHZ,
+ ENET_125MHZ,
+};
+
+uint32_t imx_get_uartclk(void);
+uint32_t imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+void setup_gpmi_io_clk(uint32_t cfg);
+void caam_clock_enable(unsigned char enable);
+void enable_ocotp_clk(unsigned char enable);
+void enable_usboh3_clk(unsigned char enable);
+void enable_uart_clk(unsigned char enable);
+int enable_cspi_clock(unsigned char enable, unsigned spi_num);
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
+int enable_sata_clock(void);
+void disable_sata_clock(void);
+int enable_pcie_clock(void);
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+int enable_spi_clk(unsigned char enable, unsigned spi_num);
+void enable_ipu_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
+void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
+void enable_thermal_clk(void);
+#endif /* CLOCK_H */
diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index 785736a..3cdbc9c 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -26,6 +26,11 @@ $(call force,CFG_SECURE_TIME_SOURCE_REE,y)
CFG_BOOT_SYNC_CPU ?= y
CFG_BOOT_SECONDARY_REQUEST ?= y
+
+$(call force,CFG_MX6,y)
+CFG_FSL_CAAM ?= y
+CFG_SYS_FSL_SEC_COMPAT ?= 4
+CFG_SYS_FSL_SEC_LE ?= y
endif
ta-targets = ta_arm32
diff --git a/core/arch/arm/plat-imx/crm_regs.h b/core/arch/arm/plat-imx/crm_regs.h
new file mode 100644
index 0000000..c96afb7
--- /dev/null
+++ b/core/arch/arm/plat-imx/crm_regs.h
@@ -0,0 +1,1098 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef CCM_REGS_H
+#define CCM_REGS_H
+
+#define CCM_CCOSR 0x020c4060
+#define CCM_CCGR0 0x020C4068
+#define CCM_CCGR1 0x020C406c
+#define CCM_CCGR2 0x020C4070
+#define CCM_CCGR3 0x020C4074
+#define CCM_CCGR4 0x020C4078
+#define CCM_CCGR5 0x020C407c
+#define CCM_CCGR6 0x020C4080
+
+#define PMU_MISC2 0x020C8170
+
+#ifndef __ASSEMBLY__
+struct mxc_ccm_reg {
+ uint32_t ccr; /* 0x0000 */
+ uint32_t ccdr;
+ uint32_t csr;
+ uint32_t ccsr;
+ uint32_t cacrr; /* 0x0010*/
+ uint32_t cbcdr;
+ uint32_t cbcmr;
+ uint32_t cscmr1;
+ uint32_t cscmr2; /* 0x0020 */
+ uint32_t cscdr1;
+ uint32_t cs1cdr;
+ uint32_t cs2cdr;
+ uint32_t cdcdr; /* 0x0030 */
+ uint32_t chsccdr;
+ uint32_t cscdr2;
+ uint32_t cscdr3;
+ uint32_t cscdr4; /* 0x0040 */
+ uint32_t resv0;
+ uint32_t cdhipr;
+ uint32_t cdcr;
+ uint32_t ctor; /* 0x0050 */
+ uint32_t clpcr;
+ uint32_t cisr;
+ uint32_t cimr;
+ uint32_t ccosr; /* 0x0060 */
+ uint32_t cgpr;
+ uint32_t CCGR0;
+ uint32_t CCGR1;
+ uint32_t CCGR2; /* 0x0070 */
+ uint32_t CCGR3;
+ uint32_t CCGR4;
+ uint32_t CCGR5;
+ uint32_t CCGR6; /* 0x0080 */
+ uint32_t CCGR7;
+ uint32_t cmeor;
+ uint32_t resv[0xfdd];
+ uint32_t analog_pll_sys; /* 0x4000 */
+ uint32_t analog_pll_sys_set;
+ uint32_t analog_pll_sys_clr;
+ uint32_t analog_pll_sys_tog;
+ uint32_t analog_usb1_pll_480_ctrl; /* 0x4010 */
+ uint32_t analog_usb1_pll_480_ctrl_set;
+ uint32_t analog_usb1_pll_480_ctrl_clr;
+ uint32_t analog_usb1_pll_480_ctrl_tog;
+ uint32_t analog_reserved0[4];
+ uint32_t analog_pll_528; /* 0x4030 */
+ uint32_t analog_pll_528_set;
+ uint32_t analog_pll_528_clr;
+ uint32_t analog_pll_528_tog;
+ uint32_t analog_pll_528_ss; /* 0x4040 */
+ uint32_t analog_reserved1[3];
+ uint32_t analog_pll_528_num; /* 0x4050 */
+ uint32_t analog_reserved2[3];
+ uint32_t analog_pll_528_denom; /* 0x4060 */
+ uint32_t analog_reserved3[3];
+ uint32_t analog_pll_audio; /* 0x4070 */
+ uint32_t analog_pll_audio_set;
+ uint32_t analog_pll_audio_clr;
+ uint32_t analog_pll_audio_tog;
+ uint32_t analog_pll_audio_num; /* 0x4080*/
+ uint32_t analog_reserved4[3];
+ uint32_t analog_pll_audio_denom; /* 0x4090 */
+ uint32_t analog_reserved5[3];
+ uint32_t analog_pll_video; /* 0x40a0 */
+ uint32_t analog_pll_video_set;
+ uint32_t analog_pll_video_clr;
+ uint32_t analog_pll_video_tog;
+ uint32_t analog_pll_video_num; /* 0x40b0 */
+ uint32_t analog_reserved6[3];
+ uint32_t analog_pll_video_denom; /* 0x40c0 */
+ uint32_t analog_reserved7[7];
+ uint32_t analog_pll_enet; /* 0x40e0 */
+ uint32_t analog_pll_enet_set;
+ uint32_t analog_pll_enet_clr;
+ uint32_t analog_pll_enet_tog;
+ uint32_t analog_pfd_480; /* 0x40f0 */
+ uint32_t analog_pfd_480_set;
+ uint32_t analog_pfd_480_clr;
+ uint32_t analog_pfd_480_tog;
+ uint32_t analog_pfd_528; /* 0x4100 */
+ uint32_t analog_pfd_528_set;
+ uint32_t analog_pfd_528_clr;
+ uint32_t analog_pfd_528_tog;
+};
+#endif
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_RBC_EN (1 << 27)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
+#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
+#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
+#define MXC_CCM_CCR_COSC_EN (1 << 12)
+#if (defined(CFG_MX6SL) || defined(CFG_MX6QP))
+#define MXC_CCM_CCR_OSCNT_MASK 0x7F
+#else
+#define MXC_CCM_CCR_OSCNT_MASK 0xFF
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET 0
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
+#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
+#ifdef CFG_MX6QP
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
+#endif
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSC_READY (1 << 5)
+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
+#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
+#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
+#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
+#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
+#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
+#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
+#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
+#endif
+#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
+#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
+#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
+#ifndef CFG_MX6SX
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
+#endif
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
+#ifndef CFG_MX6SX
+#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
+#endif
+#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
+#ifndef CFG_MX6SX
+#ifdef CFG_MX6QP
+#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
+#else
+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
+#endif
+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
+#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
+#endif
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
+#ifdef CFG_MX6SX
+#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
+#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
+#else
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
+#endif
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
+/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
+#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
+#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
+#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
+#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX) || defined(CFG_MX6QP))
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
+#endif
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX))
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
+#endif
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
+
+/* Define the bits in register CSCMR2 */
+#ifdef CFG_MX6SX
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
+#endif
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
+#if (defined(CFG_MX6SX) || defined(CFG_MX6QP))
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
+#endif
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
+
+/* Define the bits in register CSCDR1 */
+#ifndef CFG_MX6SX
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
+#endif
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
+#ifndef CFG_MX6SX
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#endif
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX) || defined(CFG_MX6QP))
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
+#endif
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
+
+/* Define the bits in register CS1CDR */
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
+
+/* Define the bits in register CS2CDR */
+#ifdef CFG_MX6SX
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
+#else
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
+
+#ifdef CFG_MX6QP
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x7) << 15)
+#else
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
+#endif
+#endif
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
+
+/* Define the bits in register CDCDR */
+#ifndef CFG_MX6SX
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
+#endif
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
+
+/* Define the bits in register CHSCCDR */
+#ifdef CFG_MX6SX
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
+#else
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
+#endif
+
+#define CHSCCDR_CLK_SEL_LDB_DI0 3
+#define CHSCCDR_PODF_DIVIDE_BY_3 2
+#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
+#ifdef CFG_MX6QP
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET 18
+#endif
+
+/* All IPU2_DI1 are LCDIF1 on MX6SX */
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
+/* All IPU2_DI0 are LCDIF2 on MX6SX */
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
+#endif
+#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
+#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
+#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
+#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
+#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
+#endif
+#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
+#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
+#endif
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
+#define MXC_CCM_CLPCR_VSTBY (1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
+#define MXC_CCM_CLPCR_SBYOS (1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
+#endif
+#define MXC_CCM_CLPCR_LPM_MASK 0x3
+#define MXC_CCM_CLPCR_LPM_OFFSET 0
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
+#endif
+#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
+#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
+#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
+#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
+#define MXC_CCM_CISR_COSC_READY (1 << 6)
+#define MXC_CCM_CISR_LRF_PLL 1
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
+#endif
+#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
+#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
+#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
+#define MXC_CCM_CIMR_MASK_LRF_PLL 1
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
+#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
+#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK 3
+
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
+#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_OFFSET 6
+#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET 14
+#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET 18
+#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
+#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
+#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
+#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
+#else
+#define MXC_CCM_CCGR0_DTCP_OFFSET 28
+#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
+#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
+#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
+#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
+#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
+#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
+#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
+#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
+#define MXC_CCM_CCGR1_CANFD_OFFSET 30
+#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
+#endif
+
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#else
+#define MXC_CCM_CCGR2_CSI_OFFSET 2
+#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
+#endif
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#endif
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
+#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
+#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
+#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR2_LCD_OFFSET 28
+#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
+#define MXC_CCM_CCGR2_PXP_OFFSET 30
+#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
+#else
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+#endif
+
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR3_M4_OFFSET 2
+#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
+#define MXC_CCM_CCGR3_ENET_OFFSET 4
+#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
+#define MXC_CCM_CCGR3_QSPI_OFFSET 14
+#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
+#else
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#endif
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
+#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
+#else
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#endif
+#define MXC_CCM_CCGR3_MLB_OFFSET 18
+#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#endif
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
+#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET 0
+#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
+#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
+#else
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#endif
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET 16
+#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET 18
+#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET 20
+#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET 22
+#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET 0
+#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR5_SATA_OFFSET 4
+#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
+#endif
+#define MXC_CCM_CCGR5_SDMA_OFFSET 6
+#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET 12
+#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
+#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET 18
+#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET 20
+#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET 22
+#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET 24
+#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR5_SAI1_OFFSET 20
+#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
+#define MXC_CCM_CCGR5_SAI2_OFFSET 30
+#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR6_PWM8_OFFSET 16
+#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
+#define MXC_CCM_CCGR6_VADC_OFFSET 20
+#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
+#define MXC_CCM_CCGR6_GIS_OFFSET 22
+#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
+#define MXC_CCM_CCGR6_I2C4_OFFSET 24
+#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
+#define MXC_CCM_CCGR6_PWM5_OFFSET 26
+#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
+#define MXC_CCM_CCGR6_PWM6_OFFSET 28
+#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
+#define MXC_CCM_CCGR6_PWM7_OFFSET 30
+#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
+#else
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#ifdef CFG_MX6QP
+#define MXC_CCM_CCGR6_VPUCLK_OFFSET 14
+#define MXC_CCM_CCGR6_VPUCLK_MASK (3 << MXC_CCM_CCGR6_VPUCLK_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK0_OFFSET 16
+#define MXC_CCM_CCGR6_PRE_CLK0_MASK (3 << MXC_CCM_CCGR6_PRE_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK1_OFFSET 18
+#define MXC_CCM_CCGR6_PRE_CLK1_MASK (3 << MXC_CCM_CCGR6_PRE_CLK1_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK2_OFFSET 20
+#define MXC_CCM_CCGR6_PRE_CLK2_MASK (3 << MXC_CCM_CCGR6_PRE_CLK2_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK3_OFFSET 22
+#define MXC_CCM_CCGR6_PRE_CLK3_MASK (3 << MXC_CCM_CCGR6_PRE_CLK3_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET 24
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK1_OFFSET 26
+#define MXC_CCM_CCGR6_PRG_CLK1_MASK (3 << MXC_CCM_CCGR6_PRG_CLK1_OFFSET)
+#endif
+#endif
+
+#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+#define BP_ANADIG_PLL_SYS_RSVD0 20
+#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
+#define BF_ANADIG_PLL_SYS_RSVD0(v) \
+ (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
+#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
+#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
+#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
+#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
+#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
+#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
+ (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
+ (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_528_LOCK 0x80000000
+#define BP_ANADIG_PLL_528_RSVD1 19
+#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
+#define BF_ANADIG_PLL_528_RSVD1(v) \
+ (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_528_BYPASS 0x00010000
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_528_ENABLE 0x00002000
+#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_528_RSVD0 1
+#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
+#define BF_ANADIG_PLL_528_RSVD0(v) \
+ (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
+#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
+
+#define BP_ANADIG_PLL_528_SS_STOP 16
+#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
+#define BF_ANADIG_PLL_528_SS_STOP(v) \
+ (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
+#define BP_ANADIG_PLL_528_SS_STEP 0
+#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
+#define BF_ANADIG_PLL_528_SS_STEP(v) \
+ (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
+
+#define BP_ANADIG_PLL_528_NUM_RSVD0 30
+#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
+#define BP_ANADIG_PLL_528_NUM_A 0
+#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_NUM_A(v) \
+ (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
+
+#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
+#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
+#define BP_ANADIG_PLL_528_DENOM_B 0
+#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_DENOM_B(v) \
+ (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
+#define BP_ANADIG_PLL_AUDIO_RSVD0 22
+#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
+ (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
+#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
+#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
+#define BP_ANADIG_PLL_VIDEO_RSVD0 22
+#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
+ (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
+#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
+#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
+#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
+#define BP_ANADIG_PLL_ENET_RSVD1 21
+#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
+#define BF_ANADIG_PLL_ENET_RSVD1(v) \
+ (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
+#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_ENET_RSVD0 2
+#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
+#define BF_ANADIG_PLL_ENET_RSVD0(v) \
+ (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
+ (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_480_PFD2_FRAC 16
+#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
+ (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_480_PFD1_FRAC 8
+#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
+ (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_480_PFD0_FRAC 0
+#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
+ (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_528_PFD3_FRAC 24
+#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
+ (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_528_PFD2_FRAC 16
+#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
+ (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_528_PFD1_FRAC 8
+#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
+ (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_528_PFD0_FRAC 0
+#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
+ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+
+#endif /*CCM_REGS_H */
diff --git a/core/arch/arm/plat-imx/imx-regs.h b/core/arch/arm/plat-imx/imx-regs.h
new file mode 100644
index 0000000..32baed5
--- /dev/null
+++ b/core/arch/arm/plat-imx/imx-regs.h
@@ -0,0 +1,917 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX_REGS_H
+#define IMX_REGS_H
+
+#define ARCH_MXC
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define ROMCP_ARB_BASE_ADDR 0x00000000
+#define ROMCP_ARB_END_ADDR 0x000FFFFF
+
+#ifdef CFG_MX6SL
+#define GPU_2D_ARB_BASE_ADDR 0x02200000
+#define GPU_2D_ARB_END_ADDR 0x02203FFF
+#define OPENVG_ARB_BASE_ADDR 0x02204000
+#define OPENVG_ARB_END_ADDR 0x02207FFF
+#elifdef CFG_MX6SX
+#define CAAM_ARB_BASE_ADDR 0x00100000
+#define CAAM_ARB_END_ADDR 0x00107FFF
+#define GPU_ARB_BASE_ADDR 0x01800000
+#define GPU_ARB_END_ADDR 0x01803FFF
+#define APBH_DMA_ARB_BASE_ADDR 0x01804000
+#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
+#define M4_BOOTROM_BASE_ADDR 0x007F8000
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+#else
+#define CAAM_ARB_BASE_ADDR 0x00100000
+#define CAAM_ARB_END_ADDR 0x00103FFF
+#define APBH_DMA_ARB_BASE_ADDR 0x00110000
+#define APBH_DMA_ARB_END_ADDR 0x00117FFF
+#define HDMI_ARB_BASE_ADDR 0x00120000
+#define HDMI_ARB_END_ADDR 0x00128FFF
+#define GPU_3D_ARB_BASE_ADDR 0x00130000
+#define GPU_3D_ARB_END_ADDR 0x00133FFF
+#define GPU_2D_ARB_BASE_ADDR 0x00134000
+#define GPU_2D_ARB_END_ADDR 0x00137FFF
+#define DTCP_ARB_BASE_ADDR 0x00138000
+#define DTCP_ARB_END_ADDR 0x0013BFFF
+#endif /* CFG_MX6SL */
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+/* GPV - PL301 configuration ports */
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX))
+#define GPV2_BASE_ADDR 0x00D00000
+#else
+#define GPV2_BASE_ADDR 0x00200000
+#endif
+
+#ifdef CFG_MX6SX
+#define GPV3_BASE_ADDR 0x00E00000
+#define GPV4_BASE_ADDR 0x00F00000
+#define GPV5_BASE_ADDR 0x01000000
+#define GPV6_BASE_ADDR 0x01100000
+#define PCIE_ARB_BASE_ADDR 0x08000000
+#define PCIE_ARB_END_ADDR 0x08FFFFFF
+
+#else
+#define GPV3_BASE_ADDR 0x00300000
+#define GPV4_BASE_ADDR 0x00800000
+#define PCIE_ARB_BASE_ADDR 0x01000000
+#define PCIE_ARB_END_ADDR 0x01FFFFFF
+#endif
+
+#define IRAM_BASE_ADDR 0x00900000
+#define SCU_BASE_ADDR 0x00A00000
+#define IC_INTERFACES_BASE_ADDR 0x00A00100
+#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
+#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
+#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+#define L2_PL310_BASE 0x00A02000
+#define GPV0_BASE_ADDR 0x00B00000
+#define GPV1_BASE_ADDR 0x00C00000
+
+#define AIPS1_ARB_BASE_ADDR 0x02000000
+#define AIPS1_ARB_END_ADDR 0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR 0x02100000
+#define AIPS2_ARB_END_ADDR 0x021FFFFF
+#ifdef CFG_MX6SX
+#define AIPS3_ARB_BASE_ADDR 0x02200000
+#define AIPS3_ARB_END_ADDR 0x022FFFFF
+#define WEIM_ARB_BASE_ADDR 0x50000000
+#define WEIM_ARB_END_ADDR 0x57FFFFFF
+#define QSPI0_AMBA_BASE 0x60000000
+#define QSPI0_AMBA_END 0x6FFFFFFF
+#define QSPI1_AMBA_BASE 0x70000000
+#define QSPI1_AMBA_END 0x7FFFFFFF
+#else
+#define SATA_ARB_BASE_ADDR 0x02200000
+#define SATA_ARB_END_ADDR 0x02203FFF
+#define OPENVG_ARB_BASE_ADDR 0x02204000
+#define OPENVG_ARB_END_ADDR 0x02207FFF
+#define HSI_ARB_BASE_ADDR 0x02208000
+#define HSI_ARB_END_ADDR 0x0220BFFF
+#define IPU1_ARB_BASE_ADDR 0x02400000
+#define IPU1_ARB_END_ADDR 0x027FFFFF
+#define IPU2_ARB_BASE_ADDR 0x02800000
+#define IPU2_ARB_END_ADDR 0x02BFFFFF
+#define WEIM_ARB_BASE_ADDR 0x08000000
+#define WEIM_ARB_END_ADDR 0x0FFFFFFF
+#endif
+
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX))
+#define MMDC0_ARB_BASE_ADDR 0x80000000
+#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0xC0000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#else
+#define MMDC0_ARB_BASE_ADDR 0x10000000
+#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0x80000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#endif
+
+#ifndef CFG_MX6SX
+#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
+#define IPU_SOC_OFFSET 0x00200000
+#endif
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
+#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+
+#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
+#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
+#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
+#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
+#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
+#ifdef CFG_MX6SL
+#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
+#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+#else
+#ifndef CFG_MX6SX
+#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#endif
+/* #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) */
+#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#endif
+
+#ifndef CFG_MX6SX
+#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
+#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
+#endif
+#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
+
+#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
+#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
+#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
+#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
+#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
+#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
+#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
+#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
+#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
+#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
+#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
+#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
+#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
+#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
+#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
+#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
+#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
+#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
+#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
+#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
+#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
+#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
+#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
+#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
+#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
+#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
+#ifdef CFG_MX6SL
+#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#elifdef CFG_MX6SX
+#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
+#else
+#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#endif
+
+#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
+#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
+#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
+
+#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
+#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
+
+#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
+
+#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
+#ifdef CFG_MX6SL
+#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#else
+#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#endif
+
+#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
+#ifdef CFG_MX6SL
+#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#elifdef CFG_MX6SX
+#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#else
+#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#endif
+
+#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
+#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
+#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
+#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#ifdef CFG_MX6SX
+#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#else
+#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#endif
+#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
+#ifdef CFG_MX6SX
+#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+#else
+#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+#endif
+#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
+#ifdef CFG_MX6SX
+#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#else
+#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#endif
+/* #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) */
+#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
+
+#ifdef CFG_MX6SX
+#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
+#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
+#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
+#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
+#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
+#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
+#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
+#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
+#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
+#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
+#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
+#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
+#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
+#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
+#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
+#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
+#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
+#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#endif
+
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_5 0x15
+#define CHIP_REV_2_0 0x20
+#ifndef CFG_MX6SX
+#define IRAM_SIZE 0x00040000
+#else
+#define IRAM_SIZE 0x00020000
+#endif
+#define FEC_QUIRK_ENET_MAC
+
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+#define SRC_SCR_CORE_1_RESET_OFFSET 14
+#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET 15
+#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET 16
+#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET 22
+#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET 23
+#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
+#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+
+/* WEIM registers */
+struct weim {
+ uint32_t cs0gcr1;
+ uint32_t cs0gcr2;
+ uint32_t cs0rcr1;
+ uint32_t cs0rcr2;
+ uint32_t cs0wcr1;
+ uint32_t cs0wcr2;
+
+ uint32_t cs1gcr1;
+ uint32_t cs1gcr2;
+ uint32_t cs1rcr1;
+ uint32_t cs1rcr2;
+ uint32_t cs1wcr1;
+ uint32_t cs1wcr2;
+
+ uint32_t cs2gcr1;
+ uint32_t cs2gcr2;
+ uint32_t cs2rcr1;
+ uint32_t cs2rcr2;
+ uint32_t cs2wcr1;
+ uint32_t cs2wcr2;
+
+ uint32_t cs3gcr1;
+ uint32_t cs3gcr2;
+ uint32_t cs3rcr1;
+ uint32_t cs3rcr2;
+ uint32_t cs3wcr1;
+ uint32_t cs3wcr2;
+
+ uint32_t unused[12];
+
+ uint32_t wcr;
+ uint32_t wiar;
+ uint32_t ear;
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+ uint32_t scr;
+ uint32_t sbmr1;
+ uint32_t srsr;
+ uint32_t reserved1[2];
+ uint32_t sisr;
+ uint32_t simr;
+ uint32_t sbmr2;
+ uint32_t gpr1;
+ uint32_t gpr2;
+ uint32_t gpr3;
+ uint32_t gpr4;
+ uint32_t gpr5;
+ uint32_t gpr6;
+ uint32_t gpr7;
+ uint32_t gpr8;
+ uint32_t gpr9;
+ uint32_t gpr10;
+};
+
+struct snvs_regs {
+ uint32_t hplr; /* 0x00 */
+ uint32_t hpcomr; /* 0x04 */
+ uint32_t hpcr; /* 0x08 */
+ uint32_t spare1; /* 0x0c */
+ uint32_t spare2; /* 0x10 */
+ uint32_t hpsr; /* 0x14 */
+ uint32_t spare3; /* 0x18 */
+ uint32_t spare4; /* 0x1c */
+ uint32_t spare5; /* 0x20 */
+ uint32_t hprtcmr; /* 0x24 */
+ uint32_t hprtclr; /* 0x28 */
+ uint32_t hptamr; /* 0x2c */
+ uint32_t hptalr; /* 0x30 */
+ uint32_t lplr; /* 0x34 */
+ uint32_t lpcr; /* 0x38 */
+ uint32_t spare6; /* 0x3c */
+ uint32_t spare7; /* 0x40 */
+ uint32_t spare8; /* 0x44 */
+ uint32_t spare9; /* 0x48 */
+ uint32_t lpsr; /* 0x4c */
+ uint32_t spare10; /* 0x50 */
+ uint32_t spare11; /* 0x54 */
+ uint32_t spare12; /* 0x58 */
+ uint32_t lpsmcmr; /* 0x5c */
+ uint32_t lpsmclr; /* 0x60 */
+ uint32_t spare13; /* 0x64 */
+ uint32_t lpgpr; /* 0x68 */
+ uint8_t spare_block[0xbf8 - 0x6c]; /* 0x6c */
+ uint32_t hpvidr1; /* 0xbf8 */
+ uint32_t hpvidr2; /* 0xbfc */
+};
+
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
+#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+
+/* GPR3 bitfields */
+#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
+#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
+#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
+#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
+
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+
+
+struct iomuxc {
+#ifdef CFG_MX6SX
+ uint8_t reserved[0x4000];
+#endif
+ uint32_t gpr[14];
+};
+
+struct gpc {
+ uint32_t cntr;
+ uint32_t pgr;
+ uint32_t imr1;
+ uint32_t imr2;
+ uint32_t imr3;
+ uint32_t imr4;
+ uint32_t isr1;
+ uint32_t isr2;
+ uint32_t isr3;
+ uint32_t isr4;
+};
+
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+
+#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
+#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
+
+#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_BITMAP_SPWG 0
+#define IOMUXC_GPR2_BITMAP_JEIDA 1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18 0
+#define IOMUXC_GPR2_DATA_WIDTH_24 1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED 0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
+
+#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
+/* ECSPI registers */
+struct cspi_regs {
+ uint32_t rxdata;
+ uint32_t txdata;
+ uint32_t ctrl;
+ uint32_t cfg;
+ uint32_t intr;
+ uint32_t dma;
+ uint32_t stat;
+ uint32_t period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN (1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC (1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 32
+#define SPI_MAX_NUM 4
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+#if defined(CFG_MX6SL) || defined(CFG_MX6DL)
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR
+#else
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR, \
+ ECSPI5_BASE_ADDR
+#endif
+
+struct ocotp_regs {
+ uint32_t ctrl;
+ uint32_t ctrl_set;
+ uint32_t ctrl_clr;
+ uint32_t ctrl_tog;
+ uint32_t timing;
+ uint32_t rsvd0[3];
+ uint32_t data;
+ uint32_t rsvd1[3];
+ uint32_t read_ctrl;
+ uint32_t rsvd2[3];
+ uint32_t read_fuse_data;
+ uint32_t rsvd3[3];
+ uint32_t sw_sticky;
+ uint32_t rsvd4[3];
+ uint32_t scs;
+ uint32_t scs_set;
+ uint32_t scs_clr;
+ uint32_t scs_tog;
+ uint32_t crc_addr;
+ uint32_t rsvd5[3];
+ uint32_t crc_value;
+ uint32_t rsvd6[3];
+ uint32_t version;
+ uint32_t rsvd7[0xdb];
+
+ struct fuse_bank {
+ uint32_t fuse_regs[0x20];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ uint32_t lock;
+ uint32_t rsvd0[3];
+ uint32_t uid_low;
+ uint32_t rsvd1[3];
+ uint32_t uid_high;
+ uint32_t rsvd2[3];
+ uint32_t cfg2;
+ uint32_t rsvd3[3];
+ uint32_t cfg3;
+ uint32_t rsvd4[3];
+ uint32_t cfg4;
+ uint32_t rsvd5[3];
+ uint32_t cfg5;
+ uint32_t rsvd6[3];
+ uint32_t cfg6;
+ uint32_t rsvd7[3];
+};
+
+struct fuse_bank1_regs {
+ uint32_t mem0;
+ uint32_t rsvd0[3];
+ uint32_t mem1;
+ uint32_t rsvd1[3];
+ uint32_t mem2;
+ uint32_t rsvd2[3];
+ uint32_t mem3;
+ uint32_t rsvd3[3];
+ uint32_t mem4;
+ uint32_t rsvd4[3];
+ uint32_t ana0;
+ uint32_t rsvd5[3];
+ uint32_t ana1;
+ uint32_t rsvd6[3];
+ uint32_t ana2;
+ uint32_t rsvd7[3];
+};
+
+#ifdef CFG_MX6SX
+struct fuse_bank4_regs {
+ uint32_t sjc_resp_low;
+ uint32_t rsvd0[3];
+ uint32_t sjc_resp_high;
+ uint32_t rsvd1[3];
+ uint32_t mac_addr_low;
+ uint32_t rsvd2[3];
+ uint32_t mac_addr_high;
+ uint32_t rsvd3[3];
+ uint32_t mac_addr2;
+ uint32_t rsvd4[7];
+ uint32_t gp1;
+ uint32_t rsvd5[7];
+};
+#else
+struct fuse_bank4_regs {
+ uint32_t sjc_resp_low;
+ uint32_t rsvd0[3];
+ uint32_t sjc_resp_high;
+ uint32_t rsvd1[3];
+ uint32_t mac_addr_low;
+ uint32_t rsvd2[3];
+ uint32_t mac_addr_high;
+ uint32_t rsvd3[0xb];
+ uint32_t gp1;
+ uint32_t rsvd4[3];
+ uint32_t gp2;
+ uint32_t rsvd5[3];
+};
+#endif
+
+struct aipstz_regs {
+ uint32_t mprot0;
+ uint32_t mprot1;
+ uint32_t rsvd[0xe];
+ uint32_t opacr0;
+ uint32_t opacr1;
+ uint32_t opacr2;
+ uint32_t opacr3;
+ uint32_t opacr4;
+};
+
+struct anatop_regs {
+ uint32_t pll_sys; /* 0x000 */
+ uint32_t pll_sys_set; /* 0x004 */
+ uint32_t pll_sys_clr; /* 0x008 */
+ uint32_t pll_sys_tog; /* 0x00c */
+ uint32_t usb1_pll_480_ctrl; /* 0x010 */
+ uint32_t usb1_pll_480_ctrl_set; /* 0x014 */
+ uint32_t usb1_pll_480_ctrl_clr; /* 0x018 */
+ uint32_t usb1_pll_480_ctrl_tog; /* 0x01c */
+ uint32_t usb2_pll_480_ctrl; /* 0x020 */
+ uint32_t usb2_pll_480_ctrl_set; /* 0x024 */
+ uint32_t usb2_pll_480_ctrl_clr; /* 0x028 */
+ uint32_t usb2_pll_480_ctrl_tog; /* 0x02c */
+ uint32_t pll_528; /* 0x030 */
+ uint32_t pll_528_set; /* 0x034 */
+ uint32_t pll_528_clr; /* 0x038 */
+ uint32_t pll_528_tog; /* 0x03c */
+ uint32_t pll_528_ss; /* 0x040 */
+ uint32_t rsvd0[3];
+ uint32_t pll_528_num; /* 0x050 */
+ uint32_t rsvd1[3];
+ uint32_t pll_528_denom; /* 0x060 */
+ uint32_t rsvd2[3];
+ uint32_t pll_audio; /* 0x070 */
+ uint32_t pll_audio_set; /* 0x074 */
+ uint32_t pll_audio_clr; /* 0x078 */
+ uint32_t pll_audio_tog; /* 0x07c */
+ uint32_t pll_audio_num; /* 0x080 */
+ uint32_t rsvd3[3];
+ uint32_t pll_audio_denom; /* 0x090 */
+ uint32_t rsvd4[3];
+ uint32_t pll_video; /* 0x0a0 */
+ uint32_t pll_video_set; /* 0x0a4 */
+ uint32_t pll_video_clr; /* 0x0a8 */
+ uint32_t pll_video_tog; /* 0x0ac */
+ uint32_t pll_video_num; /* 0x0b0 */
+ uint32_t rsvd5[3];
+ uint32_t pll_video_denom; /* 0x0c0 */
+ uint32_t rsvd6[3];
+ uint32_t pll_mlb; /* 0x0d0 */
+ uint32_t pll_mlb_set; /* 0x0d4 */
+ uint32_t pll_mlb_clr; /* 0x0d8 */
+ uint32_t pll_mlb_tog; /* 0x0dc */
+ uint32_t pll_enet; /* 0x0e0 */
+ uint32_t pll_enet_set; /* 0x0e4 */
+ uint32_t pll_enet_clr; /* 0x0e8 */
+ uint32_t pll_enet_tog; /* 0x0ec */
+ uint32_t pfd_480; /* 0x0f0 */
+ uint32_t pfd_480_set; /* 0x0f4 */
+ uint32_t pfd_480_clr; /* 0x0f8 */
+ uint32_t pfd_480_tog; /* 0x0fc */
+ uint32_t pfd_528; /* 0x100 */
+ uint32_t pfd_528_set; /* 0x104 */
+ uint32_t pfd_528_clr; /* 0x108 */
+ uint32_t pfd_528_tog; /* 0x10c */
+ uint32_t reg_1p1; /* 0x110 */
+ uint32_t reg_1p1_set; /* 0x114 */
+ uint32_t reg_1p1_clr; /* 0x118 */
+ uint32_t reg_1p1_tog; /* 0x11c */
+ uint32_t reg_3p0; /* 0x120 */
+ uint32_t reg_3p0_set; /* 0x124 */
+ uint32_t reg_3p0_clr; /* 0x128 */
+ uint32_t reg_3p0_tog; /* 0x12c */
+ uint32_t reg_2p5; /* 0x130 */
+ uint32_t reg_2p5_set; /* 0x134 */
+ uint32_t reg_2p5_clr; /* 0x138 */
+ uint32_t reg_2p5_tog; /* 0x13c */
+ uint32_t reg_core; /* 0x140 */
+ uint32_t reg_core_set; /* 0x144 */
+ uint32_t reg_core_clr; /* 0x148 */
+ uint32_t reg_core_tog; /* 0x14c */
+ uint32_t ana_misc0; /* 0x150 */
+ uint32_t ana_misc0_set; /* 0x154 */
+ uint32_t ana_misc0_clr; /* 0x158 */
+ uint32_t ana_misc0_tog; /* 0x15c */
+ uint32_t ana_misc1; /* 0x160 */
+ uint32_t ana_misc1_set; /* 0x164 */
+ uint32_t ana_misc1_clr; /* 0x168 */
+ uint32_t ana_misc1_tog; /* 0x16c */
+ uint32_t ana_misc2; /* 0x170 */
+ uint32_t ana_misc2_set; /* 0x174 */
+ uint32_t ana_misc2_clr; /* 0x178 */
+ uint32_t ana_misc2_tog; /* 0x17c */
+ uint32_t tempsense0; /* 0x180 */
+ uint32_t tempsense0_set; /* 0x184 */
+ uint32_t tempsense0_clr; /* 0x188 */
+ uint32_t tempsense0_tog; /* 0x18c */
+ uint32_t tempsense1; /* 0x190 */
+ uint32_t tempsense1_set; /* 0x194 */
+ uint32_t tempsense1_clr; /* 0x198 */
+ uint32_t tempsense1_tog; /* 0x19c */
+ uint32_t usb1_vbus_detect; /* 0x1a0 */
+ uint32_t usb1_vbus_detect_set; /* 0x1a4 */
+ uint32_t usb1_vbus_detect_clr; /* 0x1a8 */
+ uint32_t usb1_vbus_detect_tog; /* 0x1ac */
+ uint32_t usb1_chrg_detect; /* 0x1b0 */
+ uint32_t usb1_chrg_detect_set; /* 0x1b4 */
+ uint32_t usb1_chrg_detect_clr; /* 0x1b8 */
+ uint32_t usb1_chrg_detect_tog; /* 0x1bc */
+ uint32_t usb1_vbus_det_stat; /* 0x1c0 */
+ uint32_t usb1_vbus_det_stat_set; /* 0x1c4 */
+ uint32_t usb1_vbus_det_stat_clr; /* 0x1c8 */
+ uint32_t usb1_vbus_det_stat_tog; /* 0x1cc */
+ uint32_t usb1_chrg_det_stat; /* 0x1d0 */
+ uint32_t usb1_chrg_det_stat_set; /* 0x1d4 */
+ uint32_t usb1_chrg_det_stat_clr; /* 0x1d8 */
+ uint32_t usb1_chrg_det_stat_tog; /* 0x1dc */
+ uint32_t usb1_loopback; /* 0x1e0 */
+ uint32_t usb1_loopback_set; /* 0x1e4 */
+ uint32_t usb1_loopback_clr; /* 0x1e8 */
+ uint32_t usb1_loopback_tog; /* 0x1ec */
+ uint32_t usb1_misc; /* 0x1f0 */
+ uint32_t usb1_misc_set; /* 0x1f4 */
+ uint32_t usb1_misc_clr; /* 0x1f8 */
+ uint32_t usb1_misc_tog; /* 0x1fc */
+ uint32_t usb2_vbus_detect; /* 0x200 */
+ uint32_t usb2_vbus_detect_set; /* 0x204 */
+ uint32_t usb2_vbus_detect_clr; /* 0x208 */
+ uint32_t usb2_vbus_detect_tog; /* 0x20c */
+ uint32_t usb2_chrg_detect; /* 0x210 */
+ uint32_t usb2_chrg_detect_set; /* 0x214 */
+ uint32_t usb2_chrg_detect_clr; /* 0x218 */
+ uint32_t usb2_chrg_detect_tog; /* 0x21c */
+ uint32_t usb2_vbus_det_stat; /* 0x220 */
+ uint32_t usb2_vbus_det_stat_set; /* 0x224 */
+ uint32_t usb2_vbus_det_stat_clr; /* 0x228 */
+ uint32_t usb2_vbus_det_stat_tog; /* 0x22c */
+ uint32_t usb2_chrg_det_stat; /* 0x230 */
+ uint32_t usb2_chrg_det_stat_set; /* 0x234 */
+ uint32_t usb2_chrg_det_stat_clr; /* 0x238 */
+ uint32_t usb2_chrg_det_stat_tog; /* 0x23c */
+ uint32_t usb2_loopback; /* 0x240 */
+ uint32_t usb2_loopback_set; /* 0x244 */
+ uint32_t usb2_loopback_clr; /* 0x248 */
+ uint32_t usb2_loopback_tog; /* 0x24c */
+ uint32_t usb2_misc; /* 0x250 */
+ uint32_t usb2_misc_set; /* 0x254 */
+ uint32_t usb2_misc_clr; /* 0x258 */
+ uint32_t usb2_misc_tog; /* 0x25c */
+ uint32_t digprog; /* 0x260 */
+ uint32_t reserved1[7];
+ uint32_t digprog_sololite; /* 0x280 */
+};
+
+#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
+#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
+#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
+#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
+#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
+#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
+
+struct wdog_regs {
+ uint16_t wcr; /* Control */
+ uint16_t wsr; /* Service */
+ uint16_t wrsr; /* Reset Status */
+ uint16_t wicr; /* Interrupt Control */
+ uint16_t wmcr; /* Miscellaneous Control */
+};
+
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ uint32_t cr;
+ uint32_t sr;
+ uint32_t ir;
+ uint32_t sar;
+ uint32_t pr;
+ uint32_t cnr;
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* IMX_REGS_H */
diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk
index d0a2f51..42a1a2d 100644
--- a/core/arch/arm/plat-imx/sub.mk
+++ b/core/arch/arm/plat-imx/sub.mk
@@ -3,6 +3,7 @@ srcs-y += main.c
srcs-$(CFG_PL310) += imx_pl310.c
srcs-$(CFG_PSCI_ARM32) += psci.c
+srcs-$(CFG_FSL_CAAM) += clock.c caam_cmds.c
srcs-$(PLATFORM_FLAVOR_mx6qsabrelite) += a9_plat_init.S
srcs-$(PLATFORM_FLAVOR_mx6qsabresd) += a9_plat_init.S
diff --git a/core/drivers/crypto/desc.h b/core/drivers/crypto/desc.h
new file mode 100644
index 0000000..18e2ec8
--- /dev/null
+++ b/core/drivers/crypto/desc.h
@@ -0,0 +1,666 @@
+/*
+ * CAAM descriptor composition header
+ * Definitions to support CAAM descriptor instruction generation
+ *
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on desc.h file in linux drivers/crypto/caam
+ */
+
+#ifndef DESC_H
+#define DESC_H
+
+#define KEY_BLOB_SIZE 32
+#define MAC_SIZE 16
+
+/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
+#define MAX_CAAM_DESCSIZE 64
+
+/* Size of DEK Blob descriptor, inclusive of header */
+#define DEK_BLOB_DESCSIZE 9
+
+/* Block size of any entity covered/uncovered with a KEK/TKEK */
+#define KEK_BLOCKSIZE 16
+
+/*
+ * Supported descriptor command types as they show up
+ * inside a descriptor command word.
+ */
+#define CMD_SHIFT 27
+#define CMD_MASK 0xf8000000
+
+#define CMD_KEY (0x00 << CMD_SHIFT)
+#define CMD_SEQ_KEY (0x01 << CMD_SHIFT)
+#define CMD_LOAD (0x02 << CMD_SHIFT)
+#define CMD_SEQ_LOAD (0x03 << CMD_SHIFT)
+#define CMD_FIFO_LOAD (0x04 << CMD_SHIFT)
+#define CMD_SEQ_FIFO_LOAD (0x05 << CMD_SHIFT)
+#define CMD_STORE (0x0a << CMD_SHIFT)
+#define CMD_SEQ_STORE (0x0b << CMD_SHIFT)
+#define CMD_FIFO_STORE (0x0c << CMD_SHIFT)
+#define CMD_SEQ_FIFO_STORE (0x0d << CMD_SHIFT)
+#define CMD_MOVE_LEN (0x0e << CMD_SHIFT)
+#define CMD_MOVE (0x0f << CMD_SHIFT)
+#define CMD_OPERATION (0x10 << CMD_SHIFT)
+#define CMD_SIGNATURE (0x12 << CMD_SHIFT)
+#define CMD_JUMP (0x14 << CMD_SHIFT)
+#define CMD_MATH (0x15 << CMD_SHIFT)
+#define CMD_DESC_HDR (0x16 << CMD_SHIFT)
+#define CMD_SHARED_DESC_HDR (0x17 << CMD_SHIFT)
+#define CMD_SEQ_IN_PTR (0x1e << CMD_SHIFT)
+#define CMD_SEQ_OUT_PTR (0x1f << CMD_SHIFT)
+
+/* General-purpose class selector for all commands */
+#define CLASS_SHIFT 25
+#define CLASS_MASK (0x03 << CLASS_SHIFT)
+
+#define CLASS_NONE (0x00 << CLASS_SHIFT)
+#define CLASS_1 (0x01 << CLASS_SHIFT)
+#define CLASS_2 (0x02 << CLASS_SHIFT)
+#define CLASS_BOTH (0x03 << CLASS_SHIFT)
+
+/*
+ * Descriptor header command constructs
+ * Covers shared, job, and trusted descriptor headers
+ */
+
+/*
+ * Do Not Run - marks a descriptor inexecutable if there was
+ * a preceding error somewhere
+ */
+#define HDR_DNR 0x01000000
+
+/*
+ * ONE - should always be set. Combination of ONE (always
+ * set) and ZRO (always clear) forms an endianness sanity check
+ */
+#define HDR_ONE 0x00800000
+#define HDR_ZRO 0x00008000
+
+/* Start Index or SharedDesc Length */
+#define HDR_START_IDX_MASK 0x3f
+#define HDR_START_IDX_SHIFT 16
+
+/* If shared descriptor header, 6-bit length */
+#define HDR_DESCLEN_SHR_MASK 0x3f
+
+/* If non-shared header, 7-bit length */
+#define HDR_DESCLEN_MASK 0x7f
+
+/* This is a TrustedDesc (if not SharedDesc) */
+#define HDR_TRUSTED 0x00004000
+
+/* Make into TrustedDesc (if not SharedDesc) */
+#define HDR_MAKE_TRUSTED 0x00002000
+
+/* Save context if self-shared (if SharedDesc) */
+#define HDR_SAVECTX 0x00001000
+
+/* Next item points to SharedDesc */
+#define HDR_SHARED 0x00001000
+
+/*
+ * Reverse Execution Order - execute JobDesc first, then
+ * execute SharedDesc (normally SharedDesc goes first).
+ */
+#define HDR_REVERSE 0x00000800
+
+/* Propogate DNR property to SharedDesc */
+#define HDR_PROP_DNR 0x00000800
+
+/* JobDesc/SharedDesc share property */
+#define HDR_SD_SHARE_MASK 0x03
+#define HDR_SD_SHARE_SHIFT 8
+#define HDR_JD_SHARE_MASK 0x07
+#define HDR_JD_SHARE_SHIFT 8
+
+#define HDR_SHARE_NEVER (0x00 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_WAIT (0x01 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_SERIAL (0x02 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_ALWAYS (0x03 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_DEFER (0x04 << HDR_SD_SHARE_SHIFT)
+
+/* JobDesc/SharedDesc descriptor length */
+#define HDR_JD_LENGTH_MASK 0x7f
+#define HDR_SD_LENGTH_MASK 0x3f
+
+/*
+ * KEY/SEQ_KEY Command Constructs
+ */
+
+/* Key Destination Class: 01 = Class 1, 02 - Class 2 */
+#define KEY_DEST_CLASS_SHIFT 25 /* use CLASS_1 or CLASS_2 */
+#define KEY_DEST_CLASS_MASK (0x03 << KEY_DEST_CLASS_SHIFT)
+
+/* Scatter-Gather Table/Variable Length Field */
+#define KEY_SGF 0x01000000
+#define KEY_VLF 0x01000000
+
+/* Immediate - Key follows command in the descriptor */
+#define KEY_IMM 0x00800000
+
+/*
+ * Encrypted - Key is encrypted either with the KEK, or
+ * with the TDKEK if TK is set
+ */
+#define KEY_ENC 0x00400000
+
+/*
+ * No Write Back - Do not allow key to be FIFO STOREd
+ */
+#define KEY_NWB 0x00200000
+
+/*
+ * Enhanced Encryption of Key
+ */
+#define KEY_EKT 0x00100000
+
+/*
+ * Encrypted with Trusted Key
+ */
+#define KEY_TK 0x00008000
+
+/*
+ * KDEST - Key Destination: 0 - class key register,
+ * 1 - PKHA 'e', 2 - AFHA Sbox, 3 - MDHA split-key
+ */
+#define KEY_DEST_SHIFT 16
+#define KEY_DEST_MASK (0x03 << KEY_DEST_SHIFT)
+
+#define KEY_DEST_CLASS_REG (0x00 << KEY_DEST_SHIFT)
+#define KEY_DEST_PKHA_E (0x01 << KEY_DEST_SHIFT)
+#define KEY_DEST_AFHA_SBOX (0x02 << KEY_DEST_SHIFT)
+#define KEY_DEST_MDHA_SPLIT (0x03 << KEY_DEST_SHIFT)
+
+/* Length in bytes */
+#define KEY_LENGTH_MASK 0x000003ff
+
+/*
+ * LOAD/SEQ_LOAD/STORE/SEQ_STORE Command Constructs
+ */
+
+/*
+ * Load/Store Destination: 0 = class independent CCB,
+ * 1 = class 1 CCB, 2 = class 2 CCB, 3 = DECO
+ */
+#define LDST_CLASS_SHIFT 25
+#define LDST_CLASS_MASK (0x03 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_IND_CCB (0x00 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_1_CCB (0x01 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_2_CCB (0x02 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_DECO (0x03 << LDST_CLASS_SHIFT)
+
+/* Scatter-Gather Table/Variable Length Field */
+#define LDST_SGF 0x01000000
+#define LDST_VLF LDST_SGF
+
+/* Immediate - Key follows this command in descriptor */
+#define LDST_IMM_MASK 1
+#define LDST_IMM_SHIFT 23
+#define LDST_IMM (LDST_IMM_MASK << LDST_IMM_SHIFT)
+
+/* SRC/DST - Destination for LOAD, Source for STORE */
+#define LDST_SRCDST_SHIFT 16
+#define LDST_SRCDST_MASK (0x7f << LDST_SRCDST_SHIFT)
+
+#define LDST_SRCDST_BYTE_CONTEXT (0x20 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_BYTE_KEY (0x40 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_BYTE_INFIFO (0x7c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_BYTE_OUTFIFO (0x7e << LDST_SRCDST_SHIFT)
+
+#define LDST_SRCDST_WORD_MODE_REG (0x00 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_KEYSZ_REG (0x01 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DATASZ_REG (0x02 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_ICVSZ_REG (0x03 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CHACTRL (0x06 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECOCTRL (0x06 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_IRQCTRL (0x07 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_PCLOVRD (0x07 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLRW (0x08 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH0 (0x08 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_STAT (0x09 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH1 (0x09 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH2 (0x0a << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_AAD_SZ (0x0b << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH3 (0x0b << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS1_ICV_SZ (0x0c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_ALTDS_CLASS1 (0x0f << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_A_SZ (0x10 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_B_SZ (0x11 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_N_SZ (0x12 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_E_SZ (0x13 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS_CTX (0x20 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF (0x40 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_JOB (0x41 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_SHARED (0x42 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_JOB_WE (0x45 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_INFO_FIFO (0x7a << LDST_SRCDST_SHIFT)
+
+/* Offset in source/destination */
+#define LDST_OFFSET_SHIFT 8
+#define LDST_OFFSET_MASK (0xff << LDST_OFFSET_SHIFT)
+
+/* LDOFF definitions used when DST = LDST_SRCDST_WORD_DECOCTRL */
+/* These could also be shifted by LDST_OFFSET_SHIFT - this reads better */
+#define LDOFF_CHG_SHARE_SHIFT 0
+#define LDOFF_CHG_SHARE_MASK (0x3 << LDOFF_CHG_SHARE_SHIFT)
+#define LDOFF_CHG_SHARE_NEVER (0x1 << LDOFF_CHG_SHARE_SHIFT)
+#define LDOFF_CHG_SHARE_OK_PROP (0x2 << LDOFF_CHG_SHARE_SHIFT)
+#define LDOFF_CHG_SHARE_OK_NO_PROP (0x3 << LDOFF_CHG_SHARE_SHIFT)
+
+#define LDOFF_ENABLE_AUTO_NFIFO (1 << 2)
+#define LDOFF_DISABLE_AUTO_NFIFO (1 << 3)
+
+#define LDOFF_CHG_NONSEQLIODN_SHIFT 4
+#define LDOFF_CHG_NONSEQLIODN_MASK (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+#define LDOFF_CHG_NONSEQLIODN_SEQ (0x1 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+#define LDOFF_CHG_NONSEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+#define LDOFF_CHG_NONSEQLIODN_TRUSTED (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+
+#define LDOFF_CHG_SEQLIODN_SHIFT 6
+#define LDOFF_CHG_SEQLIODN_MASK (0x3 << LDOFF_CHG_SEQLIODN_SHIFT)
+#define LDOFF_CHG_SEQLIODN_SEQ (0x1 << LDOFF_CHG_SEQLIODN_SHIFT)
+#define LDOFF_CHG_SEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_SEQLIODN_SHIFT)
+#define LDOFF_CHG_SEQLIODN_TRUSTED (0x3 << LDOFF_CHG_SEQLIODN_SHIFT)
+
+/* Data length in bytes */
+#define LDST_LEN_SHIFT 0
+#define LDST_LEN_MASK (0xff << LDST_LEN_SHIFT)
+
+/* Special Length definitions when dst=deco-ctrl */
+#define LDLEN_ENABLE_OSL_COUNT (1 << 7)
+#define LDLEN_RST_CHA_OFIFO_PTR (1 << 6)
+#define LDLEN_RST_OFIFO (1 << 5)
+#define LDLEN_SET_OFIFO_OFF_VALID (1 << 4)
+#define LDLEN_SET_OFIFO_OFF_RSVD (1 << 3)
+#define LDLEN_SET_OFIFO_OFFSET_SHIFT 0
+#define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT)
+
+/*
+ * AAD Definitions
+ */
+#define AES_KEY_SHIFT 8
+#define LD_CCM_MODE 0x66
+#define KEY_AES_SRC (0x55 << AES_KEY_SHIFT)
+
+/*
+ * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE
+ * Command Constructs
+ */
+
+/*
+ * Load Destination: 0 = skip (SEQ_FIFO_LOAD only),
+ * 1 = Load for Class1, 2 = Load for Class2, 3 = Load both
+ * Store Source: 0 = normal, 1 = Class1key, 2 = Class2key
+ */
+#define FIFOLD_CLASS_SHIFT 25
+#define FIFOLD_CLASS_MASK (0x03 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_SKIP (0x00 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_CLASS1 (0x01 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_CLASS2 (0x02 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_BOTH (0x03 << FIFOLD_CLASS_SHIFT)
+
+#define FIFOST_CLASS_SHIFT 25
+#define FIFOST_CLASS_MASK (0x03 << FIFOST_CLASS_SHIFT)
+#define FIFOST_CLASS_NORMAL (0x00 << FIFOST_CLASS_SHIFT)
+#define FIFOST_CLASS_CLASS1KEY (0x01 << FIFOST_CLASS_SHIFT)
+#define FIFOST_CLASS_CLASS2KEY (0x02 << FIFOST_CLASS_SHIFT)
+
+/*
+ * Scatter-Gather Table/Variable Length Field
+ * If set for FIFO_LOAD, refers to a SG table. Within
+ * SEQ_FIFO_LOAD, is variable input sequence
+ */
+#define FIFOLDST_SGF_SHIFT 24
+#define FIFOLDST_SGF_MASK (1 << FIFOLDST_SGF_SHIFT)
+#define FIFOLDST_VLF_MASK (1 << FIFOLDST_SGF_SHIFT)
+#define FIFOLDST_SGF (1 << FIFOLDST_SGF_SHIFT)
+#define FIFOLDST_VLF (1 << FIFOLDST_SGF_SHIFT)
+
+/* Immediate - Data follows command in descriptor */
+#define FIFOLD_IMM_SHIFT 23
+#define FIFOLD_IMM_MASK (1 << FIFOLD_IMM_SHIFT)
+#define FIFOLD_IMM (1 << FIFOLD_IMM_SHIFT)
+
+/* Continue - Not the last FIFO store to come */
+#define FIFOST_CONT_SHIFT 23
+#define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT)
+
+/*
+ * Extended Length - use 32-bit extended length that
+ * follows the pointer field. Illegal with IMM set
+ */
+#define FIFOLDST_EXT_SHIFT 22
+#define FIFOLDST_EXT_MASK (1 << FIFOLDST_EXT_SHIFT)
+#define FIFOLDST_EXT (1 << FIFOLDST_EXT_SHIFT)
+
+/* Input data type.*/
+#define FIFOLD_TYPE_SHIFT 16
+#define FIFOLD_CONT_TYPE_SHIFT 19 /* shift past last-flush bits */
+#define FIFOLD_TYPE_MASK (0x3f << FIFOLD_TYPE_SHIFT)
+
+/* PK types */
+#define FIFOLD_TYPE_PK (0x00 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_MASK (0x30 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_TYPEMASK (0x0f << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A0 (0x00 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A1 (0x01 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A2 (0x02 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A3 (0x03 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B0 (0x04 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B1 (0x05 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B2 (0x06 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B3 (0x07 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_N (0x08 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A (0x0c << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B (0x0d << FIFOLD_TYPE_SHIFT)
+
+/* Other types. Need to OR in last/flush bits as desired */
+#define FIFOLD_TYPE_MSG_MASK (0x38 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_MSG (0x10 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_MSG1OUT2 (0x18 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_IV (0x20 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_BITDATA (0x28 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_AAD (0x30 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_ICV (0x38 << FIFOLD_TYPE_SHIFT)
+
+/* Last/Flush bits for use with "other" types above */
+#define FIFOLD_TYPE_ACT_MASK (0x07 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_NOACTION (0x00 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_FLUSH1 (0x01 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST1 (0x02 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST2FLUSH (0x03 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST2 (0x04 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LASTBOTH (0x06 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LASTBOTHFL (0x07 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_NOINFOFIFO (0x0F << FIFOLD_TYPE_SHIFT)
+
+#define FIFOLDST_LEN_MASK 0xffff
+#define FIFOLDST_EXT_LEN_MASK 0xffffffff
+
+/* Output data types */
+#define FIFOST_TYPE_SHIFT 16
+#define FIFOST_TYPE_MASK (0x3f << FIFOST_TYPE_SHIFT)
+
+#define FIFOST_TYPE_PKHA_A0 (0x00 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A1 (0x01 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A2 (0x02 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A3 (0x03 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B0 (0x04 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B1 (0x05 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B2 (0x06 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B3 (0x07 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_JKEK (0x10 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_E_TKEK (0x23 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_KEY_KEK (0x24 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_KEY_TKEK (0x25 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_SPLIT_KEK (0x26 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_SPLIT_TKEK (0x27 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_OUTFIFO_KEK (0x28 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_OUTFIFO_TKEK (0x29 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_RNGSTORE (0x34 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_RNGFIFO (0x35 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_SKIP (0x3f << FIFOST_TYPE_SHIFT)
+
+/*
+ * OPERATION Command Constructs
+ */
+
+/* Operation type selectors - OP TYPE */
+#define OP_TYPE_SHIFT 24
+#define OP_TYPE_MASK (0x07 << OP_TYPE_SHIFT)
+
+#define OP_TYPE_UNI_PROTOCOL (0x00 << OP_TYPE_SHIFT)
+#define OP_TYPE_PK (0x01 << OP_TYPE_SHIFT)
+#define OP_TYPE_CLASS1_ALG (0x02 << OP_TYPE_SHIFT)
+#define OP_TYPE_CLASS2_ALG (0x04 << OP_TYPE_SHIFT)
+#define OP_TYPE_DECAP_PROTOCOL (0x06 << OP_TYPE_SHIFT)
+#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT)
+
+/* ProtocolID selectors - PROTID */
+#define OP_PCLID_SHIFT 16
+#define OP_PCLID_MASK (0xff << 16)
+
+/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
+#define OP_PCLID_SECMEM 0x08
+#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
+#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT)
+#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT)
+
+/* For non-protocol/alg-only op commands */
+#define OP_ALG_TYPE_SHIFT 24
+#define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT)
+#define OP_ALG_TYPE_CLASS1 2
+#define OP_ALG_TYPE_CLASS2 4
+
+#define OP_ALG_ALGSEL_SHIFT 16
+#define OP_ALG_ALGSEL_MASK (0xff << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SUBMASK (0x0f << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_AES (0x10 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_DES (0x20 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_3DES (0x21 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_ARC4 (0x30 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_MD5 (0x40 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA1 (0x41 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA224 (0x42 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA256 (0x43 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA384 (0x44 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA512 (0x45 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_RNG (0x50 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SNOW (0x60 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SNOW_F8 (0x60 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_KASUMI (0x70 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_CRC (0x90 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SNOW_F9 (0xA0 << OP_ALG_ALGSEL_SHIFT)
+
+#define OP_ALG_AAI_SHIFT 4
+#define OP_ALG_AAI_MASK (0x1ff << OP_ALG_AAI_SHIFT)
+
+/* randomizer AAI set */
+#define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG_NZB (0x10 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG_OBP (0x20 << OP_ALG_AAI_SHIFT)
+
+/* RNG4 AAI set */
+#define OP_ALG_AAI_RNG4_SH_0 (0x00 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_SH_1 (0x01 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_PS (0x40 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_AI (0x80 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_SK (0x100 << OP_ALG_AAI_SHIFT)
+
+/* hmac/smac AAI set */
+#define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_HMAC (0x01 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_SMAC (0x02 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_HMAC_PRECOMP (0x04 << OP_ALG_AAI_SHIFT)
+
+#define OP_ALG_AS_SHIFT 2
+#define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_INIT (1 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_FINALIZE (2 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_INITFINAL (3 << OP_ALG_AS_SHIFT)
+
+#define OP_ALG_ICV_SHIFT 1
+#define OP_ALG_ICV_MASK (1 << OP_ALG_ICV_SHIFT)
+#define OP_ALG_ICV_OFF (0 << OP_ALG_ICV_SHIFT)
+#define OP_ALG_ICV_ON (1 << OP_ALG_ICV_SHIFT)
+
+#define OP_ALG_DIR_SHIFT 0
+#define OP_ALG_DIR_MASK 1
+#define OP_ALG_DECRYPT 0
+#define OP_ALG_ENCRYPT 1
+
+/* PKHA algorithm type set */
+#define OP_ALG_PK 0x00800000
+#define OP_ALG_PK_FUN_MASK 0x3f /* clrmem, modmath, or cpymem */
+
+/* PKHA mode modular-arithmetic functions */
+#define OP_ALG_PKMODE_MOD_EXPO 0x006
+
+/*
+ * SEQ_IN_PTR Command Constructs
+ */
+
+/* Release Buffers */
+#define SQIN_RBS 0x04000000
+
+/* Sequence pointer is really a descriptor */
+#define SQIN_INL 0x02000000
+
+/* Sequence pointer is a scatter-gather table */
+#define SQIN_SGF 0x01000000
+
+/* Appends to a previous pointer */
+#define SQIN_PRE 0x00800000
+
+/* Use extended length following pointer */
+#define SQIN_EXT 0x00400000
+
+/* Restore sequence with pointer/length */
+#define SQIN_RTO 0x00200000
+
+/* Replace job descriptor */
+#define SQIN_RJD 0x00100000
+
+#define SQIN_LEN_SHIFT 0
+#define SQIN_LEN_MASK (0xffff << SQIN_LEN_SHIFT)
+
+/*
+ * SEQ_OUT_PTR Command Constructs
+ */
+
+/* Sequence pointer is a scatter-gather table */
+#define SQOUT_SGF 0x01000000
+
+/* Appends to a previous pointer */
+#define SQOUT_PRE SQIN_PRE
+
+/* Restore sequence with pointer/length */
+#define SQOUT_RTO SQIN_RTO
+
+/* Use extended length following pointer */
+#define SQOUT_EXT 0x00400000
+
+#define SQOUT_LEN_SHIFT 0
+#define SQOUT_LEN_MASK (0xffff << SQOUT_LEN_SHIFT)
+
+/*
+ * MOVE Command Constructs
+ */
+
+#define MOVE_AUX_SHIFT 25
+#define MOVE_AUX_MASK (3 << MOVE_AUX_SHIFT)
+#define MOVE_AUX_MS (2 << MOVE_AUX_SHIFT)
+#define MOVE_AUX_LS (1 << MOVE_AUX_SHIFT)
+
+#define MOVE_WAITCOMP_SHIFT 24
+#define MOVE_WAITCOMP_MASK (1 << MOVE_WAITCOMP_SHIFT)
+#define MOVE_WAITCOMP (1 << MOVE_WAITCOMP_SHIFT)
+
+#define MOVE_SRC_SHIFT 20
+#define MOVE_SRC_MASK (0x0f << MOVE_SRC_SHIFT)
+#define MOVE_SRC_CLASS1CTX (0x00 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_CLASS2CTX (0x01 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_OUTFIFO (0x02 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_DESCBUF (0x03 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH0 (0x04 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH1 (0x05 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH2 (0x06 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH3 (0x07 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_INFIFO (0x08 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_INFIFO_CL (0x09 << MOVE_SRC_SHIFT)
+
+#define MOVE_DEST_SHIFT 16
+#define MOVE_DEST_MASK (0x0f << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS1CTX (0x00 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS2CTX (0x01 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_OUTFIFO (0x02 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_DESCBUF (0x03 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH0 (0x04 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH1 (0x05 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH2 (0x06 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH3 (0x07 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS1INFIFO (0x08 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS2INFIFO (0x09 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_INFIFO_NOINFO (0x0a << MOVE_DEST_SHIFT)
+#define MOVE_DEST_PK_A (0x0c << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS1KEY (0x0d << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS2KEY (0x0e << MOVE_DEST_SHIFT)
+
+#define MOVE_OFFSET_SHIFT 8
+#define MOVE_OFFSET_MASK (0xff << MOVE_OFFSET_SHIFT)
+
+#define MOVE_LEN_SHIFT 0
+#define MOVE_LEN_MASK (0xff << MOVE_LEN_SHIFT)
+
+#define MOVELEN_MRSEL_SHIFT 0
+#define MOVELEN_MRSEL_MASK (0x3 << MOVE_LEN_SHIFT)
+
+/*
+ * JUMP Command Constructs
+ */
+
+#define JUMP_CLASS_SHIFT 25
+#define JUMP_CLASS_MASK (3 << JUMP_CLASS_SHIFT)
+#define JUMP_CLASS_NONE 0
+#define JUMP_CLASS_CLASS1 (1 << JUMP_CLASS_SHIFT)
+#define JUMP_CLASS_CLASS2 (2 << JUMP_CLASS_SHIFT)
+#define JUMP_CLASS_BOTH (3 << JUMP_CLASS_SHIFT)
+
+#define JUMP_JSL_SHIFT 24
+#define JUMP_JSL_MASK (1 << JUMP_JSL_SHIFT)
+#define JUMP_JSL (1 << JUMP_JSL_SHIFT)
+
+#define JUMP_TYPE_SHIFT 22
+#define JUMP_TYPE_MASK (0x03 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_LOCAL (0x00 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_NONLOCAL (0x01 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_HALT (0x02 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_HALT_USER (0x03 << JUMP_TYPE_SHIFT)
+
+#define JUMP_TEST_SHIFT 16
+#define JUMP_TEST_MASK (0x03 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_ALL (0x00 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_INVALL (0x01 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_ANY (0x02 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_INVANY (0x03 << JUMP_TEST_SHIFT)
+
+/* Condition codes. JSL bit is factored in */
+#define JUMP_COND_SHIFT 8
+#define JUMP_COND_MASK (0x100ff << JUMP_COND_SHIFT)
+#define JUMP_COND_PK_0 (0x80 << JUMP_COND_SHIFT)
+#define JUMP_COND_PK_GCD_1 (0x40 << JUMP_COND_SHIFT)
+#define JUMP_COND_PK_PRIME (0x20 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_N (0x08 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_Z (0x04 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_C (0x02 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_NV (0x01 << JUMP_COND_SHIFT)
+
+#define JUMP_COND_JRP ((0x80 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_SHRD ((0x40 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_SELF ((0x20 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_CALM ((0x10 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NIP ((0x08 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NIFP ((0x04 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NOP ((0x02 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NCP ((0x01 << JUMP_COND_SHIFT) | JUMP_JSL)
+
+#define JUMP_OFFSET_SHIFT 0
+#define JUMP_OFFSET_MASK (0xff << JUMP_OFFSET_SHIFT)
+
+#define OP_ALG_RNG4_SHIFT 4
+#define OP_ALG_RNG4_MAS (0x1f3 << OP_ALG_RNG4_SHIFT)
+#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT)
+
+#endif /* DESC_H */
diff --git a/core/drivers/crypto/desc_constr.h b/core/drivers/crypto/desc_constr.h
new file mode 100644
index 0000000..96d089a
--- /dev/null
+++ b/core/drivers/crypto/desc_constr.h
@@ -0,0 +1,284 @@
+/*
+ * caam descriptor construction helper functions
+ *
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on desc_constr.h file in linux drivers/crypto/caam
+ */
+
+#include <string.h>
+#include "desc.h"
+
+typedef uint32_t dma_addr_t;
+
+#define IMMEDIATE (1 << 23)
+#define CAAM_CMD_SZ sizeof(uint32_t)
+#define CAAM_PTR_SZ sizeof(dma_addr_t)
+#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
+#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
+
+#ifdef DEBUG
+#define PRINT_POS do { printf("%02d: %s\n", desc_len(desc),\
+ &__func__[sizeof("append")]); \
+ } while (0)
+#else
+#define PRINT_POS
+#endif
+
+#define SET_OK_NO_PROP_ERRORS (IMMEDIATE | LDST_CLASS_DECO | \
+ LDST_SRCDST_WORD_DECOCTRL | \
+ (LDOFF_CHG_SHARE_OK_NO_PROP << \
+ LDST_OFFSET_SHIFT))
+#define DISABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \
+ LDST_SRCDST_WORD_DECOCTRL | \
+ (LDOFF_DISABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#define ENABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \
+ LDST_SRCDST_WORD_DECOCTRL | \
+ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+
+static inline int desc_len(uint32_t *desc)
+{
+ return *desc & HDR_DESCLEN_MASK;
+}
+
+static inline int desc_bytes(void *desc)
+{
+ return desc_len(desc) * CAAM_CMD_SZ;
+}
+
+static inline uint32_t *desc_end(uint32_t *desc)
+{
+ return desc + desc_len(desc);
+}
+
+static inline void init_desc(uint32_t *desc, uint32_t options)
+{
+ *desc = (options | HDR_ONE) + 1;
+}
+
+static inline void init_job_desc(uint32_t *desc, uint32_t options)
+{
+ init_desc(desc, CMD_DESC_HDR | options);
+}
+
+static inline void append_ptr(uint32_t *desc, dma_addr_t ptr)
+{
+ dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+
+ *offset = ptr;
+
+ (*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
+}
+
+static inline void append_data(uint32_t *desc, void *data, int len)
+{
+ uint32_t *offset = desc_end(desc);
+
+ if (len) /* avoid sparse warning: memcpy with byte count of 0 */
+ memcpy(offset, data, len);
+
+ (*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+}
+
+static inline void append_cmd(uint32_t *desc, uint32_t command)
+{
+ uint32_t *cmd = desc_end(desc);
+
+ *cmd = command;
+
+ (*desc)++;
+}
+
+#define append_u32 append_cmd
+
+/*
+static inline void append_u64(uint32_t *desc, uint64_t data)
+{
+ uint32_t *offset = desc_end(desc);
+
+ *offset = upper_32_bits(data);
+ *(++offset) = lower_32_bits(data);
+
+ (*desc) += 2;
+}
+*/
+
+/* Write command without affecting header, and return pointer to next word */
+static inline uint32_t *write_cmd(uint32_t *desc, uint32_t command)
+{
+ *desc = command;
+
+ return desc + 1;
+}
+
+static inline void append_cmd_ptr(uint32_t *desc, dma_addr_t ptr, int len,
+ uint32_t command)
+{
+ append_cmd(desc, command | len);
+ append_ptr(desc, ptr);
+}
+
+/* Write length after pointer, rather than inside command */
+static inline void append_cmd_ptr_extlen(uint32_t *desc, dma_addr_t ptr,
+ unsigned int len, uint32_t command)
+{
+ append_cmd(desc, command);
+ if (!(command & (SQIN_RTO | SQIN_PRE)))
+ append_ptr(desc, ptr);
+ append_cmd(desc, len);
+}
+
+static inline void append_cmd_data(uint32_t *desc, void *data, int len,
+ uint32_t command)
+{
+ append_cmd(desc, command | IMMEDIATE | len);
+ append_data(desc, data, len);
+}
+
+#define APPEND_CMD_RET(cmd, op) \
+static inline uint32_t *append_##cmd(uint32_t *desc, uint32_t options) \
+{ \
+ uint32_t *cmd = desc_end(desc); \
+ PRINT_POS; \
+ append_cmd(desc, CMD_##op | options); \
+ return cmd; \
+}
+APPEND_CMD_RET(jump, JUMP)
+APPEND_CMD_RET(move, MOVE)
+
+static inline void set_jump_tgt_here(uint32_t *desc, uint32_t *jump_cmd)
+{
+ *jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc));
+}
+
+static inline void set_move_tgt_here(uint32_t *desc, uint32_t *move_cmd)
+{
+ *move_cmd &= ~MOVE_OFFSET_MASK;
+ *move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) &
+ MOVE_OFFSET_MASK);
+}
+
+#define APPEND_CMD(cmd, op) \
+static inline void append_##cmd(uint32_t *desc, uint32_t options) \
+{ \
+ PRINT_POS; \
+ append_cmd(desc, CMD_##op | options); \
+}
+APPEND_CMD(operation, OPERATION)
+
+#define APPEND_CMD_LEN(cmd, op) \
+static inline void append_##cmd(uint32_t *desc, unsigned int len, uint32_t options) \
+{ \
+ PRINT_POS; \
+ append_cmd(desc, CMD_##op | len | options); \
+}
+APPEND_CMD_LEN(seq_store, SEQ_STORE)
+APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
+APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
+
+#define APPEND_CMD_PTR(cmd, op) \
+static inline void append_##cmd(uint32_t *desc, dma_addr_t ptr, unsigned int len, \
+ uint32_t options) \
+{ \
+ PRINT_POS; \
+ append_cmd_ptr(desc, ptr, len, CMD_##op | options); \
+}
+APPEND_CMD_PTR(key, KEY)
+APPEND_CMD_PTR(load, LOAD)
+APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
+APPEND_CMD_PTR(fifo_store, FIFO_STORE)
+
+static inline void append_store(uint32_t *desc, dma_addr_t ptr, unsigned int len,
+ uint32_t options)
+{
+ uint32_t cmd_src;
+
+ cmd_src = options & LDST_SRCDST_MASK;
+
+ append_cmd(desc, CMD_STORE | options | len);
+
+ /* The following options do not require pointer */
+ if (!(cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED ||
+ cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB ||
+ cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB_WE ||
+ cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED_WE))
+ append_ptr(desc, ptr);
+}
+
+#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
+static inline void append_seq_##cmd##_ptr_intlen(uint32_t *desc, dma_addr_t ptr, \
+ unsigned int len, \
+ uint32_t options) \
+{ \
+ PRINT_POS; \
+ if (options & (SQIN_RTO | SQIN_PRE)) \
+ append_cmd(desc, CMD_SEQ_##op##_PTR | len | options); \
+ else \
+ append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \
+}
+APPEND_SEQ_PTR_INTLEN(in, IN)
+APPEND_SEQ_PTR_INTLEN(out, OUT)
+
+#define APPEND_CMD_PTR_TO_IMM(cmd, op) \
+static inline void append_##cmd##_as_imm(uint32_t *desc, void *data, \
+ unsigned int len, uint32_t options) \
+{ \
+ PRINT_POS; \
+ append_cmd_data(desc, data, len, CMD_##op | options); \
+}
+APPEND_CMD_PTR_TO_IMM(load, LOAD)
+APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD)
+
+#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
+static inline void append_##cmd##_extlen(uint32_t *desc, dma_addr_t ptr, \
+ unsigned int len, uint32_t options) \
+{ \
+ PRINT_POS; \
+ append_cmd_ptr_extlen(desc, ptr, len, CMD_##op | SQIN_EXT | options); \
+}
+APPEND_CMD_PTR_EXTLEN(seq_in_ptr, SEQ_IN_PTR)
+APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
+
+/*
+ * Determine whether to store length internally or externally depending on
+ * the size of its type
+ */
+#define APPEND_CMD_PTR_LEN(cmd, op, type) \
+static inline void append_##cmd(uint32_t *desc, dma_addr_t ptr, \
+ type len, uint32_t options) \
+{ \
+ PRINT_POS; \
+ if (sizeof(type) > sizeof(uint16_t)) \
+ append_##cmd##_extlen(desc, ptr, len, options); \
+ else \
+ append_##cmd##_intlen(desc, ptr, len, options); \
+}
+APPEND_CMD_PTR_LEN(seq_in_ptr, SEQ_IN_PTR, uint32_t)
+APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, uint32_t)
+
+/*
+ * 2nd variant for commands whose specified immediate length differs
+ * from length of immediate data provided, e.g., split keys
+ */
+#define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
+static inline void append_##cmd##_as_imm(uint32_t *desc, void *data, \
+ unsigned int data_len, \
+ unsigned int len, uint32_t options) \
+{ \
+ PRINT_POS; \
+ append_cmd(desc, CMD_##op | IMMEDIATE | len | options); \
+ append_data(desc, data, data_len); \
+}
+APPEND_CMD_PTR_TO_IMM2(key, KEY)
+
+#define APPEND_CMD_RAW_IMM(cmd, op, type) \
+static inline void append_##cmd##_imm_##type(uint32_t *desc, type immediate, \
+ uint32_t options) \
+{ \
+ PRINT_POS; \
+ append_cmd(desc, CMD_##op | IMMEDIATE | options | sizeof(type)); \
+ append_cmd(desc, immediate); \
+}
+APPEND_CMD_RAW_IMM(load, LOAD, uint32_t)
diff --git a/core/drivers/crypto/error.c b/core/drivers/crypto/error.c
new file mode 100644
index 0000000..418304b
--- /dev/null
+++ b/core/drivers/crypto/error.c
@@ -0,0 +1,261 @@
+/*
+ * CAAM Error Reporting
+ *
+ * Copyright 2009-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Derived from error.c file in linux drivers/crypto/caam
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <trace.h>
+#include "desc.h"
+#include "jr.h"
+#include "misc.h"
+
+#define CAAM_ERROR_STR_MAX 302
+
+#define JRSTA_SSRC_SHIFT 28
+#define JRSTA_CCBERR_CHAID_MASK 0x00f0
+#define JRSTA_CCBERR_CHAID_SHIFT 4
+#define JRSTA_CCBERR_ERRID_MASK 0x000
+#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
+
+#define JRSTA_DECOERR_JUMP 0x08000000
+#define JRSTA_DECOERR_INDEX_SHIFT 8
+#define JRSTA_DECOERR_INDEX_MASK 0xff00
+#define JRSTA_DECOERR_ERROR_MASK 0x00ff
+
+
+static const struct {
+ uint8_t value;
+ const char *error_text;
+} desc_error_list[] = {
+ { 0x00, "No error." },
+ { 0x01, "SGT Length Error. The descriptor is trying to read" \
+ " more data than is contained in the SGT table." },
+ { 0x02, "SGT Null Entry Error." },
+ { 0x03, "Job Ring Control Error. Bad value in Job Ring Control reg." },
+ { 0x04, "Invalid Descriptor Command." },
+ { 0x05, "Reserved." },
+ { 0x06, "Invalid KEY Command" },
+ { 0x07, "Invalid LOAD Command" },
+ { 0x08, "Invalid STORE Command" },
+ { 0x09, "Invalid OPERATION Command" },
+ { 0x0A, "Invalid FIFO LOAD Command" },
+ { 0x0B, "Invalid FIFO STORE Command" },
+ { 0x0C, "Invalid MOVE/MOVE_LEN Command" },
+ { 0x0D, "Invalid JUMP Command" },
+ { 0x0E, "Invalid MATH Command" },
+ { 0x0F, "Invalid SIGNATURE Command" },
+ { 0x10, "Invalid Sequence Command" },
+ { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."},
+ { 0x12, "Shared Descriptor Header Error" },
+ { 0x13, "Header Error. Invalid length or parity, or other problems." },
+ { 0x14, "Burster Error. Burster has gotten to an illegal state" },
+ { 0x15, "Context Register Length Error" },
+ { 0x16, "DMA Error" },
+ { 0x17, "Reserved." },
+ { 0x1A, "Job failed due to JR reset" },
+ { 0x1B, "Job failed due to Fail Mode" },
+ { 0x1C, "DECO Watchdog timer timeout error" },
+ { 0x1D, "DECO tried to copy a key from another DECO but" \
+ " the other DECO's Key Registers were locked" },
+ { 0x1E, "DECO attempted to copy data from a DECO" \
+ "that had an unmasked Descriptor error" },
+ { 0x1F, "LIODN error" },
+ { 0x20, "DECO has completed a reset initiated via the DRR register" },
+ { 0x21, "Nonce error" },
+ { 0x22, "Meta data is too large (> 511 bytes) for TLS decap" },
+ { 0x23, "Read Input Frame error" },
+ { 0x24, "JDKEK, TDKEK or TDSK not loaded error" },
+ { 0x80, "DNR (do not run) error" },
+ { 0x81, "undefined protocol command" },
+ { 0x82, "invalid setting in PDB" },
+ { 0x83, "Anti-replay LATE error" },
+ { 0x84, "Anti-replay REPLAY error" },
+ { 0x85, "Sequence number overflow" },
+ { 0x86, "Sigver invalid signature" },
+ { 0x87, "DSA Sign Illegal test descriptor" },
+ { 0x88, "Protocol Format Error" },
+ { 0x89, "Protocol Size Error" },
+ { 0xC1, "Blob Command error: Undefined mode" },
+ { 0xC2, "Blob Command error: Secure Memory Blob mode error" },
+ { 0xC4, "Blob Command error: Black Blob key or input size error" },
+ { 0xC5, "Blob Command error: Invalid key destination" },
+ { 0xC8, "Blob Command error: Trusted/Secure mode error" },
+ { 0xF0, "IPsec TTL or hop limit field is 0, or was decremented to 0" },
+ { 0xF1, "3GPP HFN matches or exceeds the Threshold" },
+};
+
+static const char * const cha_id_list[] = {
+ "",
+ "AES",
+ "DES",
+ "ARC4",
+ "MDHA",
+ "RNG",
+ "SNOW f8",
+ "Kasumi f8/9",
+ "PKHA",
+ "CRCA",
+ "SNOW f9",
+ "ZUCE",
+ "ZUCA",
+};
+
+static const char * const err_id_list[] = {
+ "No error.",
+ "Mode error.",
+ "Data size error.",
+ "Key size error.",
+ "PKHA A memory size error.",
+ "PKHA B memory size error.",
+ "Data arrived out of sequence error.",
+ "PKHA divide-by-zero error.",
+ "PKHA modulus even error.",
+ "DES key parity error.",
+ "ICV check failed.",
+ "Hardware error.",
+ "Unsupported CCM AAD size.",
+ "Class 1 CHA is not reset",
+ "Invalid CHA combination was selected",
+ "Invalid CHA selected.",
+};
+
+static const char * const rng_err_id_list[] = {
+ "",
+ "",
+ "",
+ "Instantiate",
+ "Not instantiated",
+ "Test instantiate",
+ "Prediction resistance",
+ "Prediction resistance and test request",
+ "Uninstantiate",
+ "Secure key generation",
+};
+
+static void report_ccb_status(const uint32_t status,
+ const char *error)
+{
+ uint8_t cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >>
+ JRSTA_CCBERR_CHAID_SHIFT;
+ uint8_t err_id = status & JRSTA_CCBERR_ERRID_MASK;
+ uint8_t idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
+ JRSTA_DECOERR_INDEX_SHIFT;
+ const char *idx_str;
+ const char *cha_str = "unidentified cha_id value 0x";
+ char cha_err_code[3] = { 0 };
+ const char *err_str = "unidentified err_id value 0x";
+ char err_err_code[3] = { 0 };
+
+ if (status & JRSTA_DECOERR_JUMP)
+ idx_str = "jump tgt desc idx";
+ else
+ idx_str = "desc idx";
+
+ if (cha_id < ARRAY_SIZE(cha_id_list))
+ cha_str = cha_id_list[cha_id];
+ else
+ snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id);
+
+ if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG &&
+ err_id < ARRAY_SIZE(rng_err_id_list) &&
+ strlen(rng_err_id_list[err_id])) {
+ /* RNG-only error */
+ err_str = rng_err_id_list[err_id];
+ } else if (err_id < ARRAY_SIZE(err_id_list)) {
+ err_str = err_id_list[err_id];
+ } else {
+ snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+ }
+
+ DMSG("%08x: %s: %s %d: %s%s: %s%s\n",
+ status, error, idx_str, idx,
+ cha_str, cha_err_code,
+ err_str, err_err_code);
+}
+
+static void report_jump_status(const uint32_t status,
+ const char *error)
+{
+ DMSG("%08x: %s: %s() not implemented\n",
+ status, error, __func__);
+}
+
+static void report_deco_status(const uint32_t status,
+ const char *error)
+{
+ uint8_t err_id = status & JRSTA_DECOERR_ERROR_MASK;
+ uint8_t idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
+ JRSTA_DECOERR_INDEX_SHIFT;
+ const char *idx_str;
+ const char *err_str = "unidentified error value 0x";
+ char err_err_code[3] = { 0 };
+ unsigned int i;
+
+ if (status & JRSTA_DECOERR_JUMP)
+ idx_str = "jump tgt desc idx";
+ else
+ idx_str = "desc idx";
+
+ for (i = 0; i < ARRAY_SIZE(desc_error_list); i++)
+ if (desc_error_list[i].value == err_id)
+ break;
+
+ if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text)
+ err_str = desc_error_list[i].error_text;
+ else
+ snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+
+ DMSG("%08x: %s: %s %d: %s%s\n",
+ status, error, idx_str, idx, err_str, err_err_code);
+}
+
+static void report_jr_status(const uint32_t status,
+ const char *error)
+{
+ DMSG("%08x: %s: %s() not implemented\n",
+ status, error, __func__);
+}
+
+static void report_cond_code_status(const uint32_t status,
+ const char *error)
+{
+ DMSG("%08x: %s: %s() not implemented\n",
+ status, error, __func__);
+}
+
+void caam_jr_strstatus(uint32_t status)
+{
+ static const struct stat_src {
+ void (*report_ssed)(const uint32_t status,
+ const char *error);
+ const char *error;
+ } status_src[] = {
+ { NULL, "No error" },
+ { NULL, NULL },
+ { report_ccb_status, "CCB" },
+ { report_jump_status, "Jump" },
+ { report_deco_status, "DECO" },
+ { NULL, NULL },
+ { report_jr_status, "Job Ring" },
+ { report_cond_code_status, "Condition Code" },
+ };
+ uint32_t ssrc = status >> JRSTA_SSRC_SHIFT;
+ const char *error = status_src[ssrc].error;
+
+ /*
+ * If there is no further error handling function, just
+ * print the error code, error string and exit. Otherwise
+ * call the handler function.
+ */
+ if (!status_src[ssrc].report_ssed)
+ DMSG("%08x: %s:\n", status, status_src[ssrc].error);
+ else
+ status_src[ssrc].report_ssed(status, error);
+}
diff --git a/core/drivers/crypto/fsl_blob.c b/core/drivers/crypto/fsl_blob.c
new file mode 100644
index 0000000..9da00e6
--- /dev/null
+++ b/core/drivers/crypto/fsl_blob.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <fsl_sec.h>
+#include <mm/core_memprot.h>
+#include <stdlib.h>
+#include <trace.h>
+#include "desc.h"
+#include "jobdesc.h"
+#include "jr.h"
+#include "misc.h"
+
+int blob_decap(uint8_t *key_mod, uint8_t *src, uint8_t *dst, uint32_t len)
+{
+ int ret, i = 0;
+ uint32_t *desc;
+
+ IMSG("\nDecapsulating data to form blob\n");
+ desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+ if (!desc) {
+ DMSG("Not enough memory for descriptor allocation\n");
+ return -1;
+ }
+
+ inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
+
+ for (i = 0; i < 14; i++)
+ IMSG("%x\n", *(desc + i));
+ ret = run_descriptor_jr(desc);
+
+ if (ret)
+ EMSG("Error in Decapsulation %d\n", ret);
+
+ free(desc);
+ return ret;
+}
+
+int blob_encap(uint8_t *key_mod, uint8_t *src, uint8_t *dst, uint32_t len)
+{
+ int ret, i = 0;
+ uint32_t *desc;
+
+ IMSG("\nEncapsulating data to form blob\n");
+ desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+ if (!desc) {
+ DMSG("Not enough memory for descriptor allocation\n");
+ return -1;
+ }
+
+ inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
+ for (i = 0; i < 14; i++)
+ IMSG("%x\n", *(desc + i));
+ ret = run_descriptor_jr(desc);
+
+ if (ret)
+ EMSG("Error in Encapsulation %d\n", ret);
+
+ free(desc);
+ return ret;
+}
+
+int blob_dek(const uint8_t *src, uint8_t *dst, uint8_t len)
+{
+ int ret, size, i = 0;
+ uint32_t *desc;
+
+ int out_sz = WRP_HDR_SIZE + len + KEY_BLOB_SIZE + MAC_SIZE;
+
+ IMSG("\nEncapsulating provided DEK to form blob\n");
+ desc = memalign(ARCH_DMA_MINALIGN,
+ sizeof(uint32_t) * DEK_BLOB_DESCSIZE);
+ if (!desc) {
+ DMSG("Not enough memory for descriptor allocation\n");
+ return -1;
+ }
+
+ ret = inline_cnstr_jobdesc_blob_dek(desc, src, dst, len);
+ if (ret) {
+ EMSG("Error in Job Descriptor Construction: %d\n", ret);
+ } else {
+ size = roundup(sizeof(uint32_t) * DEK_BLOB_DESCSIZE,
+ ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, desc, (size_t)size);
+ size = roundup(sizeof(uint8_t) * out_sz, ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, dst, (size_t)size);
+
+ ret = run_descriptor_jr(desc);
+ }
+
+ if (ret) {
+ DMSG("Error in Encapsulation %d\n", ret);
+ goto err;
+ }
+
+ size = roundup(out_sz, ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_INVALIDATE, dst, (size_t)size);
+
+ IMSG("DEK Blob\n");
+ for (i = 0; i < out_sz; i++)
+ IMSG("%02X", ((uint8_t *)dst)[i]);
+ IMSG("\n");
+
+err:
+ free(desc);
+ return ret;
+}
diff --git a/core/drivers/crypto/jobdesc.c b/core/drivers/crypto/jobdesc.c
new file mode 100644
index 0000000..e16c4c5
--- /dev/null
+++ b/core/drivers/crypto/jobdesc.c
@@ -0,0 +1,274 @@
+/*
+ * SEC Descriptor Construction Library
+ * Basic job descriptor construction
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <fsl_sec.h>
+#include <mm/core_memprot.h>
+#include <trace.h>
+#include "desc_constr.h"
+#include "jobdesc.h"
+#include "misc.h"
+
+#ifdef CFG_MX6
+/*!
+ * Secure memory run command
+ *
+ * @param sec_mem_cmd Secure memory command register
+ * @return cmd_status Secure memory command status register
+ */
+static uint32_t secmem_set_cmd(uint32_t sec_mem_cmd)
+{
+ uint32_t temp_reg;
+
+ write32(sec_mem_cmd, (vaddr_t)CAAM_SMCJR0);
+
+ do {
+ temp_reg = read32((vaddr_t)CAAM_SMCSJR0);
+ } while (temp_reg & CMD_COMPLETE);
+
+ return temp_reg;
+}
+
+/*!
+ * CAAM page allocation:
+ * Allocates a partition from secure memory, with the id
+ * equal to partion_num. This will de-allocate the page
+ * if it is already allocated. The partition will have
+ * full access permissions. The permissions are set before,
+ * running a job descriptor. A memory page of secure RAM
+ * is allocated for the partition.
+ *
+ * @param page Number of the page to allocate.
+ * @param partition Number of the partition to allocate.
+ * @return 0 on success, ERROR_IN_PAGE_ALLOC otherwise
+ */
+static int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
+{
+ uint32_t temp_reg;
+
+ /*
+ * De-Allocate partition_num if already allocated to ARM core
+ */
+ if (read32((vaddr_t)CAAM_SMPO_0) & PARTITION_OWNER(partition_num)) {
+ temp_reg = secmem_set_cmd(PARTITION(partition_num) |
+ CMD_PART_DEALLOC);
+ if (temp_reg & SMCSJR_AERR) {
+ EMSG("Error: De-allocation status 0x%X\n", temp_reg);
+ return ERROR_IN_PAGE_ALLOC;
+ }
+ }
+
+ /* set the access rights to allow full access */
+ write32(0xF, (vaddr_t)CAAM_SMAG1JR0(partition_num));
+ write32(0xF, (vaddr_t)CAAM_SMAG2JR0(partition_num));
+ write32(0xFF, (vaddr_t)CAAM_SMAPJR0(partition_num));
+
+ /* Now need to allocate partition_num of secure RAM. */
+ /* De-Allocate page_num by starting with a page inquiry command */
+ temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY);
+
+ /* if the page is owned, de-allocate it */
+ if ((temp_reg & SMCSJR_PO) == PAGE_OWNED) {
+ temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_PAGE_DEALLOC);
+ if (temp_reg & SMCSJR_AERR) {
+ EMSG("Error: Allocation status 0x%X\n", temp_reg);
+ return ERROR_IN_PAGE_ALLOC;
+ }
+ }
+
+ /* Allocate page_num to partition_num */
+ temp_reg = secmem_set_cmd(PAGE(page_num) | PARTITION(partition_num)
+ | CMD_PAGE_ALLOC);
+ if (temp_reg & SMCSJR_AERR) {
+ EMSG("Error: Allocation status 0x%X\n", temp_reg);
+ return ERROR_IN_PAGE_ALLOC;
+ }
+ /* page inquiry command to ensure that the page was allocated */
+ temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY);
+
+ /* if the page is not owned => problem */
+ if ((temp_reg & SMCSJR_PO) != PAGE_OWNED) {
+ EMSG("Allocation of page %d in partition %d failed 0x%X\n",
+ temp_reg, page_num, partition_num);
+
+ return ERROR_IN_PAGE_ALLOC;
+ }
+
+ return 0;
+}
+
+int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
+ uint8_t *dek_blob, uint32_t in_sz)
+{
+ unsigned long start, end;
+ uint32_t ret = 0;
+ uint32_t aad_w1, aad_w2;
+ /* output blob will have 32 bytes key blob in beginning and
+ * 16 byte HMAC identifier at end of data blob */
+ uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE;
+ /* Setting HDR for blob */
+ uint8_t wrapped_key_hdr[8] = {HDR_TAG, 0x00, WRP_HDR_SIZE + out_sz,
+ HDR_PAR, HAB_MOD, HAB_ALG, in_sz, HAB_FLG};
+
+ /* initialize the blob array */
+ memset(dek_blob, 0, out_sz + 8);
+ /* Copy the header into the DEK blob buffer */
+ memcpy(dek_blob, wrapped_key_hdr, sizeof(wrapped_key_hdr));
+
+ /* allocating secure memory */
+ ret = caam_page_alloc(PAGE_1, PARTITION_1);
+ if (ret)
+ return ret;
+
+ /* Write DEK to secure memory */
+ memcpy((void*)SEC_MEM_PAGE1, plain_txt, in_sz);
+
+ start = (unsigned long)SEC_MEM_PAGE1 &
+ ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN(start + 0x1000, ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start,
+ (size_t)(end - start));
+
+ /* Now configure the access rights of the partition */
+ write32(KS_G1, (vaddr_t)CAAM_SMAG1JR0(PARTITION_1)); /* set group 1 */
+ write32(0, (vaddr_t)CAAM_SMAG2JR0(PARTITION_1)); /* clear group 2 */
+ write32(PERM, (vaddr_t)CAAM_SMAPJR0(PARTITION_1)); /* set perm & locks */
+
+ /* construct aad for AES */
+ aad_w1 = (in_sz << OP_ALG_ALGSEL_SHIFT) | KEY_AES_SRC | LD_CCM_MODE;
+ aad_w2 = 0x0;
+
+ init_job_desc(desc, 0);
+
+ append_cmd(desc, CMD_LOAD | CLASS_2 | KEY_IMM | KEY_ENC |
+ (0x0c << LDST_OFFSET_SHIFT) | 0x08);
+
+ append_u32(desc, aad_w1);
+
+ append_u32(desc, aad_w2);
+
+ append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
+
+ append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR);
+
+ append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
+ OP_PCLID_SECMEM);
+
+ return ret;
+}
+#endif
+
+void inline_cnstr_jobdesc_hash(uint32_t *desc,
+ const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
+ uint32_t alg_type, uint32_t alg_size, int sg_tbl)
+{
+ /* SHA 256 , output is of length 32 words */
+ uint32_t storelen = alg_size;
+ uint32_t options;
+ dma_addr_t dma_addr_in, dma_addr_out;
+
+ dma_addr_in = virt_to_phys((void *)msg);
+ dma_addr_out = virt_to_phys((void *)digest);
+
+ init_job_desc(desc, 0);
+ append_operation(desc, OP_TYPE_CLASS2_ALG |
+ OP_ALG_AAI_HASH | OP_ALG_AS_INITFINAL |
+ OP_ALG_ENCRYPT | OP_ALG_ICV_OFF | alg_type);
+
+ options = LDST_CLASS_2_CCB | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2;
+ if (sg_tbl)
+ options |= FIFOLDST_SGF;
+ if (msgsz > 0xffff) {
+ options |= FIFOLDST_EXT;
+ append_fifo_load(desc, dma_addr_in, 0, options);
+ append_cmd(desc, msgsz);
+ } else {
+ append_fifo_load(desc, dma_addr_in, msgsz, options);
+ }
+
+ append_store(desc, dma_addr_out, storelen,
+ LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT);
+}
+
+void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
+ uint8_t *plain_txt, uint8_t *enc_blob,
+ uint32_t in_sz)
+{
+ dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
+ uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
+ /* output blob will have 32 bytes key blob in beginning and
+ * 16 byte HMAC identifier at end of data blob */
+ uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE;
+
+ dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr);
+ dma_addr_in = virt_to_phys((void *)plain_txt);
+ dma_addr_out = virt_to_phys((void *)enc_blob);
+
+ init_job_desc(desc, 0);
+
+ append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2);
+
+ append_seq_in_ptr(desc, dma_addr_in, in_sz, 0);
+
+ append_seq_out_ptr(desc, dma_addr_out, out_sz, 0);
+
+ append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB);
+}
+
+void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
+ uint8_t *enc_blob, uint8_t *plain_txt,
+ uint32_t out_sz)
+{
+ dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
+ uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
+ uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE;
+
+ dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr);
+ dma_addr_in = virt_to_phys((void *)enc_blob);
+ dma_addr_out = virt_to_phys((void *)plain_txt);
+
+ init_job_desc(desc, 0);
+
+ append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2);
+
+ append_seq_in_ptr(desc, dma_addr_in, in_sz, 0);
+
+ append_seq_out_ptr(desc, dma_addr_out, out_sz, 0);
+
+ append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB);
+}
+
+/*
+ * Descriptor to instantiate RNG State Handle 0 in normal mode and
+ * load the JDKEK, TDKEK and TDSK registers
+ */
+void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc)
+{
+ uint32_t *jump_cmd;
+
+ init_job_desc(desc, 0);
+
+ /* INIT RNG in non-test mode */
+ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+ OP_ALG_AS_INIT);
+
+ /* wait for done */
+ jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
+ set_jump_tgt_here(desc, jump_cmd);
+
+ /*
+ * load 1 to clear written reg:
+ * resets the done interrrupt and returns the RNG to idle.
+ */
+ append_load_imm_uint32_t(desc, 1, LDST_SRCDST_WORD_CLRW);
+
+ /* generate secure keys (non-test) */
+ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+ OP_ALG_RNG4_SK);
+}
diff --git a/core/drivers/crypto/jobdesc.h b/core/drivers/crypto/jobdesc.h
new file mode 100644
index 0000000..f550458
--- /dev/null
+++ b/core/drivers/crypto/jobdesc.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __JOBDESC_H
+#define __JOBDESC_H
+
+#include <io.h>
+
+#define KEY_IDNFR_SZ_BYTES 16
+
+/* inline_cnstr_jobdesc_blob_dek:
+ * Intializes and constructs the job descriptor for DEK encapsulation
+ * using the given parameters.
+ * @desc: reference to the job descriptor
+ * @plain_txt: reference to the DEK
+ * @enc_blob: reference where to store the blob
+ * @in_sz: size in bytes of the DEK
+ * @return: 0 on success, ECONSTRJDESC otherwise
+ */
+int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
+ uint8_t *enc_blob, uint32_t in_sz);
+
+void inline_cnstr_jobdesc_hash(uint32_t *desc,
+ const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
+ uint32_t alg_type, uint32_t alg_size, int sg_tbl);
+
+void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
+ uint8_t *plain_txt, uint8_t *enc_blob,
+ uint32_t in_sz);
+
+void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
+ uint8_t *enc_blob, uint8_t *plain_txt,
+ uint32_t out_sz);
+
+void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc);
+#endif
diff --git a/core/drivers/crypto/jr.c b/core/drivers/crypto/jr.c
new file mode 100644
index 0000000..691367b
--- /dev/null
+++ b/core/drivers/crypto/jr.c
@@ -0,0 +1,489 @@
+#include <imx-regs.h>
+#include <io.h>
+#include <mm/core_memprot.h>
+#include <mm/core_mmu.h>
+#include <stdlib.h>
+#include <string.h>
+#include <trace.h>
+#include "fsl_sec.h"
+#include "jobdesc.h"
+#include "jr.h"
+#include "misc.h"
+
+#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
+#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
+
+struct jobring jr;
+
+static inline void start_jr0(void)
+{
+ ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ uint32_t ctpr_ms = read32((vaddr_t)&sec->ctpr_ms);
+ uint32_t scfgr = read32((vaddr_t)&sec->scfgr);
+
+ if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
+ /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
+ * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
+ */
+ if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
+ (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
+ (scfgr & SEC_SCFGR_VIRT_EN)))
+ write32(CONFIG_JRSTARTR_JR0, (vaddr_t)&sec->jrstartr);
+ } else {
+ /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
+ if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
+ write32(CONFIG_JRSTARTR_JR0, (vaddr_t)&sec->jrstartr);
+ }
+}
+
+static inline void jr_disable_irq(void)
+{
+ struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ uint32_t jrcfg = read32((vaddr_t)&regs->jrcfg1);
+
+ jrcfg = jrcfg | JR_INTMASK;
+
+ write32(jrcfg, (vaddr_t)&regs->jrcfg1);
+}
+
+static void jr_initregs(void)
+{
+ struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ paddr_t ip_base = virt_to_phys((void *)jr.input_ring);
+ paddr_t op_base = virt_to_phys((void *)jr.output_ring);
+
+#ifdef CFG_PHYS_64BIT
+ write32(ip_base >> 32, (vaddr_t)&regs->irba_h);
+#else
+ write32(0x0, (vaddr_t)&regs->irba_h);
+#endif
+ write32((uint32_t)ip_base, (vaddr_t)&regs->irba_l);
+#ifdef CFG_PHYS_64BIT
+ write32(op_base >> 32, (vaddr_t)&regs->orba_h);
+#else
+ write32(0x0, (vaddr_t)&regs->orba_h);
+#endif
+ write32((uint32_t)op_base, (vaddr_t)&regs->orba_l);
+ write32(JR_SIZE, (vaddr_t)&regs->ors);
+ write32(JR_SIZE, (vaddr_t)&regs->irs);
+
+ if (!jr.irq)
+ jr_disable_irq();
+}
+
+static int jr_init(void)
+{
+ memset(&jr, 0, sizeof(struct jobring));
+
+ jr.jq_id = DEFAULT_JR_ID;
+ jr.irq = DEFAULT_IRQ;
+
+#ifdef CFG_FSL_CORENET
+ jr.liodn = DEFAULT_JR_LIODN;
+#endif
+ jr.size = JR_SIZE;
+ jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+ JR_SIZE * sizeof(dma_addr_t));
+ if (!jr.input_ring)
+ return -1;
+ jr.output_ring =
+ (struct op_ring *)memalign(ARCH_DMA_MINALIGN,
+ JR_SIZE * sizeof(struct op_ring));
+ if (!jr.output_ring)
+ return -1;
+
+ memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
+ memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring));
+
+ start_jr0();
+
+ jr_initregs();
+
+ return 0;
+}
+
+static int jr_sw_cleanup(void)
+{
+ jr.head = 0;
+ jr.tail = 0;
+ jr.read_idx = 0;
+ jr.write_idx = 0;
+ memset(jr.info, 0, sizeof(jr.info));
+ memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
+ memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
+
+ return 0;
+}
+
+static int jr_hw_reset(void)
+{
+ struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ uint32_t timeout = 100000;
+ uint32_t jrint, jrcr;
+
+ write32(JRCR_RESET, (vaddr_t)&regs->jrcr);
+ do {
+ jrint = read32((vaddr_t)&regs->jrint);
+ } while (((jrint & JRINT_ERR_HALT_MASK) ==
+ JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+ jrint = read32((vaddr_t)&regs->jrint);
+ if (((jrint & JRINT_ERR_HALT_MASK) !=
+ JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+ return -1;
+
+ timeout = 100000;
+ write32(JRCR_RESET, (vaddr_t)&regs->jrcr);
+ do {
+ jrcr = read32((vaddr_t)&regs->jrcr);
+ } while ((jrcr & JRCR_RESET) && --timeout);
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
+/* -1 --- error, can't enqueue -- no space available */
+static int jr_enqueue(uint32_t *desc_addr,
+ void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void *arg)
+{
+ unsigned long start, end;
+ struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ int head = jr.head;
+ dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+
+ if (read32((vaddr_t)&regs->irsa) == 0 ||
+ CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
+ return -1;
+
+ jr.info[head].desc_phys_addr = desc_phys_addr;
+ jr.info[head].desc_addr = (uint32_t)desc_addr;
+ jr.info[head].callback = callback;
+ jr.info[head].arg = arg;
+ jr.info[head].op_done = 0;
+
+ start = (unsigned long)&jr.info[head] &
+ ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN(start + sizeof(struct jr_info),
+ ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start,
+ (size_t)(end-start));
+
+ jr.input_ring[head] = desc_phys_addr;
+ start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start,
+ (size_t)(end-start));
+
+ jr.head = (head + 1) & (jr.size - 1);
+
+ write32(1, (vaddr_t)&regs->irja);
+
+ return 0;
+}
+
+static int jr_dequeue(void)
+{
+ struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ int head = jr.head;
+ int tail = jr.tail;
+ int idx, i, found;
+ void (*callback)(uint32_t desc, uint32_t status, void *arg);
+ void *arg = NULL;
+
+ while (read32((vaddr_t)&regs->orsf)
+ && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+ dma_addr_t op_desc;
+ uint32_t status, desc_virt;
+ unsigned long start = (unsigned long)jr.output_ring &
+ ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start +
+ sizeof(struct op_ring)*JR_SIZE,
+ ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_INVALIDATE, (void*)start,
+ (size_t)(end-start));
+
+ found = 0;
+
+ op_desc = jr.output_ring[jr.tail].desc;
+ status = jr.output_ring[jr.tail].status;
+
+ for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
+ idx = (tail + i) & (jr.size - 1);
+ if (op_desc == jr.info[idx].desc_phys_addr) {
+ desc_virt = jr.info[idx].desc_addr;
+ found = 1;
+ break;
+ }
+ }
+
+ /* Error condition if match not found */
+ if (!found)
+ return -1;
+
+ jr.info[idx].op_done = 1;
+ callback = jr.info[idx].callback;
+ arg = jr.info[idx].arg;
+
+ /* When the job on tail idx gets done, increment
+ * tail till the point where job completed out of oredr has
+ * been taken into account
+ */
+ if (idx == tail)
+ do {
+ tail = (tail + 1) & (jr.size - 1);
+ } while (jr.info[tail].op_done);
+
+ jr.tail = tail;
+ jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
+
+ write32(1, (vaddr_t)&regs->orjr);
+ jr.info[idx].op_done = 0;
+
+ callback(desc_virt, status, arg);
+ }
+
+ return 0;
+}
+
+static void desc_done(uint32_t desc, uint32_t status, void *arg)
+{
+ struct result *x = arg;
+
+ (void)desc;
+ x->status = status;
+ caam_jr_strstatus(status);
+ x->done = 1;
+}
+
+int run_descriptor_jr(uint32_t *desc)
+{
+ /* unsigned long long timeval; */
+ /* unsigned long long timeout; */
+ struct result op;
+ int ret = 0;
+
+ memset(&op, 0, sizeof(op));
+
+ ret = jr_enqueue(desc, desc_done, &op);
+ if (ret) {
+ DMSG("Error in SEC enq\n");
+ ret = JQ_ENQ_ERR;
+ goto out;
+ }
+
+ /* timeval = get_ticks(); */
+ /* timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); */
+ while (op.done != 1) {
+ ret = jr_dequeue();
+ if (ret) {
+ DMSG("Error in SEC deq\n");
+ ret = JQ_DEQ_ERR;
+ goto out;
+ }
+/*
+ if ((get_ticks() - timeval) > timeout) {
+ DMSG("SEC Dequeue timed out\n");
+ ret = JQ_DEQ_TO_ERR;
+ goto out;
+ }
+*/
+ }
+
+ if (!op.status) {
+ DMSG("Error %x\n", op.status);
+ ret = op.status;
+ }
+out:
+ return ret;
+}
+
+int jr_reset(void)
+{
+ if (jr_hw_reset() < 0)
+ return -1;
+
+ /* Clean up the jobring structure maintained by software */
+ jr_sw_cleanup();
+
+ return 0;
+}
+
+int sec_reset(void)
+{
+ ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ uint32_t mcfgr = read32((vaddr_t)&sec->mcfgr);
+ uint32_t timeout = 100000;
+
+ mcfgr |= MCFGR_SWRST;
+ write32(mcfgr, (vaddr_t)&sec->mcfgr);
+
+ mcfgr |= MCFGR_DMA_RST;
+ write32(mcfgr, (vaddr_t)&sec->mcfgr);
+ do {
+ mcfgr = read32((vaddr_t)&sec->mcfgr);
+ } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
+
+ if (timeout == 0)
+ return -1;
+
+ timeout = 100000;
+ do {
+ mcfgr = read32((vaddr_t)&sec->mcfgr);
+ } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
+static int instantiate_rng(void)
+{
+ struct result op;
+ uint32_t *desc;
+ uint32_t rdsta_val;
+ int size;
+ int ret = 0;
+ ccsr_sec_t *sec =
+ (ccsr_sec_t *)CONFIG_SYS_FSL_SEC_ADDR;
+ struct rng4tst *rng =
+ (struct rng4tst *)&sec->rng;
+
+ memset(&op, 0, sizeof(struct result));
+
+ desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
+ if (!desc) {
+ IMSG("cannot allocate RNG init descriptor memory\n");
+ return -1;
+ }
+
+ inline_cnstr_jobdesc_rng_instantiation(desc);
+ size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, desc, (size_t)size);
+
+ ret = run_descriptor_jr(desc);
+
+ if (ret)
+ IMSG("RNG: Instantiation failed with error %x\n", ret);
+
+ rdsta_val = read32((vaddr_t)&rng->rdsta);
+ if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
+ return -1;
+
+ return ret;
+}
+
+static uint8_t get_rng_vid(void)
+{
+ ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ uint32_t cha_vid = read32((vaddr_t)&sec->chavid_ls);
+
+ return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
+}
+
+/*
+ * By default, the TRNG runs for 200 clocks per sample;
+ * 1200 clocks per sample generates better entropy.
+ */
+static void kick_trng(int ent_delay)
+{
+ ccsr_sec_t *sec =
+ (ccsr_sec_t *)CONFIG_SYS_FSL_SEC_ADDR;
+ struct rng4tst *rng =
+ (struct rng4tst *)&sec->rng;
+ uint32_t val;
+
+ /* put RNG4 into program mode */
+ write32(read32((vaddr_t)&rng->rtmctl) | RTMCTL_PRGM,
+ (vaddr_t)&rng->rtmctl);
+ /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
+ * length (in system clocks) of each Entropy sample taken
+ * */
+ val = read32((vaddr_t)&rng->rtsdctl);
+ val = (val & ~RTSDCTL_ENT_DLY_MASK) |
+ (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
+ write32(val, (vaddr_t)&rng->rtsdctl);
+ /* min. freq. count, equal to 1/4 of the entropy sample length */
+ write32(ent_delay >> 2, (vaddr_t)&rng->rtfreqmin);
+ /* max. freq. count, equal to 8 times the entropy sample length */
+ write32(ent_delay << 3, (vaddr_t)&rng->rtfreq_u.rtfreqmax);
+ /* put RNG4 into run mode */
+ write32(read32((vaddr_t)&rng->rtmctl) & ~RTMCTL_PRGM,
+ (vaddr_t)&rng->rtmctl);
+}
+
+static int rng_init(void)
+{
+ int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
+ ccsr_sec_t *sec =
+ (ccsr_sec_t *)CONFIG_SYS_FSL_SEC_ADDR;
+ struct rng4tst *rng =
+ (struct rng4tst *)&sec->rng;
+
+ uint32_t rdsta = read32((vaddr_t)&rng->rdsta);
+
+ /* Check if RNG state 0 handler is already instantiated */
+ if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
+ return 0;
+
+ do {
+ /*
+ * If either of the SH's were instantiated by somebody else
+ * then it is assumed that the entropy
+ * parameters are properly set and thus the function
+ * setting these (kick_trng(...)) is skipped.
+ * Also, if a handle was instantiated, do not change
+ * the TRNG parameters.
+ */
+ kick_trng(ent_delay);
+ ent_delay += 400;
+ /*
+ * if instantiate_rng(...) fails, the loop will rerun
+ * and the kick_trng(...) function will modfiy the
+ * upper and lower limits of the entropy sampling
+ * interval, leading to a sucessful initialization of
+ * the RNG.
+ */
+ ret = instantiate_rng();
+ } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
+ if (ret) {
+ IMSG("RNG: Failed to instantiate RNG\n");
+ return ret;
+ }
+
+ /* Enable RDB bit so that RNG works faster */
+ write32(read32((vaddr_t)&sec->scfgr) | SEC_SCFGR_RDBENABLE,
+ (vaddr_t)&sec->scfgr);
+
+ return ret;
+}
+
+int sec_init(void)
+{
+ int ret = 0;
+
+#ifdef CFG_PHYS_64BIT
+ ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ uint32_t mcr = read32(&sec->mcfgr);
+
+ write32(mcr | 1 << MCFGR_PS_SHIFT, &sec->mcfgr);
+#endif
+ ret = jr_init();
+ if (ret < 0) {
+ IMSG("SEC initialization failed\n");
+ return -1;
+ }
+
+ if (get_rng_vid() >= 4) {
+ if (rng_init() < 0) {
+ IMSG("RNG instantiation failed\n");
+ return -1;
+ }
+ IMSG("SEC: RNG instantiated\n");
+ }
+
+ return ret;
+}
diff --git a/core/drivers/crypto/jr.h b/core/drivers/crypto/jr.h
new file mode 100644
index 0000000..60fc654
--- /dev/null
+++ b/core/drivers/crypto/jr.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __JR_H
+#define __JR_H
+
+typedef uint32_t dma_addr_t;
+
+#define JR_SIZE 4
+/* Timeout currently defined as 90 sec */
+#define CONFIG_SEC_DEQ_TIMEOUT 90000000U
+
+#define DEFAULT_JR_ID 0
+#define DEFAULT_JR_LIODN 0
+#define DEFAULT_IRQ 0 /* Interrupts not to be configured */
+
+#define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */
+#define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */
+#define MCFGR_PS_SHIFT 16
+#define JR_INTMASK 0x00000001
+#define JRCR_RESET 0x01
+#define JRINT_ERR_HALT_INPROGRESS 0x4
+#define JRINT_ERR_HALT_MASK 0xc
+#define JRNSLIODN_SHIFT 16
+#define JRNSLIODN_MASK 0x0fff0000
+#define JRSLIODN_SHIFT 0
+#define JRSLIODN_MASK 0x00000fff
+
+#define JQ_DEQ_ERR -1
+#define JQ_DEQ_TO_ERR -2
+#define JQ_ENQ_ERR -3
+
+struct op_ring {
+ dma_addr_t desc;
+ uint32_t status;
+} __packed;
+
+struct jr_info {
+ void (*callback)(dma_addr_t desc, uint32_t status, void *arg);
+ dma_addr_t desc_phys_addr;
+ uint32_t desc_addr;
+ uint32_t desc_len;
+ uint32_t op_done;
+ void *arg;
+};
+
+struct jobring {
+ int jq_id;
+ int irq;
+ int liodn;
+ /* Head is the index where software would enq the descriptor in
+ * the i/p ring
+ */
+ int head;
+ /* Tail index would be used by s/w ehile enqueuing to determine if
+ * there is any space left in the s/w maintained i/p rings
+ */
+ /* Also in case of deq tail will be incremented only in case of
+ * in-order job completion
+ */
+ int tail;
+ /* Read index of the output ring. It may not match with tail in case
+ * of out of order completetion
+ */
+ int read_idx;
+ /* Write index to input ring. Would be always equal to head */
+ int write_idx;
+ /* Size of the rings. */
+ int size;
+ /* The ip and output rings have to be accessed by SEC. So the
+ * pointers will ahve to point to the housekeeping region provided
+ * by SEC
+ */
+ /*Circular Ring of i/p descriptors */
+ dma_addr_t *input_ring;
+ /* Circular Ring of o/p descriptors */
+ /* Circula Ring containing info regarding descriptors in i/p
+ * and o/p ring
+ */
+ /* This ring can be on the stack */
+ struct jr_info info[JR_SIZE];
+ struct op_ring *output_ring;
+};
+
+struct result {
+ int done;
+ uint32_t status;
+};
+
+void caam_jr_strstatus(uint32_t status);
+int run_descriptor_jr(uint32_t *desc);
+int jr_reset(void);
+int sec_reset(void);
+
+#endif
diff --git a/core/drivers/crypto/misc.h b/core/drivers/crypto/misc.h
new file mode 100644
index 0000000..ad147bb
--- /dev/null
+++ b/core/drivers/crypto/misc.h
@@ -0,0 +1,16 @@
+#ifndef MISC_H
+#define MISC_H
+
+#define ARCH_DMA_MINALIGN 64
+
+#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static inline uint32_t roundup(uint32_t x, uint32_t y) {
+ const uint32_t __y = y;
+ return (((x) + (__y - 1)) / __y) * __y;
+}
+
+#endif /* MISC_H */
diff --git a/core/drivers/crypto/sub.mk b/core/drivers/crypto/sub.mk
new file mode 100644
index 0000000..96afb04
--- /dev/null
+++ b/core/drivers/crypto/sub.mk
@@ -0,0 +1 @@
+srcs-$(CFG_FSL_CAAM) += error.c fsl_blob.c jobdesc.c jr.c
diff --git a/core/drivers/sub.mk b/core/drivers/sub.mk
index 802bfbc..27eea05 100644
--- a/core/drivers/sub.mk
+++ b/core/drivers/sub.mk
@@ -1,3 +1,5 @@
+subdirs-$(CFG_FSL_CAAM) += crypto
+
srcs-$(CFG_CDNS_UART) += cdns_uart.c
srcs-$(CFG_PL011) += pl011.c
srcs-$(CFG_PL050) += pl050.c
diff --git a/core/include/fsl_sec.h b/core/include/fsl_sec.h
new file mode 100644
index 0000000..77416ce
--- /dev/null
+++ b/core/include/fsl_sec.h
@@ -0,0 +1,267 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __FSL_SEC_H
+#define __FSL_SEC_H
+
+#include <imx-regs.h>
+#include <platform_config.h>
+#include <stdint.h>
+
+/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
+#if CFG_SYS_FSL_SEC_COMPAT >= 4
+/* RNG4 TRNG test registers */
+struct rng4tst {
+#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+ uint32_t rtmctl; /* misc. control register */
+ uint32_t rtscmisc; /* statistical check misc. register */
+ uint32_t rtpkrrng; /* poker range register */
+#define RTSDCTL_ENT_DLY_MIN 1200
+#define RTSDCTL_ENT_DLY_MAX 12800
+ union {
+ uint32_t rtpkrmax; /* PRGM=1: poker max. limit register */
+ uint32_t rtpkrsq; /* PRGM=0: poker square calc. result register */
+ } rtpkr_u;
+#define RTSDCTL_ENT_DLY_SHIFT 16
+#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
+ uint32_t rtsdctl; /* seed control register */
+ union {
+ uint32_t rtsblim; /* PRGM=1: sparse bit limit register */
+ uint32_t rttotsam; /* PRGM=0: total samples register */
+ } rt_u;
+ uint32_t rtfreqmin; /* frequency count min. limit register */
+ union {
+ uint32_t rtfreqmax; /* PRGM=1: freq. count max. limit register */
+ uint32_t rtfreqcnt; /* PRGM=0: freq. count register */
+ } rtfreq_u;
+ uint32_t rsvd1[40];
+#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
+ uint32_t rdsta; /*RNG DRNG Status Register*/
+ uint32_t rsvd2[15];
+};
+
+typedef struct ccsr_sec {
+ uint32_t res0;
+ uint32_t mcfgr; /* Master CFG Register */
+ uint8_t res1[0x4];
+ uint32_t scfgr;
+ struct {
+ uint32_t ms; /* Job Ring LIODN Register, MS */
+ uint32_t ls; /* Job Ring LIODN Register, LS */
+ } jrliodnr[4];
+ uint8_t res2[0x2c];
+ uint32_t jrstartr; /* Job Ring Start Register */
+ struct {
+ uint32_t ms; /* RTIC LIODN Register, MS */
+ uint32_t ls; /* RTIC LIODN Register, LS */
+ } rticliodnr[4];
+ uint8_t res3[0x1c];
+ uint32_t decorr; /* DECO Request Register */
+ struct {
+ uint32_t ms; /* DECO LIODN Register, MS */
+ uint32_t ls; /* DECO LIODN Register, LS */
+ } decoliodnr[8];
+ uint8_t res4[0x40];
+ uint32_t dar; /* DECO Avail Register */
+ uint32_t drr; /* DECO Reset Register */
+ uint8_t res5[0x4d8];
+ struct rng4tst rng; /* RNG Registers */
+ uint8_t res11[0x8a0];
+ uint32_t crnr_ms; /* CHA Revision Number Register, MS */
+ uint32_t crnr_ls; /* CHA Revision Number Register, LS */
+ uint32_t ctpr_ms; /* Compile Time Parameters Register, MS */
+ uint32_t ctpr_ls; /* Compile Time Parameters Register, LS */
+ uint8_t res6[0x10];
+ uint32_t far_ms; /* Fault Address Register, MS */
+ uint32_t far_ls; /* Fault Address Register, LS */
+ uint32_t falr; /* Fault Address LIODN Register */
+ uint32_t fadr; /* Fault Address Detail Register */
+ uint8_t res7[0x4];
+ uint32_t csta; /* CAAM Status Register */
+ uint8_t res8[0x8];
+ uint32_t rvid; /* Run Time Integrity Checking Version ID Reg.*/
+ uint32_t ccbvid; /* CHA Cluster Block Version ID Register */
+ uint32_t chavid_ms; /* CHA Version ID Register, MS */
+ uint32_t chavid_ls; /* CHA Version ID Register, LS */
+ uint32_t chanum_ms; /* CHA Number Register, MS */
+ uint32_t chanum_ls; /* CHA Number Register, LS */
+ uint32_t secvid_ms; /* SEC Version ID Register, MS */
+ uint32_t secvid_ls; /* SEC Version ID Register, LS */
+ uint8_t res9[0x6020];
+ uint32_t qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
+ uint32_t qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+ uint8_t res10[0x8fd8];
+} ccsr_sec_t;
+
+#define SEC_CTPR_MS_AXI_LIODN 0x08000000
+#define SEC_CTPR_MS_QI 0x02000000
+#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
+#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
+#define SEC_RVID_MA 0x0f000000
+#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
+#define SEC_CHANUM_MS_JRNUM_SHIFT 28
+#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
+#define SEC_CHANUM_MS_DECONUM_SHIFT 24
+#define SEC_SECVID_MS_IPID_MASK 0xffff0000
+#define SEC_SECVID_MS_IPID_SHIFT 16
+#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
+#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
+#define SEC_CCBVID_ERA_MASK 0xff000000
+#define SEC_CCBVID_ERA_SHIFT 24
+#define SEC_SCFGR_RDBENABLE 0x00000400
+#define SEC_SCFGR_VIRT_EN 0x00008000
+#define SEC_CHAVID_LS_RNG_SHIFT 16
+#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
+
+#define CONFIG_JRSTARTR_JR0 0x00000001
+
+struct jr_regs {
+#if defined(CFG_SYS_FSL_SEC_LE) && !defined(CFG_MX6)
+ uint32_t irba_l;
+ uint32_t irba_h;
+#else
+ uint32_t irba_h;
+ uint32_t irba_l;
+#endif
+ uint32_t rsvd1;
+ uint32_t irs;
+ uint32_t rsvd2;
+ uint32_t irsa;
+ uint32_t rsvd3;
+ uint32_t irja;
+#if defined(CFG_SYS_FSL_SEC_LE) && !defined(CFG_MX6)
+ uint32_t orba_l;
+ uint32_t orba_h;
+#else
+ uint32_t orba_h;
+ uint32_t orba_l;
+#endif
+ uint32_t rsvd4;
+ uint32_t ors;
+ uint32_t rsvd5;
+ uint32_t orjr;
+ uint32_t rsvd6;
+ uint32_t orsf;
+ uint32_t rsvd7;
+ uint32_t jrsta;
+ uint32_t rsvd8;
+ uint32_t jrint;
+ uint32_t jrcfg0;
+ uint32_t jrcfg1;
+ uint32_t rsvd9;
+ uint32_t irri;
+ uint32_t rsvd10;
+ uint32_t orwi;
+ uint32_t rsvd11;
+ uint32_t jrcr;
+};
+
+/*
+ * Scatter Gather Entry - Specifies the the Scatter Gather Format
+ * related information
+ */
+struct sg_entry {
+#if defined(CFG_SYS_FSL_SEC_LE) && !defined(CFG_MX6)
+ uint32_t addr_lo; /* Memory Address - lo */
+ uint16_t addr_hi; /* Memory Address of start of buffer - hi */
+ uint16_t reserved_zero;
+#else
+ uint16_t reserved_zero;
+ uint16_t addr_hi; /* Memory Address of start of buffer - hi */
+ uint32_t addr_lo; /* Memory Address - lo */
+#endif
+
+ uint32_t len_flag; /* Length of the data in the frame */
+#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
+#define SG_ENTRY_EXTENSION_BIT 0x80000000
+#define SG_ENTRY_FINAL_BIT 0x40000000
+ uint32_t bpid_offset;
+#define SG_ENTRY_BPID_MASK 0x00FF0000
+#define SG_ENTRY_BPID_SHIFT 16
+#define SG_ENTRY_OFFSET_MASK 0x00001FFF
+#define SG_ENTRY_OFFSET_SHIFT 0
+};
+
+#ifdef CFG_MX6
+/* CAAM Job Ring 0 Registers */
+/* Secure Memory Partition Owner register */
+#define SMCSJR_PO (3 << 6)
+/* JR Allocation Error */
+#define SMCSJR_AERR (3 << 12)
+/* Secure memory partition 0 page 0 owner register */
+#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
+/* Secure memory command register */
+#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
+/* Secure memory command status register */
+#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
+/* Secure memory access permissions register */
+#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
+/* Secure memory access group 2 register */
+#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
+/* Secure memory access group 1 register */
+#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
+
+/* Commands and macros for secure memory */
+#define CMD_PAGE_ALLOC 0x1
+#define CMD_PAGE_DEALLOC 0x2
+#define CMD_PART_DEALLOC 0x3
+#define CMD_INQUIRY 0x5
+#define CMD_COMPLETE (3 << 14)
+#define PAGE_AVAILABLE 0
+#define PAGE_OWNED (3 << 6)
+#define PAGE(x) (x << 16)
+#define PARTITION(x) (x << 8)
+#define PARTITION_OWNER(x) (0x3 << (x*2))
+
+/* Address of secure 4kbyte pages */
+#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
+#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
+#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
+#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
+
+#define JR_MID 2 /* Matches ROM configuration */
+#define KS_G1 (1 << JR_MID) /* CAAM only */
+#define PERM 0x0000B008 /* Clear on release, lock SMAP
+ * lock SMAG group 1 Blob */
+
+#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
+
+/* HAB WRAPPED KEY header */
+#define WRP_HDR_SIZE 0x08
+#define HDR_TAG 0x81
+#define HDR_PAR 0x41
+/* HAB WRAPPED KEY Data */
+#define HAB_MOD 0x66
+#define HAB_ALG 0x55
+#define HAB_FLG 0x00
+
+/* Partition and Page IDs */
+#define PARTITION_1 1
+#define PAGE_1 1
+
+#define ERROR_IN_PAGE_ALLOC 1
+#define ECONSTRJDESC -1
+
+#endif
+
+int sec_init(void);
+
+int blob_decap(uint8_t *key_mod, uint8_t *src, uint8_t *dst, uint32_t len);
+int blob_encap(uint8_t *key_mod, uint8_t *src, uint8_t *dst, uint32_t len);
+
+/* blob_dek:
+ * Encapsulates the src in a secure blob and stores it dst
+ * @src: reference to the plaintext
+ * @dst: reference to the output adrress
+ * @len: size in bytes of src
+ * @return: 0 on success, error otherwise
+ */
+int blob_dek(const uint8_t *src, uint8_t *dst, uint8_t len);
+
+#endif
+
+#endif /* __FSL_SEC_H */
--
1.9.5
Raw
0002-register-caam-phys_mem.patch
From b7e65f633906a60c431dca071060632e437af294 Mon Sep 17 00:00:00 2001
From: Jangseop Shin <jsshin@sor.snu.ac.kr>
Date: Fri, 24 Feb 2017 16:50:16 +0900
Subject: [PATCH 2/5] register caam phys_mem
---
core/arch/arm/plat-imx/main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/core/arch/arm/plat-imx/main.c b/core/arch/arm/plat-imx/main.c
index edfbc37..6481773 100644
--- a/core/arch/arm/plat-imx/main.c
+++ b/core/arch/arm/plat-imx/main.c
@@ -31,6 +31,7 @@
#include <console.h>
#include <drivers/gic.h>
#include <drivers/imx_uart.h>
+#include <imx-regs.h>
#include <io.h>
#include <kernel/generic_boot.h>
#include <kernel/misc.h>
@@ -71,6 +72,7 @@ register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
defined(PLATFORM_FLAVOR_mx6qsabresd)
register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE);
register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE);
+register_phys_mem(MEM_AREA_IO_SEC, CAAM_BASE_ADDR, CORE_MMU_DEVICE_SIZE);
#endif
const struct thread_handlers *generic_boot_get_handlers(void)
--
1.9.5
Raw
0003-convert-physical-to-virtual-address.patch
From 3b7665f269c20283975fdd23945055c1f2361d18 Mon Sep 17 00:00:00 2001
From: Jangseop Shin <jsshin@sor.snu.ac.kr>
Date: Sat, 25 Feb 2017 19:36:09 +0900
Subject: [PATCH 3/5] convert physical to virtual address
---
core/arch/arm/plat-imx/caam_cmds.c | 3 +-
core/arch/arm/plat-imx/clock.c | 9 +++--
core/arch/arm/plat-imx/get_virt.h | 14 +++++++
core/drivers/crypto/jobdesc.c | 19 ++++-----
core/drivers/crypto/jr.c | 83 +++++++++++++++++++-------------------
5 files changed, 73 insertions(+), 55 deletions(-)
create mode 100644 core/arch/arm/plat-imx/get_virt.h
diff --git a/core/arch/arm/plat-imx/caam_cmds.c b/core/arch/arm/plat-imx/caam_cmds.c
index 40332d0..cec9495 100644
--- a/core/arch/arm/plat-imx/caam_cmds.c
+++ b/core/arch/arm/plat-imx/caam_cmds.c
@@ -4,6 +4,7 @@
#include <io.h>
#include <stdint.h>
#include <trace.h>
+#include "get_virt.h"
#include "fsl_sec.h"
/**
@@ -19,7 +20,7 @@
int ret = 0;
uint32_t jr_size = 4;
- uint32_t out_jr_size = read32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+ uint32_t out_jr_size = read32(get_virt(CONFIG_SYS_FSL_JR0_ADDR) + 0x102c);
if (out_jr_size != jr_size) {
caam_clock_enable(1);
sec_init();
diff --git a/core/arch/arm/plat-imx/clock.c b/core/arch/arm/plat-imx/clock.c
index 64bc93b..b028122 100644
--- a/core/arch/arm/plat-imx/clock.c
+++ b/core/arch/arm/plat-imx/clock.c
@@ -2,6 +2,7 @@
#include <clock.h>
#include <crm_regs.h>
#include <imx-regs.h>
+#include "get_virt.h"
#include "fsl_sec.h"
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -11,7 +12,7 @@ void caam_clock_enable(unsigned char enable)
uint32_t reg;
/* CG4 ~ CG6, CAAM clocks */
- reg = read32((vaddr_t)&imx_ccm->CCGR0);
+ reg = read32(get_virt((paddr_t)&imx_ccm->CCGR0));
if (enable)
reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
@@ -20,13 +21,13 @@ void caam_clock_enable(unsigned char enable)
reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- write32(reg, (vaddr_t)&imx_ccm->CCGR0);
+ write32(reg, get_virt((paddr_t)&imx_ccm->CCGR0));
/* EMI slow clk */
- reg = read32((vaddr_t)&imx_ccm->CCGR6);
+ reg = read32(get_virt((paddr_t)&imx_ccm->CCGR6));
if (enable)
reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
else
reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
- write32(reg, (vaddr_t)&imx_ccm->CCGR6);
+ write32(reg, get_virt((paddr_t)&imx_ccm->CCGR6));
}
diff --git a/core/arch/arm/plat-imx/get_virt.h b/core/arch/arm/plat-imx/get_virt.h
new file mode 100644
index 0000000..a522c13
--- /dev/null
+++ b/core/arch/arm/plat-imx/get_virt.h
@@ -0,0 +1,14 @@
+#ifndef CAAM_VA_H
+#define CAAM_VA_H
+
+#include <mm/core_mmu.h>
+#include <mm/core_memprot.h>
+
+static vaddr_t get_virt(paddr_t pa)
+{
+ if (cpu_mmu_enabled())
+ return (vaddr_t)phys_to_virt(pa, MEM_AREA_IO_SEC);
+ return (vaddr_t)pa;
+}
+
+#endif /* CAAM_VA_H */
diff --git a/core/drivers/crypto/jobdesc.c b/core/drivers/crypto/jobdesc.c
index e16c4c5..79712d5 100644
--- a/core/drivers/crypto/jobdesc.c
+++ b/core/drivers/crypto/jobdesc.c
@@ -12,6 +12,7 @@
#include <mm/core_memprot.h>
#include <trace.h>
#include "desc_constr.h"
+#include "get_virt.h"
#include "jobdesc.h"
#include "misc.h"
@@ -26,10 +27,10 @@ static uint32_t secmem_set_cmd(uint32_t sec_mem_cmd)
{
uint32_t temp_reg;
- write32(sec_mem_cmd, (vaddr_t)CAAM_SMCJR0);
+ write32(sec_mem_cmd, get_virt(CAAM_SMCJR0));
do {
- temp_reg = read32((vaddr_t)CAAM_SMCSJR0);
+ temp_reg = read32(get_virt(CAAM_SMCSJR0));
} while (temp_reg & CMD_COMPLETE);
return temp_reg;
@@ -55,7 +56,7 @@ static int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
/*
* De-Allocate partition_num if already allocated to ARM core
*/
- if (read32((vaddr_t)CAAM_SMPO_0) & PARTITION_OWNER(partition_num)) {
+ if (read32(get_virt(CAAM_SMPO_0)) & PARTITION_OWNER(partition_num)) {
temp_reg = secmem_set_cmd(PARTITION(partition_num) |
CMD_PART_DEALLOC);
if (temp_reg & SMCSJR_AERR) {
@@ -65,9 +66,9 @@ static int caam_page_alloc(uint8_t page_num, uint8_t partition_num)
}
/* set the access rights to allow full access */
- write32(0xF, (vaddr_t)CAAM_SMAG1JR0(partition_num));
- write32(0xF, (vaddr_t)CAAM_SMAG2JR0(partition_num));
- write32(0xFF, (vaddr_t)CAAM_SMAPJR0(partition_num));
+ write32(0xF, get_virt(CAAM_SMAG1JR0(partition_num)));
+ write32(0xF, get_virt(CAAM_SMAG2JR0(partition_num)));
+ write32(0xFF, get_virt(CAAM_SMAPJR0(partition_num)));
/* Now need to allocate partition_num of secure RAM. */
/* De-Allocate page_num by starting with a page inquiry command */
@@ -136,9 +137,9 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
(size_t)(end - start));
/* Now configure the access rights of the partition */
- write32(KS_G1, (vaddr_t)CAAM_SMAG1JR0(PARTITION_1)); /* set group 1 */
- write32(0, (vaddr_t)CAAM_SMAG2JR0(PARTITION_1)); /* clear group 2 */
- write32(PERM, (vaddr_t)CAAM_SMAPJR0(PARTITION_1)); /* set perm & locks */
+ write32(KS_G1, get_virt(CAAM_SMAG1JR0(PARTITION_1))); /* set group 1 */
+ write32(0, get_virt(CAAM_SMAG2JR0(PARTITION_1))); /* clear group 2 */
+ write32(PERM, get_virt(CAAM_SMAPJR0(PARTITION_1))); /* set perm & locks */
/* construct aad for AES */
aad_w1 = (in_sz << OP_ALG_ALGSEL_SHIFT) | KEY_AES_SRC | LD_CCM_MODE;
diff --git a/core/drivers/crypto/jr.c b/core/drivers/crypto/jr.c
index 691367b..c791069 100644
--- a/core/drivers/crypto/jr.c
+++ b/core/drivers/crypto/jr.c
@@ -6,6 +6,7 @@
#include <string.h>
#include <trace.h>
#include "fsl_sec.h"
+#include "get_virt.h"
#include "jobdesc.h"
#include "jr.h"
#include "misc.h"
@@ -18,8 +19,8 @@ struct jobring jr;
static inline void start_jr0(void)
{
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
- uint32_t ctpr_ms = read32((vaddr_t)&sec->ctpr_ms);
- uint32_t scfgr = read32((vaddr_t)&sec->scfgr);
+ uint32_t ctpr_ms = read32(get_virt((paddr_t)&sec->ctpr_ms));
+ uint32_t scfgr = read32(get_virt((paddr_t)&sec->scfgr));
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
@@ -28,22 +29,22 @@ static inline void start_jr0(void)
if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
(!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
(scfgr & SEC_SCFGR_VIRT_EN)))
- write32(CONFIG_JRSTARTR_JR0, (vaddr_t)&sec->jrstartr);
+ write32(CONFIG_JRSTARTR_JR0, get_virt((paddr_t)&sec->jrstartr));
} else {
/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
- write32(CONFIG_JRSTARTR_JR0, (vaddr_t)&sec->jrstartr);
+ write32(CONFIG_JRSTARTR_JR0, get_virt((paddr_t)&sec->jrstartr));
}
}
static inline void jr_disable_irq(void)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- uint32_t jrcfg = read32((vaddr_t)&regs->jrcfg1);
+ uint32_t jrcfg = read32(get_virt((paddr_t)&regs->jrcfg1));
jrcfg = jrcfg | JR_INTMASK;
- write32(jrcfg, (vaddr_t)&regs->jrcfg1);
+ write32(jrcfg, get_virt((paddr_t)&regs->jrcfg1));
}
static void jr_initregs(void)
@@ -53,19 +54,19 @@ static void jr_initregs(void)
paddr_t op_base = virt_to_phys((void *)jr.output_ring);
#ifdef CFG_PHYS_64BIT
- write32(ip_base >> 32, (vaddr_t)&regs->irba_h);
+ write32(ip_base >> 32, get_virt((paddr_t)&regs->irba_h));
#else
- write32(0x0, (vaddr_t)&regs->irba_h);
+ write32(0x0, get_virt((paddr_t)&regs->irba_h));
#endif
- write32((uint32_t)ip_base, (vaddr_t)&regs->irba_l);
+ write32((uint32_t)ip_base, get_virt((paddr_t)&regs->irba_l));
#ifdef CFG_PHYS_64BIT
- write32(op_base >> 32, (vaddr_t)&regs->orba_h);
+ write32(op_base >> 32, get_virt((paddr_t)&regs->orba_h));
#else
- write32(0x0, (vaddr_t)&regs->orba_h);
+ write32(0x0, get_virt((paddr_t)&regs->orba_h));
#endif
- write32((uint32_t)op_base, (vaddr_t)&regs->orba_l);
- write32(JR_SIZE, (vaddr_t)&regs->ors);
- write32(JR_SIZE, (vaddr_t)&regs->irs);
+ write32((uint32_t)op_base, get_virt((paddr_t)&regs->orba_l));
+ write32(JR_SIZE, get_virt((paddr_t)&regs->ors));
+ write32(JR_SIZE, get_virt((paddr_t)&regs->irs));
if (!jr.irq)
jr_disable_irq();
@@ -121,21 +122,21 @@ static int jr_hw_reset(void)
uint32_t timeout = 100000;
uint32_t jrint, jrcr;
- write32(JRCR_RESET, (vaddr_t)&regs->jrcr);
+ write32(JRCR_RESET, get_virt((paddr_t)&regs->jrcr));
do {
- jrint = read32((vaddr_t)&regs->jrint);
+ jrint = read32(get_virt((paddr_t)&regs->jrint));
} while (((jrint & JRINT_ERR_HALT_MASK) ==
JRINT_ERR_HALT_INPROGRESS) && --timeout);
- jrint = read32((vaddr_t)&regs->jrint);
+ jrint = read32(get_virt((paddr_t)&regs->jrint));
if (((jrint & JRINT_ERR_HALT_MASK) !=
JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
return -1;
timeout = 100000;
- write32(JRCR_RESET, (vaddr_t)&regs->jrcr);
+ write32(JRCR_RESET, get_virt((paddr_t)&regs->jrcr));
do {
- jrcr = read32((vaddr_t)&regs->jrcr);
+ jrcr = read32(get_virt((paddr_t)&regs->jrcr));
} while ((jrcr & JRCR_RESET) && --timeout);
if (timeout == 0)
@@ -154,7 +155,7 @@ static int jr_enqueue(uint32_t *desc_addr,
int head = jr.head;
dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
- if (read32((vaddr_t)&regs->irsa) == 0 ||
+ if (read32(get_virt((paddr_t)&regs->irsa)) == 0 ||
CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
return -1;
@@ -179,7 +180,7 @@ static int jr_enqueue(uint32_t *desc_addr,
jr.head = (head + 1) & (jr.size - 1);
- write32(1, (vaddr_t)&regs->irja);
+ write32(1, get_virt((paddr_t)&regs->irja));
return 0;
}
@@ -193,7 +194,7 @@ static int jr_dequeue(void)
void (*callback)(uint32_t desc, uint32_t status, void *arg);
void *arg = NULL;
- while (read32((vaddr_t)&regs->orsf)
+ while (read32(get_virt((paddr_t)&regs->orsf))
&& CIRC_CNT(jr.head, jr.tail, jr.size)) {
dma_addr_t op_desc;
uint32_t status, desc_virt;
@@ -239,7 +240,7 @@ static int jr_dequeue(void)
jr.tail = tail;
jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
- write32(1, (vaddr_t)&regs->orjr);
+ write32(1, get_virt((paddr_t)&regs->orjr));
jr.info[idx].op_done = 0;
callback(desc_virt, status, arg);
@@ -314,16 +315,16 @@ int jr_reset(void)
int sec_reset(void)
{
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
- uint32_t mcfgr = read32((vaddr_t)&sec->mcfgr);
+ uint32_t mcfgr = read32(get_virt((paddr_t)&sec->mcfgr));
uint32_t timeout = 100000;
mcfgr |= MCFGR_SWRST;
- write32(mcfgr, (vaddr_t)&sec->mcfgr);
+ write32(mcfgr, get_virt((paddr_t)&sec->mcfgr));
mcfgr |= MCFGR_DMA_RST;
- write32(mcfgr, (vaddr_t)&sec->mcfgr);
+ write32(mcfgr, get_virt((paddr_t)&sec->mcfgr));
do {
- mcfgr = read32((vaddr_t)&sec->mcfgr);
+ mcfgr = read32(get_virt((paddr_t)&sec->mcfgr));
} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
if (timeout == 0)
@@ -331,7 +332,7 @@ int sec_reset(void)
timeout = 100000;
do {
- mcfgr = read32((vaddr_t)&sec->mcfgr);
+ mcfgr = read32(get_virt((paddr_t)&sec->mcfgr));
} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
if (timeout == 0)
@@ -369,7 +370,7 @@ static int instantiate_rng(void)
if (ret)
IMSG("RNG: Instantiation failed with error %x\n", ret);
- rdsta_val = read32((vaddr_t)&rng->rdsta);
+ rdsta_val = read32(get_virt((paddr_t)&rng->rdsta));
if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
return -1;
@@ -379,7 +380,7 @@ static int instantiate_rng(void)
static uint8_t get_rng_vid(void)
{
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
- uint32_t cha_vid = read32((vaddr_t)&sec->chavid_ls);
+ uint32_t cha_vid = read32(get_virt((paddr_t)&sec->chavid_ls));
return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
}
@@ -397,22 +398,22 @@ static void kick_trng(int ent_delay)
uint32_t val;
/* put RNG4 into program mode */
- write32(read32((vaddr_t)&rng->rtmctl) | RTMCTL_PRGM,
- (vaddr_t)&rng->rtmctl);
+ write32(read32(get_virt((paddr_t)&rng->rtmctl)) | RTMCTL_PRGM,
+ get_virt((paddr_t)&rng->rtmctl));
/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
* length (in system clocks) of each Entropy sample taken
* */
- val = read32((vaddr_t)&rng->rtsdctl);
+ val = read32(get_virt((paddr_t)&rng->rtsdctl));
val = (val & ~RTSDCTL_ENT_DLY_MASK) |
(ent_delay << RTSDCTL_ENT_DLY_SHIFT);
- write32(val, (vaddr_t)&rng->rtsdctl);
+ write32(val, get_virt((paddr_t)&rng->rtsdctl));
/* min. freq. count, equal to 1/4 of the entropy sample length */
- write32(ent_delay >> 2, (vaddr_t)&rng->rtfreqmin);
+ write32(ent_delay >> 2, get_virt((paddr_t)&rng->rtfreqmin));
/* max. freq. count, equal to 8 times the entropy sample length */
- write32(ent_delay << 3, (vaddr_t)&rng->rtfreq_u.rtfreqmax);
+ write32(ent_delay << 3, get_virt((paddr_t)&rng->rtfreq_u.rtfreqmax));
/* put RNG4 into run mode */
- write32(read32((vaddr_t)&rng->rtmctl) & ~RTMCTL_PRGM,
- (vaddr_t)&rng->rtmctl);
+ write32(read32(get_virt((paddr_t)&rng->rtmctl)) & ~RTMCTL_PRGM,
+ get_virt((paddr_t)&rng->rtmctl));
}
static int rng_init(void)
@@ -423,7 +424,7 @@ static int rng_init(void)
struct rng4tst *rng =
(struct rng4tst *)&sec->rng;
- uint32_t rdsta = read32((vaddr_t)&rng->rdsta);
+ uint32_t rdsta = read32(get_virt((paddr_t)&rng->rdsta));
/* Check if RNG state 0 handler is already instantiated */
if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
@@ -455,8 +456,8 @@ static int rng_init(void)
}
/* Enable RDB bit so that RNG works faster */
- write32(read32((vaddr_t)&sec->scfgr) | SEC_SCFGR_RDBENABLE,
- (vaddr_t)&sec->scfgr);
+ write32(read32(get_virt((paddr_t)&sec->scfgr)) | SEC_SCFGR_RDBENABLE,
+ get_virt((paddr_t)&sec->scfgr));
return ret;
}
--
1.9.5
Raw
0004-clean-inv-l2-cache-also.patch
From 7d4f0cb814abbe7bc77322b67d15bda99dfe6cff Mon Sep 17 00:00:00 2001
From: Jangseop Shin <jsshin@sor.snu.ac.kr>
Date: Sat, 25 Feb 2017 19:38:13 +0900
Subject: [PATCH 4/5] clean/inv l2 cache also
---
core/drivers/crypto/fsl_blob.c | 11 ++++++++---
core/drivers/crypto/jobdesc.c | 5 +++--
core/drivers/crypto/jr.c | 17 +++++++++++------
3 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/core/drivers/crypto/fsl_blob.c b/core/drivers/crypto/fsl_blob.c
index 9da00e6..304c805 100644
--- a/core/drivers/crypto/fsl_blob.c
+++ b/core/drivers/crypto/fsl_blob.c
@@ -84,9 +84,13 @@ int blob_dek(const uint8_t *src, uint8_t *dst, uint8_t len)
} else {
size = roundup(sizeof(uint32_t) * DEK_BLOB_DESCSIZE,
ARCH_DMA_MINALIGN);
- cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, desc, (size_t)size);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, desc, size);
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys(desc),
+ size);
size = roundup(sizeof(uint8_t) * out_sz, ARCH_DMA_MINALIGN);
- cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, dst, (size_t)size);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, dst, size);
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys(dst),
+ size);
ret = run_descriptor_jr(desc);
}
@@ -97,7 +101,8 @@ int blob_dek(const uint8_t *src, uint8_t *dst, uint8_t len)
}
size = roundup(out_sz, ARCH_DMA_MINALIGN);
- cache_maintenance_l1(DCACHE_AREA_INVALIDATE, dst, (size_t)size);
+ cache_maintenance_l1(DCACHE_AREA_INVALIDATE, dst, size);
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys(dst), size);
IMSG("DEK Blob\n");
for (i = 0; i < out_sz; i++)
diff --git a/core/drivers/crypto/jobdesc.c b/core/drivers/crypto/jobdesc.c
index 79712d5..9eca9ef 100644
--- a/core/drivers/crypto/jobdesc.c
+++ b/core/drivers/crypto/jobdesc.c
@@ -133,8 +133,9 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
start = (unsigned long)SEC_MEM_PAGE1 &
~(ARCH_DMA_MINALIGN - 1);
end = ALIGN(start + 0x1000, ARCH_DMA_MINALIGN);
- cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start,
- (size_t)(end - start));
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start, (end - start));
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys((void*)start),
+ (end-start));
/* Now configure the access rights of the partition */
write32(KS_G1, get_virt(CAAM_SMAG1JR0(PARTITION_1))); /* set group 1 */
diff --git a/core/drivers/crypto/jr.c b/core/drivers/crypto/jr.c
index c791069..44f7b36 100644
--- a/core/drivers/crypto/jr.c
+++ b/core/drivers/crypto/jr.c
@@ -169,14 +169,16 @@ static int jr_enqueue(uint32_t *desc_addr,
~(ARCH_DMA_MINALIGN - 1);
end = ALIGN(start + sizeof(struct jr_info),
ARCH_DMA_MINALIGN);
- cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start,
- (size_t)(end-start));
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start, (end-start));
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys((void*)start),
+ (end-start));
jr.input_ring[head] = desc_phys_addr;
start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
- cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start,
- (size_t)(end-start));
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start, (end-start));
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys((void*)start),
+ (end-start));
jr.head = (head + 1) & (jr.size - 1);
@@ -204,7 +206,9 @@ static int jr_dequeue(void)
sizeof(struct op_ring)*JR_SIZE,
ARCH_DMA_MINALIGN);
cache_maintenance_l1(DCACHE_AREA_INVALIDATE, (void*)start,
- (size_t)(end-start));
+ (end-start));
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys((void*)start),
+ (end-start));
found = 0;
@@ -363,7 +367,8 @@ static int instantiate_rng(void)
inline_cnstr_jobdesc_rng_instantiation(desc);
size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
- cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, desc, (size_t)size);
+ cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, desc, size);
+ cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, virt_to_phys(desc), size);
ret = run_descriptor_jr(desc);
--
1.9.5
Raw
0005-register-CAAM-secure-memory-mapping.patch
From f8552e785694a3fafb3983f4f32b8ee235151af3 Mon Sep 17 00:00:00 2001
From: Jangseop Shin <jsshin@sor.snu.ac.kr>
Date: Sat, 25 Feb 2017 19:38:26 +0900
Subject: [PATCH 5/5] register CAAM secure memory mapping
---
core/arch/arm/plat-imx/main.c | 3 +++
core/drivers/crypto/jobdesc.c | 5 +++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/core/arch/arm/plat-imx/main.c b/core/arch/arm/plat-imx/main.c
index 6481773..943467e 100644
--- a/core/arch/arm/plat-imx/main.c
+++ b/core/arch/arm/plat-imx/main.c
@@ -72,7 +72,10 @@ register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
defined(PLATFORM_FLAVOR_mx6qsabresd)
register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE);
register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE);
+/* caam mmaped registers */
register_phys_mem(MEM_AREA_IO_SEC, CAAM_BASE_ADDR, CORE_MMU_DEVICE_SIZE);
+/* caam secure memory */
+register_phys_mem(MEM_AREA_IO_SEC, CAAM_ARB_BASE_ADDR, CORE_MMU_DEVICE_SIZE);
#endif
const struct thread_handlers *generic_boot_get_handlers(void)
diff --git a/core/drivers/crypto/jobdesc.c b/core/drivers/crypto/jobdesc.c
index 9eca9ef..531b04b 100644
--- a/core/drivers/crypto/jobdesc.c
+++ b/core/drivers/crypto/jobdesc.c
@@ -128,9 +128,10 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
return ret;
/* Write DEK to secure memory */
- memcpy((void*)SEC_MEM_PAGE1, plain_txt, in_sz);
+ start = get_virt(SEC_MEM_PAGE1);
+ memcpy((void*)start, plain_txt, in_sz);
- start = (unsigned long)SEC_MEM_PAGE1 &
+ start = (unsigned long)start &
~(ARCH_DMA_MINALIGN - 1);
end = ALIGN(start + 0x1000, ARCH_DMA_MINALIGN);
cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void*)start, (end - start));
--
1.9.5
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