Skitspråk

gistfile1.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity bcd59 is
  port (
    clk, ce, reset : in  std_logic;
    count          : out std_logic_vector(7 downto 0);
    ceo            : out std_logic
    ) ;
end entity;  -- bcd59

architecture arch of bcd59 is
  signal ce2, ce2next, ceonext          : std_logic;
  signal loOut, hiOut : std_logic_vector(3 downto 0);
begin
  -- Den minst signifikanta siffran
  lower : process (ce, clk, reset) is
  begin
    if clk'event and clk = '1' then
      ce2 <= ce2next;
      ceo <= ceonext;
      if reset = '1' then
        loOut <= "0000";
        hiOut <= "0000";
        ce2next <= '0';
      elsif ce = '1' then
        if loOut = "1001" then
          loOut <= "0000";
        else
          loOut <= loOut + 1;
        end if;  -- if loOut = 0
      end if;  -- if reset = 1
    end if;  -- if clock
  end process;

  -- skapar count enable till den mest signifikanta siffran
  ce2next <= not ce2next when loOut = "1001";
  ceonext   <= ce when hiOut & loOut = "01011001" else '0';
  -- Den mest signifikanta siffran
  upper : process (ce2) is
  begin
    if hiOut = "0101" then
      hiOut <= "0000";
    else
      hiOut <= hiOut + 1;
    end if;
  end process;

  count <= hiOut & loOut;
end architecture;  -- arch

gistfile2.txt

-- jesper josefsson
-- 110214
restart -f nowave
view signals wave
-- add wave count clk reset ceo ce2next ce2
force clk '0' 0, '1' 50 -repeat 100
force reset '1'
run 100
force reset '0'
force ce '1'
run 10000

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