I have a lazy friend wildcard who needs help creating his FPGA design. Implement a PCIe device with an option rom by using the LiteX Python framework.

litepcie_opt_rom.py

from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform

# Create the platform object
platform = XilinxPlatform("my_platform")

# Add the PCIe device to the platform
platform.add_extension([
    ("pcie_phy", 0,
        Subsignal("rst_n", Pins("")),
        Subsignal("clk_p", Pins("")),
        Subsignal("clk_n", Pins("")),
        Subsignal("tx_p", Pins("")),
        Subsignal("tx_n", Pins("")),
        Subsignal("rx_p", Pins("")),
        Subsignal("rx_n", Pins(""))
    ),
    ("pcie_core", 0,
        Subsignal("rst_n", Pins("")),
        Subsignal("clk_p", Pins("")),
        Subsignal("clk_n", Pins("")),
        Subsignal("tx_p", Pins("")),
        Subsignal("tx_n", Pins("")),
        Subsignal("rx_p", Pins("")),
        Subsignal("rx_n", Pins(""))
    ),
    ("pcie_mgmt", 0,
        Subsignal("rst_n", Pins("")),
        Subsignal("clk_p", Pins("")),
        Subsignal("clk_n", Pins("")),
        Subsignal("tx_p", Pins("")),
        Subsignal("tx_n", Pins("")),
        Subsignal("rx_p", Pins("")),
        Subsignal("rx_n", Pins(""))
    ),
    ("pcie_mgmt_intr", 0, Pins("")),
    ("pcie_mgmt_rst_n", 0, Pins("")),
    ("pcie_mgmt_clk", 0, Pins("")),
    ("pcie_mgmt_wake", 0, Pins(""))
])

# Create the PCIe device
class PCIeDevice(Module):
    def __init__(self):
        self.submodules.pcie_phy = LitePCIEPHY(platform, platform.request("pcie_phy"))
        self.submodules.pcie_core = LitePCIECore(self.pcie_phy, with_reordering=True)
        self.submodules.pcie_mgmt = LitePCIEMgmt(self.pcie_core)

# Create the FPGA design
class PCIeDesign(PcieDesign):
    def __init__(self, platform):
        PcieDesign.__init__(self, platform)
        self.submodules.pcie_device =