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jevinskie/deca_leds.py

Created February 9, 2022 00:32
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FHDL verilog generation issue
Raw
deca_leds.py
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import deca
from litex.soc.cores.clock import Max10PLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_hdmi = ClockDomain()
self.clock_domains.cd_usb = ClockDomain()
# # #
# Clk / Rst.
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_hdmi, 40e6)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_uartbone=False, with_jtagbone=False,
**kwargs):
self.platform = platform = deca.Platform()
# Defaults to JTAG-UART since no hardware UART.
real_uart_name = kwargs["uart_name"]
if real_uart_name == "serial":
kwargs["uart_name"] = "jtag_uart"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Terasic DECA",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
# Bug --------------------------------------------------------------------------------------
input_pads = platform.request("gpio")
# this is what I want to work but only user_led7 is ever set
led_pads = platform.request_all("user_led")
# this works as expected
# led_pads = [platform.request("user_led") for i in range(8)]
for src, sink in zip(input_pads, led_pads):
self.comb += sink.eq(src)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
args.cpu_type = "None"
soc = BaseSoC(
sys_clk_freq = int(50e6),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=False)
if __name__ == "__main__":
main()
Raw
opt-request_all.v
/* Generated by Yosys 0.13+39 (git sha1 9c9366895, clang 10.0.0-4ubuntu1 -fPIC -Os) */
(* cells_not_processed = 1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:20.1-1836.10" *)
module terasic_deca(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_tdo, clk50, gpio, user_led0, user_led1, user_led2, user_led3, user_led4, user_led5, user_led6, user_led7);
(* src = "build/terasic_deca/gateware/terasic_deca.v:1689.1-1693.4" *)
wire [1:0] _000_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1689.1-1693.4" *)
wire [9:0] _001_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1689.1-1693.4" *)
wire [9:0] _002_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1694.1-1696.4" *)
wire [9:0] _003_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1379.41-1379.81" *)
wire [3:0] _004_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1405.41-1405.80" *)
wire [4:0] _005_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:766.54-766.102" *)
wire [2:0] _006_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:775.54-775.102" *)
wire [2:0] _007_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:805.54-805.102" *)
wire [2:0] _008_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:814.54-814.102" *)
wire [2:0] _009_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:836.40-836.65" *)
wire [2:0] _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:756.52-756.131" *)
wire _031_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:756.136-756.215" *)
wire _032_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:795.52-795.131" *)
wire _033_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:795.136-795.215" *)
wire _034_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:840.10-840.36" *)
wire _035_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1736.21-1736.30" *)
wire [9:0] _036_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:756.221-756.300" *)
wire _037_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:795.221-795.300" *)
wire _038_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:928.97-928.132" *)
wire _039_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:958.97-958.132" *)
wire _040_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:756.51-756.216" *)
wire _041_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:795.51-795.216" *)
wire _042_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:928.96-928.164" *)
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire [3:0] _061_;
wire [3:0] _062_;
wire [3:0] _063_;
wire [3:0] _064_;
wire [3:0] _065_;
wire [3:0] _066_;
wire [3:0] _067_;
wire [3:0] _068_;
wire [3:0] _069_;
wire [3:0] _070_;
wire [3:0] _071_;
wire [3:0] _072_;
wire [3:0] _073_;
wire [3:0] _074_;
wire [3:0] _075_;
wire [4:0] _076_;
wire [4:0] _077_;
wire [4:0] _078_;
wire _079_;
wire _080_;
wire _081_;
wire [1:0] _082_;
wire [1:0] _083_;
wire [1:0] _084_;
wire [1:0] _085_;
wire _086_;
wire [2:0] _087_;
wire _088_;
wire [7:0] _089_;
wire [7:0] _090_;
wire _091_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1387.41-1387.80" *)
wire [4:0] _092_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1409.41-1409.80" *)
wire [4:0] _093_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:22.14-22.33" *)
input altera_reserved_tck;
wire altera_reserved_tck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:23.14-23.33" *)
input altera_reserved_tdi;
wire altera_reserved_tdi;
(* src = "build/terasic_deca/gateware/terasic_deca.v:24.14-24.33" *)
output altera_reserved_tdo;
wire altera_reserved_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:21.14-21.33" *)
input altera_reserved_tms;
wire altera_reserved_tms;
(* src = "build/terasic_deca/gateware/terasic_deca.v:393.13-393.32" *)
wire [13:0] builder_basesoc_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:395.13-395.34" *)
wire [31:0] builder_basesoc_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:394.6-394.24" *)
wire builder_basesoc_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:397.13-397.41" *)
wire [29:0] builder_basesoc_wishbone_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:401.6-401.34" *)
wire builder_basesoc_wishbone_cyc;
(* src = "build/terasic_deca/gateware/terasic_deca.v:398.13-398.43" *)
wire [31:0] builder_basesoc_wishbone_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:400.12-400.40" *)
wire [3:0] builder_basesoc_wishbone_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:402.6-402.34" *)
wire builder_basesoc_wishbone_stb;
(* src = "build/terasic_deca/gateware/terasic_deca.v:404.6-404.33" *)
wire builder_basesoc_wishbone_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:392.12-392.24" *)
wire [1:0] builder_clks;
(* src = "build/terasic_deca/gateware/terasic_deca.v:426.12-426.37" *)
wire [5:0] builder_csr_bankarray_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:418.13-418.56" *)
wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:417.6-417.50" *)
wire builder_csr_bankarray_csrbank0_bus_errors_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:419.6-419.50" *)
wire builder_csr_bankarray_csrbank0_bus_errors_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:410.12-410.51" *)
wire [1:0] builder_csr_bankarray_csrbank0_reset0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:409.6-409.46" *)
wire builder_csr_bankarray_csrbank0_reset0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:411.6-411.46" *)
wire builder_csr_bankarray_csrbank0_reset0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:414.13-414.54" *)
wire [31:0] builder_csr_bankarray_csrbank0_scratch0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:413.6-413.48" *)
wire builder_csr_bankarray_csrbank0_scratch0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:415.6-415.48" *)
wire builder_csr_bankarray_csrbank0_scratch0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:421.6-421.40" *)
wire builder_csr_bankarray_csrbank0_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:443.6-443.42" *)
wire builder_csr_bankarray_csrbank1_en0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:442.6-442.43" *)
wire builder_csr_bankarray_csrbank1_en0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:444.6-444.43" *)
wire builder_csr_bankarray_csrbank1_en0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:463.6-463.49" *)
wire builder_csr_bankarray_csrbank1_ev_enable0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:462.6-462.50" *)
wire builder_csr_bankarray_csrbank1_ev_enable0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:464.6-464.50" *)
wire builder_csr_bankarray_csrbank1_ev_enable0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:459.6-459.49" *)
wire builder_csr_bankarray_csrbank1_ev_pending_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:458.6-458.50" *)
wire builder_csr_bankarray_csrbank1_ev_pending_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:460.6-460.50" *)
wire builder_csr_bankarray_csrbank1_ev_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:455.6-455.48" *)
wire builder_csr_bankarray_csrbank1_ev_status_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:454.6-454.49" *)
wire builder_csr_bankarray_csrbank1_ev_status_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:456.6-456.49" *)
wire builder_csr_bankarray_csrbank1_ev_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:435.13-435.51" *)
wire [31:0] builder_csr_bankarray_csrbank1_load0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:434.6-434.45" *)
wire builder_csr_bankarray_csrbank1_load0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:436.6-436.45" *)
wire builder_csr_bankarray_csrbank1_load0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:439.13-439.53" *)
wire [31:0] builder_csr_bankarray_csrbank1_reload0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:438.6-438.47" *)
wire builder_csr_bankarray_csrbank1_reload0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:440.6-440.47" *)
wire builder_csr_bankarray_csrbank1_reload0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:466.6-466.40" *)
wire builder_csr_bankarray_csrbank1_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:447.6-447.52" *)
wire builder_csr_bankarray_csrbank1_update_value0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:446.6-446.53" *)
wire builder_csr_bankarray_csrbank1_update_value0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:448.6-448.53" *)
wire builder_csr_bankarray_csrbank1_update_value0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:451.13-451.51" *)
wire [31:0] builder_csr_bankarray_csrbank1_value_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:450.6-450.45" *)
wire builder_csr_bankarray_csrbank1_value_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:452.6-452.45" *)
wire builder_csr_bankarray_csrbank1_value_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:488.12-488.55" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_enable0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:487.6-487.50" *)
wire builder_csr_bankarray_csrbank2_ev_enable0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:489.6-489.50" *)
wire builder_csr_bankarray_csrbank2_ev_enable0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:484.12-484.55" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_pending_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:483.6-483.50" *)
wire builder_csr_bankarray_csrbank2_ev_pending_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:485.6-485.50" *)
wire builder_csr_bankarray_csrbank2_ev_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:480.12-480.54" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:479.6-479.49" *)
wire builder_csr_bankarray_csrbank2_ev_status_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:482.12-482.54" *)
(* unused_bits = "0" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:481.6-481.49" *)
wire builder_csr_bankarray_csrbank2_ev_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:476.6-476.46" *)
wire builder_csr_bankarray_csrbank2_rxempty_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:475.6-475.47" *)
wire builder_csr_bankarray_csrbank2_rxempty_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:477.6-477.47" *)
wire builder_csr_bankarray_csrbank2_rxempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:496.6-496.45" *)
wire builder_csr_bankarray_csrbank2_rxfull_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:495.6-495.46" *)
wire builder_csr_bankarray_csrbank2_rxfull_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:497.6-497.46" *)
wire builder_csr_bankarray_csrbank2_rxfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:499.6-499.40" *)
wire builder_csr_bankarray_csrbank2_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:492.6-492.46" *)
wire builder_csr_bankarray_csrbank2_txempty_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:491.6-491.47" *)
wire builder_csr_bankarray_csrbank2_txempty_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:493.6-493.47" *)
wire builder_csr_bankarray_csrbank2_txempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:472.6-472.45" *)
wire builder_csr_bankarray_csrbank2_txfull_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:471.6-471.46" *)
wire builder_csr_bankarray_csrbank2_txfull_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:473.6-473.46" *)
wire builder_csr_bankarray_csrbank2_txfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:405.13-405.58" *)
wire [13:0] builder_csr_bankarray_interface0_bank_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:407.13-407.60" *)
wire [31:0] builder_csr_bankarray_interface0_bank_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:406.6-406.50" *)
wire builder_csr_bankarray_interface0_bank_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:430.13-430.58" *)
wire [13:0] builder_csr_bankarray_interface1_bank_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:432.13-432.60" *)
wire [31:0] builder_csr_bankarray_interface1_bank_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:431.6-431.50" *)
wire builder_csr_bankarray_interface1_bank_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:467.13-467.58" *)
wire [13:0] builder_csr_bankarray_interface2_bank_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:469.13-469.60" *)
wire [31:0] builder_csr_bankarray_interface2_bank_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:468.6-468.50" *)
wire builder_csr_bankarray_interface2_bank_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:428.6-428.31" *)
wire builder_csr_bankarray_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:422.13-422.47" *)
wire [13:0] builder_csr_bankarray_sram_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:424.13-424.49" *)
wire [31:0] builder_csr_bankarray_sram_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:423.6-423.39" *)
wire builder_csr_bankarray_sram_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:500.13-500.41" *)
wire [13:0] builder_csr_interconnect_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:502.13-502.43" *)
wire [31:0] builder_csr_interconnect_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:501.6-501.33" *)
wire builder_csr_interconnect_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:383.12-383.40" *)
wire [3:0] builder_max10jtag_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:382.12-382.35" *)
reg [3:0] builder_max10jtag_state = 4'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:515.12-515.39" *)
reg [2:0] builder_multiregimpl0_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:516.12-516.39" *)
reg [2:0] builder_multiregimpl0_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:517.12-517.39" *)
reg [2:0] builder_multiregimpl1_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:518.12-518.39" *)
reg [2:0] builder_multiregimpl1_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:519.12-519.39" *)
reg [2:0] builder_multiregimpl2_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:520.12-520.39" *)
reg [2:0] builder_multiregimpl2_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:521.12-521.39" *)
reg [2:0] builder_multiregimpl3_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:522.12-522.39" *)
reg [2:0] builder_multiregimpl3_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:385.12-385.44" *)
wire [1:0] builder_resetinserter_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:384.12-384.39" *)
reg [1:0] builder_resetinserter_state = 2'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:514.6-514.23" *)
wire builder_rst_meta0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:523.6-523.23" *)
wire builder_rst_meta1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:524.6-524.23" *)
wire builder_rst_meta2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:506.12-506.32" *)
(* unused_bits = "0 1 2 3 4 5 6 7" *)
wire [7:0] builder_slice_proxy0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:507.12-507.32" *)
(* unused_bits = "0 1 2 3 4 5 6 7" *)
wire [7:0] builder_slice_proxy1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:508.12-508.32" *)
(* unused_bits = "0 1 2 3 4 5 6 7" *)
wire [7:0] builder_slice_proxy2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:509.12-509.32" *)
(* unused_bits = "0 1 2 3 4 5 6 7" *)
wire [7:0] builder_slice_proxy3;
(* src = "build/terasic_deca/gateware/terasic_deca.v:510.12-510.32" *)
(* unused_bits = "0 1 2 3 4 5 6 7" *)
wire [7:0] builder_slice_proxy4;
(* src = "build/terasic_deca/gateware/terasic_deca.v:511.12-511.32" *)
(* unused_bits = "0 1 2 3 4 5 6 7" *)
wire [7:0] builder_slice_proxy5;
(* src = "build/terasic_deca/gateware/terasic_deca.v:512.12-512.32" *)
(* unused_bits = "0 1 2 3 4 5 6 7" *)
wire [7:0] builder_slice_proxy6;
(* src = "build/terasic_deca/gateware/terasic_deca.v:513.12-513.32" *)
wire [7:0] builder_slice_proxy7;
(* src = "build/terasic_deca/gateware/terasic_deca.v:25.14-25.19" *)
input clk50;
wire clk50;
(* src = "build/terasic_deca/gateware/terasic_deca.v:26.21-26.25" *)
input [43:0] gpio;
wire [43:0] gpio;
(* src = "build/terasic_deca/gateware/terasic_deca.v:375.6-375.14" *)
wire hdmi_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:376.6-376.14" *)
wire hdmi_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:133.6-133.14" *)
wire jtag_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:100.6-100.18" *)
wire jtag_inv_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:134.6-134.14" *)
wire jtag_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:61.13-61.29" *)
wire [10:0] main_basesoc_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:51.6-51.28" *)
wire main_basesoc_bus_error;
(* src = "build/terasic_deca/gateware/terasic_deca.v:49.6-49.32" *)
wire main_basesoc_bus_errors_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:79.12-79.30" *)
reg [2:0] main_basesoc_count = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:390.12-390.42" *)
wire [2:0] main_basesoc_count_next_value2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:391.6-391.39" *)
wire main_basesoc_count_next_value_ce2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:64.13-64.31" *)
wire [31:0] main_basesoc_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:78.12-78.29" *)
reg [7:0] main_basesoc_data = 8'h00;
(* src = "build/terasic_deca/gateware/terasic_deca.v:388.12-388.41" *)
wire [7:0] main_basesoc_data_next_value1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:389.6-389.38" *)
wire main_basesoc_data_next_value_ce1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:215.6-215.28" *)
wire main_basesoc_fsm_reset;
(* src = "build/terasic_deca/gateware/terasic_deca.v:108.6-108.34" *)
wire main_basesoc_jtag_CAPTURE_DR;
(* src = "build/terasic_deca/gateware/terasic_deca.v:102.6-102.40" *)
wire main_basesoc_jtag_TEST_LOGIC_RESET;
(* src = "build/terasic_deca/gateware/terasic_deca.v:91.6-91.43" *)
wire main_basesoc_jtag_altera_reserved_tck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:93.6-93.43" *)
wire main_basesoc_jtag_altera_reserved_tdi;
(* src = "build/terasic_deca/gateware/terasic_deca.v:94.6-94.43" *)
wire main_basesoc_jtag_altera_reserved_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:92.6-92.43" *)
wire main_basesoc_jtag_altera_reserved_tms;
(* src = "build/terasic_deca/gateware/terasic_deca.v:81.6-81.31" *)
reg main_basesoc_jtag_capture = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:85.6-85.28" *)
wire main_basesoc_jtag_drck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:101.6-101.35" *)
wire main_basesoc_jtag_is_ongoing0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:107.6-107.35" *)
wire main_basesoc_jtag_is_ongoing3;
(* src = "build/terasic_deca/gateware/terasic_deca.v:80.6-80.29" *)
reg main_basesoc_jtag_reset = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:84.6-84.31" *)
wire main_basesoc_jtag_runtest;
(* src = "build/terasic_deca/gateware/terasic_deca.v:86.6-86.27" *)
wire main_basesoc_jtag_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:82.6-82.29" *)
wire main_basesoc_jtag_shift;
(* src = "build/terasic_deca/gateware/terasic_deca.v:87.6-87.27" *)
wire main_basesoc_jtag_tck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:97.6-97.31" *)
wire main_basesoc_jtag_tckutap;
(* src = "build/terasic_deca/gateware/terasic_deca.v:89.6-89.27" *)
wire main_basesoc_jtag_tdi;
(* src = "build/terasic_deca/gateware/terasic_deca.v:98.6-98.31" *)
wire main_basesoc_jtag_tdiutap;
(* src = "build/terasic_deca/gateware/terasic_deca.v:90.6-90.27" *)
wire main_basesoc_jtag_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:95.6-95.31" *)
reg main_basesoc_jtag_tdouser = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:88.6-88.27" *)
wire main_basesoc_jtag_tms;
(* src = "build/terasic_deca/gateware/terasic_deca.v:96.6-96.31" *)
wire main_basesoc_jtag_tmsutap;
(* src = "build/terasic_deca/gateware/terasic_deca.v:83.6-83.30" *)
wire main_basesoc_jtag_update;
(* src = "build/terasic_deca/gateware/terasic_deca.v:53.13-53.37" *)
wire [29:0] main_basesoc_ram_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:57.6-57.30" *)
wire main_basesoc_ram_bus_cyc;
(* src = "build/terasic_deca/gateware/terasic_deca.v:54.13-54.39" *)
wire [31:0] main_basesoc_ram_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:56.12-56.36" *)
wire [3:0] main_basesoc_ram_bus_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:58.6-58.30" *)
wire main_basesoc_ram_bus_stb;
(* src = "build/terasic_deca/gateware/terasic_deca.v:60.6-60.29" *)
wire main_basesoc_ram_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:189.12-189.45" *)
wire [9:0] main_basesoc_rx_cdc_asyncfifo_din;
(* src = "build/terasic_deca/gateware/terasic_deca.v:187.6-187.38" *)
wire main_basesoc_rx_cdc_asyncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:188.6-188.44" *)
wire main_basesoc_rx_cdc_asyncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:185.6-185.38" *)
wire main_basesoc_rx_cdc_asyncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:186.6-186.44" *)
wire main_basesoc_rx_cdc_asyncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:202.12-202.47" *)
wire [2:0] main_basesoc_rx_cdc_consume_wdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:210.6-210.39" *)
wire main_basesoc_rx_cdc_fifo_in_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:211.6-211.38" *)
wire main_basesoc_rx_cdc_fifo_in_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:209.12-209.52" *)
wire [7:0] main_basesoc_rx_cdc_fifo_in_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:191.6-191.41" *)
wire main_basesoc_rx_cdc_graycounter0_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:192.12-192.46" *)
reg [2:0] main_basesoc_rx_cdc_graycounter0_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:194.12-194.53" *)
reg [2:0] main_basesoc_rx_cdc_graycounter0_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:193.12-193.51" *)
wire [2:0] main_basesoc_rx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:195.12-195.58" *)
wire [2:0] main_basesoc_rx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:196.6-196.41" *)
wire main_basesoc_rx_cdc_graycounter1_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:197.12-197.46" *)
reg [2:0] main_basesoc_rx_cdc_graycounter1_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:199.12-199.53" *)
reg [2:0] main_basesoc_rx_cdc_graycounter1_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:198.12-198.51" *)
wire [2:0] main_basesoc_rx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:200.12-200.58" *)
wire [2:0] main_basesoc_rx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:201.12-201.47" *)
wire [2:0] main_basesoc_rx_cdc_produce_rdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:207.12-207.42" *)
wire [1:0] main_basesoc_rx_cdc_rdport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:177.6-177.36" *)
wire main_basesoc_rx_cdc_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:178.6-178.35" *)
wire main_basesoc_rx_cdc_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:179.12-179.49" *)
wire [7:0] main_basesoc_rx_cdc_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:176.6-176.36" *)
wire main_basesoc_rx_cdc_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:175.6-175.36" *)
wire main_basesoc_rx_cdc_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:181.6-181.38" *)
wire main_basesoc_rx_cdc_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:180.6-180.38" *)
wire main_basesoc_rx_cdc_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:203.12-203.42" *)
wire [1:0] main_basesoc_rx_cdc_wrport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:206.12-206.44" *)
wire [9:0] main_basesoc_rx_cdc_wrport_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:205.6-205.35" *)
wire main_basesoc_rx_cdc_wrport_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:69.6-69.34" *)
wire main_basesoc_sink_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:70.6-70.33" *)
wire main_basesoc_sink_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:71.12-71.47" *)
wire [7:0] main_basesoc_sink_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:68.6-68.34" *)
wire main_basesoc_sink_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:67.6-67.34" *)
wire main_basesoc_sink_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:73.6-73.38" *)
wire main_basesoc_source_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:72.6-72.38" *)
wire main_basesoc_source_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:365.6-365.35" *)
wire main_basesoc_timer_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:361.6-361.34" *)
wire main_basesoc_timer_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:351.6-351.33" *)
wire main_basesoc_timer_value_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:149.12-149.45" *)
wire [9:0] main_basesoc_tx_cdc_asyncfifo_din;
(* src = "build/terasic_deca/gateware/terasic_deca.v:150.12-150.46" *)
(* unused_bits = "8 9" *)
wire [9:0] main_basesoc_tx_cdc_asyncfifo_dout;
(* src = "build/terasic_deca/gateware/terasic_deca.v:147.6-147.38" *)
wire main_basesoc_tx_cdc_asyncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:148.6-148.44" *)
wire main_basesoc_tx_cdc_asyncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:145.6-145.38" *)
wire main_basesoc_tx_cdc_asyncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:146.6-146.44" *)
wire main_basesoc_tx_cdc_asyncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:162.12-162.47" *)
wire [2:0] main_basesoc_tx_cdc_consume_wdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:170.6-170.39" *)
wire main_basesoc_tx_cdc_fifo_in_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:171.6-171.38" *)
wire main_basesoc_tx_cdc_fifo_in_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:169.12-169.52" *)
wire [7:0] main_basesoc_tx_cdc_fifo_in_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:173.6-173.40" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_fifo_out_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:174.6-174.39" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_fifo_out_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:172.12-172.53" *)
wire [7:0] main_basesoc_tx_cdc_fifo_out_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:151.6-151.41" *)
wire main_basesoc_tx_cdc_graycounter0_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:152.12-152.46" *)
reg [2:0] main_basesoc_tx_cdc_graycounter0_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:154.12-154.53" *)
reg [2:0] main_basesoc_tx_cdc_graycounter0_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:153.12-153.51" *)
wire [2:0] main_basesoc_tx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:155.12-155.58" *)
wire [2:0] main_basesoc_tx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:156.6-156.41" *)
wire main_basesoc_tx_cdc_graycounter1_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:157.12-157.46" *)
reg [2:0] main_basesoc_tx_cdc_graycounter1_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:159.12-159.53" *)
reg [2:0] main_basesoc_tx_cdc_graycounter1_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:158.12-158.51" *)
wire [2:0] main_basesoc_tx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:160.12-160.58" *)
wire [2:0] main_basesoc_tx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:161.12-161.47" *)
wire [2:0] main_basesoc_tx_cdc_produce_rdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:167.12-167.42" *)
wire [1:0] main_basesoc_tx_cdc_rdport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:168.12-168.44" *)
(* unused_bits = "8 9" *)
wire [9:0] main_basesoc_tx_cdc_rdport_dat_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:137.6-137.36" *)
wire main_basesoc_tx_cdc_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:138.6-138.35" *)
wire main_basesoc_tx_cdc_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:139.12-139.49" *)
wire [7:0] main_basesoc_tx_cdc_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:136.6-136.36" *)
wire main_basesoc_tx_cdc_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:135.6-135.36" *)
wire main_basesoc_tx_cdc_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:142.6-142.38" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_source_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:143.6-143.37" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_source_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:144.12-144.51" *)
wire [7:0] main_basesoc_tx_cdc_source_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:141.6-141.38" *)
wire main_basesoc_tx_cdc_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:140.6-140.38" *)
wire main_basesoc_tx_cdc_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:163.12-163.42" *)
wire [1:0] main_basesoc_tx_cdc_wrport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:166.12-166.44" *)
wire [9:0] main_basesoc_tx_cdc_wrport_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:165.6-165.35" *)
wire main_basesoc_tx_cdc_wrport_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:247.12-247.39" *)
wire [1:0] main_basesoc_uart_pending_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:246.6-246.34" *)
wire main_basesoc_uart_pending_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:245.6-245.34" *)
wire main_basesoc_uart_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:238.6-238.27" *)
wire main_basesoc_uart_rx0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:235.6-235.32" *)
wire main_basesoc_uart_rx_clear;
(* src = "build/terasic_deca/gateware/terasic_deca.v:331.6-331.39" *)
wire main_basesoc_uart_rx_fifo_do_read;
(* src = "build/terasic_deca/gateware/terasic_deca.v:323.12-323.44" *)
reg [4:0] main_basesoc_uart_rx_fifo_level0 = 5'h00;
(* src = "build/terasic_deca/gateware/terasic_deca.v:334.6-334.41" *)
wire main_basesoc_uart_rx_fifo_rdport_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:315.6-315.34" *)
wire main_basesoc_uart_rx_fifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:316.6-316.40" *)
reg main_basesoc_uart_rx_fifo_readable = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:324.6-324.39" *)
wire main_basesoc_uart_rx_fifo_replace;
(* src = "build/terasic_deca/gateware/terasic_deca.v:306.6-306.42" *)
wire main_basesoc_uart_rx_fifo_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:305.6-305.42" *)
wire main_basesoc_uart_rx_fifo_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:311.6-311.44" *)
wire main_basesoc_uart_rx_fifo_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:310.6-310.44" *)
wire main_basesoc_uart_rx_fifo_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:319.6-319.43" *)
wire main_basesoc_uart_rx_fifo_syncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:320.6-320.49" *)
wire main_basesoc_uart_rx_fifo_syncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:317.6-317.43" *)
wire main_basesoc_uart_rx_fifo_syncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:318.6-318.49" *)
wire main_basesoc_uart_rx_fifo_syncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:232.6-232.33" *)
wire main_basesoc_uart_rx_status;
(* src = "build/terasic_deca/gateware/terasic_deca.v:234.6-234.34" *)
wire main_basesoc_uart_rx_trigger;
(* src = "build/terasic_deca/gateware/terasic_deca.v:224.6-224.34" *)
wire main_basesoc_uart_rxempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:256.6-256.33" *)
wire main_basesoc_uart_rxfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:217.12-217.36" *)
wire [7:0] main_basesoc_uart_rxtx_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:216.6-216.31" *)
wire main_basesoc_uart_rxtx_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:218.6-218.31" *)
wire main_basesoc_uart_rxtx_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:239.12-239.43" *)
(* unused_bits = "0" *)
wire [1:0] main_basesoc_uart_status_status;
(* src = "build/terasic_deca/gateware/terasic_deca.v:240.6-240.33" *)
wire main_basesoc_uart_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:237.6-237.27" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:289.12-289.45" *)
reg [3:0] main_basesoc_uart_tx_fifo_consume = 4'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:294.6-294.39" *)
wire main_basesoc_uart_tx_fifo_do_read;
(* src = "build/terasic_deca/gateware/terasic_deca.v:300.6-300.45" *)
wire main_basesoc_uart_tx_fifo_fifo_in_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:301.6-301.44" *)
wire main_basesoc_uart_tx_fifo_fifo_in_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:299.12-299.58" *)
wire [7:0] main_basesoc_uart_tx_fifo_fifo_in_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:303.6-303.46" *)
wire main_basesoc_uart_tx_fifo_fifo_out_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:304.6-304.45" *)
wire main_basesoc_uart_tx_fifo_fifo_out_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:302.12-302.59" *)
wire [7:0] main_basesoc_uart_tx_fifo_fifo_out_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:286.12-286.44" *)
reg [4:0] main_basesoc_uart_tx_fifo_level0 = 5'h00;
(* src = "build/terasic_deca/gateware/terasic_deca.v:295.12-295.48" *)
wire [3:0] main_basesoc_uart_tx_fifo_rdport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:296.12-296.50" *)
wire [9:0] main_basesoc_uart_tx_fifo_rdport_dat_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:297.6-297.41" *)
wire main_basesoc_uart_tx_fifo_rdport_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:278.6-278.34" *)
wire main_basesoc_uart_tx_fifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:279.6-279.40" *)
reg main_basesoc_uart_tx_fifo_readable = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:287.6-287.39" *)
wire main_basesoc_uart_tx_fifo_replace;
(* src = "build/terasic_deca/gateware/terasic_deca.v:270.6-270.42" *)
wire main_basesoc_uart_tx_fifo_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:271.6-271.41" *)
wire main_basesoc_uart_tx_fifo_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:272.12-272.55" *)
wire [7:0] main_basesoc_uart_tx_fifo_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:269.6-269.42" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_fifo_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:268.6-268.42" *)
wire main_basesoc_uart_tx_fifo_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:275.6-275.44" *)
wire main_basesoc_uart_tx_fifo_source_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:276.6-276.43" *)
wire main_basesoc_uart_tx_fifo_source_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:277.12-277.57" *)
wire [7:0] main_basesoc_uart_tx_fifo_source_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:274.6-274.44" *)
wire main_basesoc_uart_tx_fifo_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:273.6-273.44" *)
wire main_basesoc_uart_tx_fifo_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:284.12-284.50" *)
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_din;
(* src = "build/terasic_deca/gateware/terasic_deca.v:285.12-285.51" *)
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_dout;
(* src = "build/terasic_deca/gateware/terasic_deca.v:282.6-282.43" *)
wire main_basesoc_uart_tx_fifo_syncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:283.6-283.49" *)
wire main_basesoc_uart_tx_fifo_syncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:280.6-280.43" *)
wire main_basesoc_uart_tx_fifo_syncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:281.6-281.49" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_fifo_syncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:293.12-293.50" *)
wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:292.6-292.41" *)
wire main_basesoc_uart_tx_fifo_wrport_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:227.6-227.33" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_status;
(* src = "build/terasic_deca/gateware/terasic_deca.v:229.6-229.34" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_trigger;
(* src = "build/terasic_deca/gateware/terasic_deca.v:253.6-253.34" *)
wire main_basesoc_uart_txempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:221.6-221.33" *)
wire main_basesoc_uart_txfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:259.6-259.39" *)
wire main_basesoc_uart_uart_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:258.6-258.39" *)
wire main_basesoc_uart_uart_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:265.6-265.41" *)
wire main_basesoc_uart_uart_source_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:266.6-266.40" *)
wire main_basesoc_uart_uart_source_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:267.12-267.54" *)
wire [7:0] main_basesoc_uart_uart_source_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:264.6-264.41" *)
wire main_basesoc_uart_uart_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:263.6-263.41" *)
wire main_basesoc_uart_uart_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:77.6-77.24" *)
reg main_basesoc_valid = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:386.6-386.36" *)
wire main_basesoc_valid_next_value0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:387.6-387.39" *)
wire main_basesoc_valid_next_value_ce0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:63.12-63.27" *)
wire [3:0] main_basesoc_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:379.6-379.20" *)
wire main_crg_clkin;
(* src = "build/terasic_deca/gateware/terasic_deca.v:380.6-380.22" *)
wire main_crg_clkout0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:381.6-381.22" *)
wire main_crg_clkout1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:378.6-378.21" *)
wire main_crg_locked;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1728.11-1728.25" *)
reg [9:0] storage_2_dat1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1688.11-1688.23" *)
(* unused_bits = "8 9" *)
reg [9:0] storage_dat1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:373.6-373.13" *)
wire sys_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:65.6-65.18" *)
wire sys_jtag_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:66.6-66.18" *)
wire sys_jtag_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:374.6-374.13" *)
wire sys_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:27.14-27.23" *)
output user_led0;
wire user_led0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:28.14-28.23" *)
output user_led1;
wire user_led1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:29.14-29.23" *)
output user_led2;
wire user_led2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:30.14-30.23" *)
output user_led3;
wire user_led3;
(* src = "build/terasic_deca/gateware/terasic_deca.v:31.14-31.23" *)
output user_led4;
wire user_led4;
(* src = "build/terasic_deca/gateware/terasic_deca.v:32.14-32.23" *)
output user_led5;
wire user_led5;
(* src = "build/terasic_deca/gateware/terasic_deca.v:33.14-33.23" *)
output user_led6;
wire user_led6;
(* src = "build/terasic_deca/gateware/terasic_deca.v:34.14-34.23" *)
output user_led7;
wire user_led7;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1686.11-1686.18" *)
reg [9:0] storage [3:0];
always @(posedge builder_clks[0]) begin
if (_002_[9])
storage[_000_] <= _001_;
end
assign _003_ = storage[main_basesoc_tx_cdc_graycounter1_q_next_binary[1:0]];
(* src = "build/terasic_deca/gateware/terasic_deca.v:1726.11-1726.20" *)
reg [9:0] storage_2 [15:0];
always @(posedge builder_clks[0]) begin
end
assign _036_ = storage_2[main_basesoc_uart_tx_fifo_consume];
assign _004_ = main_basesoc_uart_tx_fifo_consume + (* src = "build/terasic_deca/gateware/terasic_deca.v:1379.41-1379.81" *) 1'h1;
assign _005_ = main_basesoc_uart_rx_fifo_level0 + (* src = "build/terasic_deca/gateware/terasic_deca.v:1405.41-1405.80" *) 1'h1;
assign _006_ = main_basesoc_tx_cdc_graycounter0_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:766.54-766.102" *) 1'h1;
assign _007_ = main_basesoc_tx_cdc_graycounter1_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:775.54-775.102" *) 1'h1;
assign _008_ = main_basesoc_rx_cdc_graycounter0_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:805.54-805.102" *) 1'h1;
assign _009_ = main_basesoc_rx_cdc_graycounter1_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:814.54-814.102" *) 1'h1;
assign _010_ = main_basesoc_count + (* src = "build/terasic_deca/gateware/terasic_deca.v:836.40-836.65" *) 1'h1;
assign main_basesoc_rx_cdc_graycounter1_ce = main_basesoc_rx_cdc_asyncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:1403.8-1403.91" *) main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_tx_cdc_graycounter0_ce = main_basesoc_tx_cdc_asyncfifo_writable & (* src = "build/terasic_deca/gateware/terasic_deca.v:754.47-754.120" *) main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_tx_cdc_graycounter1_ce = main_basesoc_tx_cdc_asyncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:755.47-755.120" *) main_basesoc_tx_cdc_asyncfifo_re;
assign main_basesoc_rx_cdc_graycounter0_ce = main_basesoc_rx_cdc_asyncfifo_writable & (* src = "build/terasic_deca/gateware/terasic_deca.v:793.47-793.120" *) main_basesoc_rx_cdc_asyncfifo_we;
assign main_basesoc_uart_tx_fifo_syncfifo_re = main_basesoc_uart_tx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:928.49-928.165" *) _043_;
assign main_basesoc_uart_tx_fifo_do_read = main_basesoc_uart_tx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:940.45-940.128" *) main_basesoc_uart_tx_fifo_syncfifo_re;
assign main_basesoc_uart_rx_fifo_syncfifo_re = main_basesoc_uart_rx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:958.49-958.165" *) _040_;
assign main_basesoc_uart_rx_fifo_do_read = main_basesoc_uart_rx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:970.45-970.128" *) main_basesoc_uart_rx_fifo_syncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (_027_) builder_resetinserter_state <= 2'h0;
else if (_024_) builder_resetinserter_state <= builder_resetinserter_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (jtag_rst) builder_max10jtag_state <= 4'h0;
else if (_025_) builder_max10jtag_state <= builder_max10jtag_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_rx_cdc_graycounter0_q_binary <= 3'h0;
else main_basesoc_rx_cdc_graycounter0_q_binary <= main_basesoc_rx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_rx_cdc_graycounter0_q <= 3'h0;
else main_basesoc_rx_cdc_graycounter0_q <= main_basesoc_rx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_tx_cdc_graycounter1_q_binary <= 3'h0;
else main_basesoc_tx_cdc_graycounter1_q_binary <= main_basesoc_tx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_tx_cdc_graycounter1_q <= 3'h0;
else main_basesoc_tx_cdc_graycounter1_q <= main_basesoc_tx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (_027_) main_basesoc_count <= 3'h0;
else if (main_basesoc_count_next_value_ce2) main_basesoc_count <= main_basesoc_count_next_value2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (_027_) main_basesoc_data <= 8'h00;
else if (main_basesoc_count_next_value_ce2) main_basesoc_data <= main_basesoc_data_next_value1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
if (_027_) main_basesoc_valid <= 1'h0;
else if (main_basesoc_valid_next_value_ce0) main_basesoc_valid <= main_basesoc_valid_next_value0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1333.1-1342.4" *)
always @(negedge jtag_clk)
if (jtag_rst) main_basesoc_jtag_tdouser <= 1'h0;
else main_basesoc_jtag_tdouser <= main_basesoc_jtag_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1333.1-1342.4" *)
always @(negedge jtag_clk)
if (jtag_rst) main_basesoc_jtag_capture <= 1'h0;
else main_basesoc_jtag_capture <= main_basesoc_jtag_is_ongoing3;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1333.1-1342.4" *)
always @(negedge jtag_clk)
if (jtag_rst) main_basesoc_jtag_reset <= 1'h0;
else main_basesoc_jtag_reset <= main_basesoc_jtag_is_ongoing0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1344.1-1603.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_rx_fifo_level0 <= 5'h00;
else if (_026_) main_basesoc_uart_rx_fifo_level0 <= _078_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1344.1-1603.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_rx_fifo_readable <= 1'h0;
else if (main_basesoc_uart_rx_fifo_syncfifo_re) main_basesoc_uart_rx_fifo_readable <= _079_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1344.1-1603.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_tx_fifo_consume <= 4'h0;
else if (main_basesoc_uart_tx_fifo_do_read) main_basesoc_uart_tx_fifo_consume <= _004_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1344.1-1603.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_tx_fifo_level0 <= 5'h00;
else if (main_basesoc_uart_tx_fifo_do_read) main_basesoc_uart_tx_fifo_level0 <= _092_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1344.1-1603.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_tx_fifo_readable <= 1'h0;
else if (_023_) main_basesoc_uart_tx_fifo_readable <= _081_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1734.1-1737.4" *)
always @(posedge builder_clks[0])
if (main_basesoc_uart_tx_fifo_do_read) storage_2_dat1 <= _036_;
assign _011_ = | { _045_, _044_, main_basesoc_jtag_shift };
assign _012_ = { _044_, main_basesoc_jtag_shift } != 2'h2;
assign _013_ = { _045_, main_basesoc_jtag_shift } != 2'h2;
assign _014_ = { _045_, _035_, main_basesoc_jtag_shift } != 3'h5;
assign _015_ = { _048_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _016_ = { _050_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _017_ = { _055_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _018_ = { _057_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _019_ = { _060_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _020_ = { _060_, _059_, _058_, _057_, _056_, _055_, _054_, _053_, _052_, _051_, _050_, _049_, _048_, _047_, _046_, main_basesoc_jtag_tmsutap } != 16'h0001;
assign _021_ = | { main_basesoc_rx_cdc_graycounter1_ce, main_basesoc_uart_rx_fifo_do_read };
assign _022_ = { main_basesoc_rx_cdc_graycounter1_ce, main_basesoc_uart_rx_fifo_do_read } != 2'h3;
assign _023_ = | { main_basesoc_uart_tx_fifo_syncfifo_re, main_basesoc_tx_cdc_asyncfifo_writable };
assign _024_ = & { _013_, _011_, _014_, _012_ };
assign _025_ = & { _017_, _018_, _019_, _020_, _015_, _016_ };
assign _026_ = & { _021_, _022_ };
assign _027_ = | { main_basesoc_fsm_reset, jtag_rst };
assign _029_ = | { _060_, _059_, _058_, _057_, _056_, _055_, _054_, _053_, _052_, _051_, _050_, _049_, _048_, _047_, _046_ };
assign _028_ = | { _045_, _044_ };
assign _030_ = | { _053_, _046_ };
assign _031_ = main_basesoc_tx_cdc_graycounter0_q[2] == (* src = "build/terasic_deca/gateware/terasic_deca.v:756.52-756.131" *) builder_multiregimpl1_regs1[2];
assign _032_ = main_basesoc_tx_cdc_graycounter0_q[1] == (* src = "build/terasic_deca/gateware/terasic_deca.v:756.136-756.215" *) builder_multiregimpl1_regs1[1];
assign _033_ = main_basesoc_rx_cdc_graycounter0_q[2] == (* src = "build/terasic_deca/gateware/terasic_deca.v:795.52-795.131" *) builder_multiregimpl3_regs1[2];
assign _034_ = main_basesoc_rx_cdc_graycounter0_q[1] == (* src = "build/terasic_deca/gateware/terasic_deca.v:795.136-795.215" *) builder_multiregimpl3_regs1[1];
assign _035_ = main_basesoc_count == (* src = "build/terasic_deca/gateware/terasic_deca.v:840.10-840.36" *) 3'h7;
assign _037_ = main_basesoc_tx_cdc_graycounter0_q[0] != (* src = "build/terasic_deca/gateware/terasic_deca.v:756.221-756.300" *) builder_multiregimpl1_regs1[0];
assign main_basesoc_tx_cdc_asyncfifo_readable = main_basesoc_tx_cdc_graycounter1_q != (* src = "build/terasic_deca/gateware/terasic_deca.v:757.50-757.123" *) builder_multiregimpl0_regs1;
assign _038_ = main_basesoc_rx_cdc_graycounter0_q[0] != (* src = "build/terasic_deca/gateware/terasic_deca.v:795.221-795.300" *) builder_multiregimpl3_regs1[0];
assign main_basesoc_rx_cdc_asyncfifo_readable = main_basesoc_rx_cdc_graycounter1_q != (* src = "build/terasic_deca/gateware/terasic_deca.v:796.50-796.123" *) builder_multiregimpl2_regs1;
assign main_basesoc_uart_tx_fifo_syncfifo_readable = | (* src = "build/terasic_deca/gateware/terasic_deca.v:945.55-945.95" *) main_basesoc_uart_tx_fifo_level0;
assign main_basesoc_rx_cdc_asyncfifo_re = main_basesoc_uart_rx_fifo_level0 != (* src = "build/terasic_deca/gateware/terasic_deca.v:974.55-974.96" *) 5'h10;
assign main_basesoc_uart_rx_fifo_syncfifo_readable = | (* src = "build/terasic_deca/gateware/terasic_deca.v:975.55-975.95" *) main_basesoc_uart_rx_fifo_level0;
assign _039_ = ~ (* src = "build/terasic_deca/gateware/terasic_deca.v:928.97-928.132" *) main_basesoc_uart_tx_fifo_readable;
assign _040_ = ~ (* src = "build/terasic_deca/gateware/terasic_deca.v:958.97-958.132" *) main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_fsm_reset = main_basesoc_jtag_reset | (* src = "build/terasic_deca/gateware/terasic_deca.v:562.34-562.85" *) main_basesoc_jtag_capture;
assign _041_ = _031_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:756.51-756.216" *) _032_;
assign main_basesoc_tx_cdc_asyncfifo_writable = _041_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:756.50-756.301" *) _037_;
assign _042_ = _033_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:795.51-795.216" *) _034_;
assign main_basesoc_rx_cdc_asyncfifo_writable = _042_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:795.50-795.301" *) _038_;
assign _043_ = _039_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:928.96-928.164" *) main_basesoc_tx_cdc_asyncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1694.1-1696.4" *)
always @(posedge jtag_clk)
storage_dat1 <= _003_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
main_basesoc_tx_cdc_graycounter0_q <= main_basesoc_tx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
main_basesoc_tx_cdc_graycounter0_q_binary <= main_basesoc_tx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
main_basesoc_rx_cdc_graycounter1_q <= main_basesoc_rx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
main_basesoc_rx_cdc_graycounter1_q_binary <= main_basesoc_rx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl1_regs0 <= main_basesoc_tx_cdc_graycounter1_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl1_regs1 <= builder_multiregimpl1_regs0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl2_regs0 <= main_basesoc_rx_cdc_graycounter0_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1605.1-1620.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl2_regs1 <= builder_multiregimpl2_regs0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
builder_multiregimpl0_regs0 <= main_basesoc_tx_cdc_graycounter0_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
builder_multiregimpl0_regs1 <= builder_multiregimpl0_regs0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
builder_multiregimpl3_regs0 <= main_basesoc_rx_cdc_graycounter1_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1294.1-1331.4" *)
always @(posedge jtag_clk)
builder_multiregimpl3_regs1 <= builder_multiregimpl3_regs0;
assign main_basesoc_valid_next_value0 = _028_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) 1'h0 : _091_;
assign _044_ = builder_resetinserter_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) 2'h2;
assign _045_ = builder_resetinserter_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) 2'h1;
assign main_basesoc_rx_cdc_graycounter1_q_next_binary = main_basesoc_rx_cdc_graycounter1_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:813.6-813.41|build/terasic_deca/gateware/terasic_deca.v:813.2-817.5" *) _009_ : main_basesoc_rx_cdc_graycounter1_q_binary;
assign main_basesoc_rx_cdc_graycounter0_q_next_binary = main_basesoc_rx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:804.6-804.41|build/terasic_deca/gateware/terasic_deca.v:804.2-808.5" *) _008_ : main_basesoc_rx_cdc_graycounter0_q_binary;
assign main_basesoc_tx_cdc_graycounter1_q_next_binary = main_basesoc_tx_cdc_graycounter1_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:774.6-774.41|build/terasic_deca/gateware/terasic_deca.v:774.2-778.5" *) _007_ : main_basesoc_tx_cdc_graycounter1_q_binary;
assign main_basesoc_tx_cdc_graycounter0_q_next_binary = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:765.6-765.41|build/terasic_deca/gateware/terasic_deca.v:765.2-769.5" *) _006_ : main_basesoc_tx_cdc_graycounter0_q_binary;
assign main_basesoc_jtag_is_ongoing0 = _029_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 1'h0 : 1'h1;
assign _046_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'hf;
assign _047_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'he;
assign _048_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'hd;
assign _049_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'hc;
assign _050_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'hb;
assign _051_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'ha;
assign _052_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h9;
assign _053_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h8;
assign _054_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h7;
assign _055_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h6;
assign _056_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h5;
assign _057_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h4;
assign _058_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h3;
assign _059_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h2;
assign _060_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 4'h1;
assign _061_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:735.8-735.32|build/terasic_deca/gateware/terasic_deca.v:735.4-737.7" *) 4'hx : 4'h1;
assign _062_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:726.8-726.29|build/terasic_deca/gateware/terasic_deca.v:726.4-730.7" *) 4'h2 : 4'h1;
function [3:0] _209_;
input [3:0] a;
input [55:0] b;
input [13:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *)
(* parallel_case *)
casez (s)
14'b?????????????1:
_209_ = b[3:0];
14'b????????????1?:
_209_ = b[7:4];
14'b???????????1??:
_209_ = b[11:8];
14'b??????????1???:
_209_ = b[15:12];
14'b?????????1????:
_209_ = b[19:16];
14'b????????1?????:
_209_ = b[23:20];
14'b???????1??????:
_209_ = b[27:24];
14'b??????1???????:
_209_ = b[31:28];
14'b?????1????????:
_209_ = b[35:32];
14'b????1?????????:
_209_ = b[39:36];
14'b???1??????????:
_209_ = b[43:40];
14'b??1???????????:
_209_ = b[47:44];
14'b?1????????????:
_209_ = b[51:48];
14'b1?????????????:
_209_ = b[55:52];
default:
_209_ = a;
endcase
endfunction
assign builder_max10jtag_next_state = _209_(_061_, { _075_, _074_, _073_, _072_, _071_, _070_, _069_, _068_, _067_, _066_, _065_, _064_, _063_, _062_ }, { _060_, _059_, _058_, _057_, _056_, _055_, _054_, _052_, _051_, _050_, _049_, _048_, _047_, _030_ });
assign _063_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:717.8-717.29|build/terasic_deca/gateware/terasic_deca.v:717.4-721.7" *) 4'hf : 4'hb;
assign _064_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:710.8-710.29|build/terasic_deca/gateware/terasic_deca.v:710.4-712.7" *) 4'he : 4'hx;
assign _065_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:701.8-701.32|build/terasic_deca/gateware/terasic_deca.v:701.4-705.7" *) 4'hf : 4'hd;
assign _066_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:694.8-694.29|build/terasic_deca/gateware/terasic_deca.v:694.4-696.7" *) 4'hc : 4'hx;
assign _067_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:685.8-685.32|build/terasic_deca/gateware/terasic_deca.v:685.4-689.7" *) 4'hc : 4'hb;
assign _068_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:676.8-676.32|build/terasic_deca/gateware/terasic_deca.v:676.4-680.7" *) 4'h0 : 4'ha;
assign _069_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:658.8-658.29|build/terasic_deca/gateware/terasic_deca.v:658.4-662.7" *) 4'h8 : 4'h4;
assign _070_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:651.8-651.29|build/terasic_deca/gateware/terasic_deca.v:651.4-653.7" *) 4'h7 : 4'hx;
assign _071_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:642.8-642.32|build/terasic_deca/gateware/terasic_deca.v:642.4-646.7" *) 4'h8 : 4'h6;
assign _072_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:635.8-635.29|build/terasic_deca/gateware/terasic_deca.v:635.4-637.7" *) 4'h5 : 4'hx;
assign _073_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:626.8-626.32|build/terasic_deca/gateware/terasic_deca.v:626.4-630.7" *) 4'h5 : 4'h4;
assign _074_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:617.8-617.32|build/terasic_deca/gateware/terasic_deca.v:617.4-621.7" *) 4'h9 : 4'h3;
assign _075_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:610.8-610.29|build/terasic_deca/gateware/terasic_deca.v:610.4-612.7" *) 4'h2 : 4'hx;
assign main_basesoc_jtag_is_ongoing3 = _058_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:608.2-740.9" *) 1'h1 : 1'h0;
assign _002_[9] = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1690.6-1690.35|build/terasic_deca/gateware/terasic_deca.v:1690.2-1691.79" *) 1'h1 : 1'h0;
assign _001_ = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1690.6-1690.35|build/terasic_deca/gateware/terasic_deca.v:1690.2-1691.79" *) storage_2_dat1 : 10'hxxx;
assign _000_ = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1690.6-1690.35|build/terasic_deca/gateware/terasic_deca.v:1690.2-1691.79" *) main_basesoc_tx_cdc_graycounter0_q_binary[1:0] : 2'hx;
assign _076_ = main_basesoc_uart_rx_fifo_do_read ? (* src = "build/terasic_deca/gateware/terasic_deca.v:1408.7-1408.40|build/terasic_deca/gateware/terasic_deca.v:1408.3-1410.6" *) _093_ : 5'hxx;
assign _077_ = main_basesoc_uart_rx_fifo_do_read ? (* src = "build/terasic_deca/gateware/terasic_deca.v:1404.7-1404.43|build/terasic_deca/gateware/terasic_deca.v:1404.3-1406.6" *) 5'hxx : _005_;
assign _078_ = main_basesoc_rx_cdc_graycounter1_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1403.6-1403.132|build/terasic_deca/gateware/terasic_deca.v:1403.2-1411.5" *) _077_ : _076_;
assign _079_ = main_basesoc_uart_rx_fifo_syncfifo_re ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1390.6-1390.43|build/terasic_deca/gateware/terasic_deca.v:1390.2-1396.5" *) 1'h1 : 1'hx;
assign _080_ = main_basesoc_tx_cdc_asyncfifo_writable ? (* src = "build/terasic_deca/gateware/terasic_deca.v:1371.7-1371.35|build/terasic_deca/gateware/terasic_deca.v:1371.3-1373.6" *) 1'h0 : 1'hx;
assign _081_ = main_basesoc_uart_tx_fifo_syncfifo_re ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1368.6-1368.43|build/terasic_deca/gateware/terasic_deca.v:1368.2-1374.5" *) 1'h1 : _080_;
function [0:0] _233_;
input [0:0] a;
input [1:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *)
(* parallel_case *)
casez (s)
2'b?1:
_233_ = b[0:0];
2'b1?:
_233_ = b[1:1];
default:
_233_ = a;
endcase
endfunction
assign main_basesoc_jtag_tdo = _233_(main_basesoc_rx_cdc_asyncfifo_writable, { main_basesoc_data[0], main_basesoc_valid }, { _045_, _044_ });
assign _082_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:854.8-854.31|build/terasic_deca/gateware/terasic_deca.v:854.4-863.7" *) 2'h1 : 2'hx;
assign _083_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:847.8-847.31|build/terasic_deca/gateware/terasic_deca.v:847.4-850.7" *) 2'h0 : 2'hx;
function [1:0] _236_;
input [1:0] a;
input [3:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *)
(* parallel_case *)
casez (s)
2'b?1:
_236_ = b[1:0];
2'b1?:
_236_ = b[3:2];
default:
_236_ = a;
endcase
endfunction
assign builder_resetinserter_next_state = _236_(_082_, { _085_, _083_ }, { _045_, _044_ });
assign _084_ = _035_ ? (* src = "build/terasic_deca/gateware/terasic_deca.v:840.9-840.37|build/terasic_deca/gateware/terasic_deca.v:840.5-842.8" *) 2'h2 : 2'hx;
assign _085_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:835.8-835.31|build/terasic_deca/gateware/terasic_deca.v:835.4-843.7" *) _084_ : 2'hx;
assign _086_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:854.8-854.31|build/terasic_deca/gateware/terasic_deca.v:854.4-863.7" *) 1'h1 : 1'h0;
assign main_basesoc_count_next_value_ce2 = _044_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) 1'h0 : _086_;
assign _087_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:835.8-835.31|build/terasic_deca/gateware/terasic_deca.v:835.4-843.7" *) _010_ : 3'h0;
assign main_basesoc_count_next_value2 = _045_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) _087_ : 3'h0;
assign _088_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:847.8-847.31|build/terasic_deca/gateware/terasic_deca.v:847.4-850.7" *) main_basesoc_jtag_tdiutap : 1'h0;
assign main_basesoc_rx_cdc_asyncfifo_we = _044_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) _088_ : 1'h0;
assign _089_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:854.8-854.31|build/terasic_deca/gateware/terasic_deca.v:854.4-863.7" *) storage_dat1[7:0] : 8'h00;
function [7:0] _246_;
input [7:0] a;
input [15:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *)
(* parallel_case *)
casez (s)
2'b?1:
_246_ = b[7:0];
2'b1?:
_246_ = b[15:8];
default:
_246_ = a;
endcase
endfunction
assign main_basesoc_data_next_value1 = _246_(_089_, { _090_, 8'h00 }, { _045_, _044_ });
assign _090_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:835.8-835.31|build/terasic_deca/gateware/terasic_deca.v:835.4-843.7" *) { main_basesoc_jtag_tdiutap, main_basesoc_data[7:1] } : 8'h00;
assign main_basesoc_tx_cdc_asyncfifo_re = _028_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) 1'h0 : _088_;
assign main_basesoc_valid_next_value_ce0 = _028_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:832.2-865.9" *) 1'h0 : _086_;
assign _091_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:854.8-854.31|build/terasic_deca/gateware/terasic_deca.v:854.4-863.7" *) main_basesoc_tx_cdc_asyncfifo_readable : 1'h0;
assign _092_ = main_basesoc_uart_tx_fifo_level0 - (* src = "build/terasic_deca/gateware/terasic_deca.v:1387.41-1387.80" *) 1'h1;
assign _093_ = main_basesoc_uart_rx_fifo_level0 - (* src = "build/terasic_deca/gateware/terasic_deca.v:1409.41-1409.80" *) 1'h1;
assign main_basesoc_tx_cdc_graycounter0_q_next = main_basesoc_tx_cdc_graycounter0_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:771.51-771.151" *) main_basesoc_tx_cdc_graycounter0_q_next_binary[2:1];
assign main_basesoc_tx_cdc_graycounter1_q_next = main_basesoc_tx_cdc_graycounter1_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:780.51-780.151" *) main_basesoc_tx_cdc_graycounter1_q_next_binary[2:1];
assign main_basesoc_rx_cdc_graycounter0_q_next = main_basesoc_rx_cdc_graycounter0_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:810.51-810.151" *) main_basesoc_rx_cdc_graycounter0_q_next_binary[2:1];
assign main_basesoc_rx_cdc_graycounter1_q_next = main_basesoc_rx_cdc_graycounter1_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:819.51-819.151" *) main_basesoc_rx_cdc_graycounter1_q_next_binary[2:1];
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1776.3-1786.2" *)
ALTPLL #(
.BANDWIDTH_TYPE("AUTO"),
.CLK0_DIVIDE_BY(5'h19),
.CLK0_DUTY_CYCLE(6'h32),
.CLK0_MULTIPLY_BY(5'h19),
.CLK0_PHASE_SHIFT(1'h0),
.CLK1_DIVIDE_BY(5'h1f),
.CLK1_DUTY_CYCLE(6'h32),
.CLK1_MULTIPLY_BY(5'h19),
.CLK1_PHASE_SHIFT(1'h0),
.COMPENSATE_CLOCK("CLK0"),
.INCLK0_INPUT_FREQUENCY(15'h4e20),
.OPERATION_MODE("NORMAL")
) ALTPLL (
.ARESET(1'h0),
.CLK(builder_clks),
.CLKENA(5'h1f),
.EXTCLKENA(4'hf),
.FBIN(1'h1),
.INCLK(clk50),
.LOCKED(main_crg_locked),
.PFDENA(1'h1),
.PLLENA(1'h1)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1788.5-1794.2" *)
DFF DFF (
.clk(jtag_clk),
.clrn(1'h1),
.d(1'h0),
.prn(1'h1),
.q(builder_rst_meta0)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1796.5-1802.2" *)
DFF DFF_1 (
.clk(jtag_clk),
.clrn(1'h1),
.d(builder_rst_meta0),
.prn(1'h1),
.q(jtag_rst)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1804.5-1810.2" *)
DFF DFF_2 (
.clk(builder_clks[0]),
.clrn(1'h1),
.d(1'h0),
.prn(main_crg_locked),
.q(builder_rst_meta1)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1812.5-1818.2" *)
DFF DFF_3 (
.clk(builder_clks[0]),
.clrn(1'h1),
.d(builder_rst_meta1),
.prn(main_crg_locked),
.q(sys_rst)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1820.5-1826.2" *)
DFF DFF_4 (
.clk(builder_clks[1]),
.clrn(1'h1),
.d(1'h0),
.prn(main_crg_locked),
.q(builder_rst_meta2)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1828.5-1834.2" *)
DFF DFF_5 (
.clk(builder_clks[1]),
.clrn(1'h1),
.d(builder_rst_meta2),
.prn(main_crg_locked),
.q(hdmi_rst)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1665.18-1679.2" *)
fiftyfivenm_jtag fiftyfivenm_jtag (
.clkdruser(main_basesoc_jtag_drck),
.runidleuser(main_basesoc_jtag_runtest),
.shiftuser(main_basesoc_jtag_shift),
.tck(altera_reserved_tck),
.tckutap(jtag_clk),
.tdi(altera_reserved_tdi),
.tdiutap(main_basesoc_jtag_tdiutap),
.tdo(main_basesoc_jtag_altera_reserved_tdo),
.tdouser(main_basesoc_jtag_tdouser),
.tms(altera_reserved_tms),
.tmsutap(main_basesoc_jtag_tmsutap),
.updateuser(main_basesoc_jtag_update),
.usr1user(main_basesoc_jtag_sel)
);
assign _002_[8:0] = { _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9] };
assign altera_reserved_tdo = main_basesoc_jtag_altera_reserved_tdo;
assign builder_basesoc_adr = 14'h0000;
assign builder_basesoc_dat_w = 32'd0;
assign builder_basesoc_we = 1'h0;
assign builder_basesoc_wishbone_adr = 30'h00000000;
assign builder_basesoc_wishbone_cyc = 1'h0;
assign builder_basesoc_wishbone_dat_w = 32'd0;
assign builder_basesoc_wishbone_sel = 4'h0;
assign builder_basesoc_wishbone_stb = 1'h0;
assign builder_basesoc_wishbone_we = 1'h0;
assign builder_csr_bankarray_adr = 6'h00;
assign builder_csr_bankarray_csrbank0_bus_errors_r = 32'd0;
assign builder_csr_bankarray_csrbank0_bus_errors_re = 1'h0;
assign builder_csr_bankarray_csrbank0_bus_errors_we = 1'h0;
assign builder_csr_bankarray_csrbank0_reset0_r = 2'h0;
assign builder_csr_bankarray_csrbank0_reset0_re = 1'h0;
assign builder_csr_bankarray_csrbank0_reset0_we = 1'h1;
assign builder_csr_bankarray_csrbank0_scratch0_r = 32'd0;
assign builder_csr_bankarray_csrbank0_scratch0_re = 1'h0;
assign builder_csr_bankarray_csrbank0_scratch0_we = 1'h0;
assign builder_csr_bankarray_csrbank0_sel = 1'h1;
assign builder_csr_bankarray_csrbank1_en0_r = 1'h0;
assign builder_csr_bankarray_csrbank1_en0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_en0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_enable0_r = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_enable0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_enable0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_pending_r = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_pending_re = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_pending_we = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_status_r = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_status_re = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_status_we = 1'h0;
assign builder_csr_bankarray_csrbank1_load0_r = 32'd0;
assign builder_csr_bankarray_csrbank1_load0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_load0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_reload0_r = 32'd0;
assign builder_csr_bankarray_csrbank1_reload0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_reload0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_sel = 1'h0;
assign builder_csr_bankarray_csrbank1_update_value0_r = 1'h0;
assign builder_csr_bankarray_csrbank1_update_value0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_update_value0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_value_r = 32'd0;
assign builder_csr_bankarray_csrbank1_value_re = 1'h0;
assign builder_csr_bankarray_csrbank1_value_we = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_enable0_r = 2'h0;
assign builder_csr_bankarray_csrbank2_ev_enable0_re = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_enable0_we = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_pending_r = 2'h0;
assign builder_csr_bankarray_csrbank2_ev_pending_re = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_pending_we = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_status_r = 2'h0;
assign builder_csr_bankarray_csrbank2_ev_status_re = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_status_w[1] = main_basesoc_uart_rx_fifo_readable;
assign builder_csr_bankarray_csrbank2_ev_status_we = 1'h0;
assign builder_csr_bankarray_csrbank2_rxempty_r = 1'h0;
assign builder_csr_bankarray_csrbank2_rxempty_re = 1'h0;
assign builder_csr_bankarray_csrbank2_rxempty_we = 1'h0;
assign builder_csr_bankarray_csrbank2_rxfull_r = 1'h0;
assign builder_csr_bankarray_csrbank2_rxfull_re = 1'h0;
assign builder_csr_bankarray_csrbank2_rxfull_we = 1'h0;
assign builder_csr_bankarray_csrbank2_sel = 1'h0;
assign builder_csr_bankarray_csrbank2_txempty_r = 1'h0;
assign builder_csr_bankarray_csrbank2_txempty_re = 1'h0;
assign builder_csr_bankarray_csrbank2_txempty_we = 1'h0;
assign builder_csr_bankarray_csrbank2_txfull_r = 1'h0;
assign builder_csr_bankarray_csrbank2_txfull_re = 1'h0;
assign builder_csr_bankarray_csrbank2_txfull_we = 1'h0;
assign builder_csr_bankarray_interface0_bank_bus_adr = 14'h0000;
assign builder_csr_bankarray_interface0_bank_bus_dat_w = 32'd0;
assign builder_csr_bankarray_interface0_bank_bus_we = 1'h0;
assign builder_csr_bankarray_interface1_bank_bus_adr = 14'h0000;
assign builder_csr_bankarray_interface1_bank_bus_dat_w = 32'd0;
assign builder_csr_bankarray_interface1_bank_bus_we = 1'h0;
assign builder_csr_bankarray_interface2_bank_bus_adr = 14'h0000;
assign builder_csr_bankarray_interface2_bank_bus_dat_w = 32'd0;
assign builder_csr_bankarray_interface2_bank_bus_we = 1'h0;
assign builder_csr_bankarray_sel = 1'h0;
assign builder_csr_bankarray_sram_bus_adr = 14'h0000;
assign builder_csr_bankarray_sram_bus_dat_w = 32'd0;
assign builder_csr_bankarray_sram_bus_we = 1'h0;
assign builder_csr_interconnect_adr = 14'h0000;
assign builder_csr_interconnect_dat_w = 32'd0;
assign builder_csr_interconnect_we = 1'h0;
assign builder_slice_proxy0[0] = gpio[0];
assign builder_slice_proxy1[1] = gpio[1];
assign builder_slice_proxy2[2] = gpio[2];
assign builder_slice_proxy3[3] = gpio[3];
assign builder_slice_proxy4[4] = gpio[4];
assign builder_slice_proxy5[5] = gpio[5];
assign builder_slice_proxy6[6] = gpio[6];
assign builder_slice_proxy7 = { gpio[7], user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0 };
assign hdmi_clk = builder_clks[1];
assign jtag_inv_rst = jtag_rst;
assign main_basesoc_adr = 11'h000;
assign main_basesoc_bus_error = 1'h0;
assign main_basesoc_bus_errors_we = 1'h0;
assign main_basesoc_dat_w = 32'd0;
assign main_basesoc_data_next_value_ce1 = main_basesoc_count_next_value_ce2;
assign main_basesoc_jtag_CAPTURE_DR = main_basesoc_jtag_is_ongoing3;
assign main_basesoc_jtag_TEST_LOGIC_RESET = main_basesoc_jtag_is_ongoing0;
assign main_basesoc_jtag_altera_reserved_tck = altera_reserved_tck;
assign main_basesoc_jtag_altera_reserved_tdi = altera_reserved_tdi;
assign main_basesoc_jtag_altera_reserved_tms = altera_reserved_tms;
assign main_basesoc_jtag_tck = jtag_clk;
assign main_basesoc_jtag_tckutap = jtag_clk;
assign main_basesoc_jtag_tdi = main_basesoc_jtag_tdiutap;
assign main_basesoc_jtag_tms = main_basesoc_jtag_tmsutap;
assign main_basesoc_ram_bus_adr = 30'h00000000;
assign main_basesoc_ram_bus_cyc = 1'h0;
assign main_basesoc_ram_bus_dat_w = 32'd0;
assign main_basesoc_ram_bus_sel = 4'h0;
assign main_basesoc_ram_bus_stb = 1'h0;
assign main_basesoc_ram_bus_we = 1'h0;
assign main_basesoc_rx_cdc_asyncfifo_din = { 2'h0, main_basesoc_data };
assign main_basesoc_rx_cdc_consume_wdomain = builder_multiregimpl3_regs1;
assign main_basesoc_rx_cdc_fifo_in_first = 1'h0;
assign main_basesoc_rx_cdc_fifo_in_last = 1'h0;
assign main_basesoc_rx_cdc_fifo_in_payload_data = main_basesoc_data;
assign main_basesoc_rx_cdc_produce_rdomain = builder_multiregimpl2_regs1;
assign main_basesoc_rx_cdc_rdport_adr = main_basesoc_rx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_rx_cdc_sink_first = 1'h0;
assign main_basesoc_rx_cdc_sink_last = 1'h0;
assign main_basesoc_rx_cdc_sink_payload_data = main_basesoc_data;
assign main_basesoc_rx_cdc_sink_ready = main_basesoc_rx_cdc_asyncfifo_writable;
assign main_basesoc_rx_cdc_sink_valid = main_basesoc_rx_cdc_asyncfifo_we;
assign main_basesoc_rx_cdc_source_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_rx_cdc_source_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_rx_cdc_wrport_adr = main_basesoc_rx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_rx_cdc_wrport_dat_w = { 2'h0, main_basesoc_data };
assign main_basesoc_rx_cdc_wrport_we = main_basesoc_rx_cdc_graycounter0_ce;
assign main_basesoc_sink_sink_first = storage_2_dat1[8];
assign main_basesoc_sink_sink_last = storage_2_dat1[9];
assign main_basesoc_sink_sink_payload_data = storage_2_dat1[7:0];
assign main_basesoc_sink_sink_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_sink_sink_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_source_source_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_source_source_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_timer_pending_we = 1'h0;
assign main_basesoc_timer_status_we = 1'h0;
assign main_basesoc_timer_value_we = 1'h0;
assign main_basesoc_tx_cdc_asyncfifo_din = storage_2_dat1;
assign main_basesoc_tx_cdc_asyncfifo_dout = storage_dat1;
assign main_basesoc_tx_cdc_asyncfifo_we = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_tx_cdc_consume_wdomain = builder_multiregimpl1_regs1;
assign main_basesoc_tx_cdc_fifo_in_first = storage_2_dat1[8];
assign main_basesoc_tx_cdc_fifo_in_last = storage_2_dat1[9];
assign main_basesoc_tx_cdc_fifo_in_payload_data = storage_2_dat1[7:0];
assign main_basesoc_tx_cdc_fifo_out_first = storage_dat1[8];
assign main_basesoc_tx_cdc_fifo_out_last = storage_dat1[9];
assign main_basesoc_tx_cdc_fifo_out_payload_data = storage_dat1[7:0];
assign main_basesoc_tx_cdc_produce_rdomain = builder_multiregimpl0_regs1;
assign main_basesoc_tx_cdc_rdport_adr = main_basesoc_tx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_tx_cdc_rdport_dat_r = storage_dat1;
assign main_basesoc_tx_cdc_sink_first = storage_2_dat1[8];
assign main_basesoc_tx_cdc_sink_last = storage_2_dat1[9];
assign main_basesoc_tx_cdc_sink_payload_data = storage_2_dat1[7:0];
assign main_basesoc_tx_cdc_sink_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_tx_cdc_sink_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_tx_cdc_source_first = storage_dat1[8];
assign main_basesoc_tx_cdc_source_last = storage_dat1[9];
assign main_basesoc_tx_cdc_source_payload_data = storage_dat1[7:0];
assign main_basesoc_tx_cdc_source_ready = main_basesoc_tx_cdc_asyncfifo_re;
assign main_basesoc_tx_cdc_source_valid = main_basesoc_tx_cdc_asyncfifo_readable;
assign main_basesoc_tx_cdc_wrport_adr = main_basesoc_tx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_tx_cdc_wrport_dat_w = storage_2_dat1;
assign main_basesoc_tx_cdc_wrport_we = main_basesoc_tx_cdc_graycounter0_ce;
assign main_basesoc_uart_pending_r = 2'h0;
assign main_basesoc_uart_pending_re = 1'h0;
assign main_basesoc_uart_pending_we = 1'h0;
assign main_basesoc_uart_rx0 = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_clear = 1'h0;
assign main_basesoc_uart_rx_fifo_rdport_re = main_basesoc_uart_rx_fifo_do_read;
assign main_basesoc_uart_rx_fifo_re = 1'h0;
assign main_basesoc_uart_rx_fifo_replace = 1'h0;
assign main_basesoc_uart_rx_fifo_sink_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_uart_rx_fifo_sink_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_uart_rx_fifo_source_ready = 1'h0;
assign main_basesoc_uart_rx_fifo_source_valid = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_fifo_syncfifo_we = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_uart_rx_fifo_syncfifo_writable = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_uart_rx_status = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_trigger = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rxempty_we = 1'h0;
assign main_basesoc_uart_rxfull_we = 1'h0;
assign main_basesoc_uart_rxtx_r = 8'h00;
assign main_basesoc_uart_rxtx_re = 1'h0;
assign main_basesoc_uart_rxtx_we = 1'h0;
assign main_basesoc_uart_status_status = { main_basesoc_uart_rx_fifo_readable, builder_csr_bankarray_csrbank2_ev_status_w[0] };
assign main_basesoc_uart_status_we = 1'h0;
assign main_basesoc_uart_tx0 = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_fifo_fifo_in_first = 1'h0;
assign main_basesoc_uart_tx_fifo_fifo_in_last = 1'h0;
assign main_basesoc_uart_tx_fifo_fifo_in_payload_data = 8'h00;
assign main_basesoc_uart_tx_fifo_fifo_out_first = storage_2_dat1[8];
assign main_basesoc_uart_tx_fifo_fifo_out_last = storage_2_dat1[9];
assign main_basesoc_uart_tx_fifo_fifo_out_payload_data = storage_2_dat1[7:0];
assign main_basesoc_uart_tx_fifo_rdport_adr = main_basesoc_uart_tx_fifo_consume;
assign main_basesoc_uart_tx_fifo_rdport_dat_r = storage_2_dat1;
assign main_basesoc_uart_tx_fifo_rdport_re = main_basesoc_uart_tx_fifo_do_read;
assign main_basesoc_uart_tx_fifo_re = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_uart_tx_fifo_replace = 1'h0;
assign main_basesoc_uart_tx_fifo_sink_first = 1'h0;
assign main_basesoc_uart_tx_fifo_sink_last = 1'h0;
assign main_basesoc_uart_tx_fifo_sink_payload_data = 8'h00;
assign main_basesoc_uart_tx_fifo_sink_ready = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_fifo_sink_valid = 1'h0;
assign main_basesoc_uart_tx_fifo_source_first = storage_2_dat1[8];
assign main_basesoc_uart_tx_fifo_source_last = storage_2_dat1[9];
assign main_basesoc_uart_tx_fifo_source_payload_data = storage_2_dat1[7:0];
assign main_basesoc_uart_tx_fifo_source_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_uart_tx_fifo_source_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_uart_tx_fifo_syncfifo_din = 10'h000;
assign main_basesoc_uart_tx_fifo_syncfifo_dout = storage_2_dat1;
assign main_basesoc_uart_tx_fifo_syncfifo_we = 1'h0;
assign main_basesoc_uart_tx_fifo_syncfifo_writable = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_fifo_wrport_dat_w = 10'h000;
assign main_basesoc_uart_tx_fifo_wrport_we = 1'h0;
assign main_basesoc_uart_tx_status = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_trigger = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_txempty_we = 1'h0;
assign main_basesoc_uart_txfull_we = 1'h0;
assign main_basesoc_uart_uart_sink_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_uart_uart_sink_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_uart_uart_source_first = storage_2_dat1[8];
assign main_basesoc_uart_uart_source_last = storage_2_dat1[9];
assign main_basesoc_uart_uart_source_payload_data = storage_2_dat1[7:0];
assign main_basesoc_uart_uart_source_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_uart_uart_source_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_we = 4'h0;
assign main_crg_clkin = clk50;
assign main_crg_clkout0 = builder_clks[0];
assign main_crg_clkout1 = builder_clks[1];
assign sys_clk = builder_clks[0];
assign sys_jtag_clk = builder_clks[0];
assign sys_jtag_rst = 1'h0;
assign user_led7 = gpio[7];
endmodule
Raw
opt.tcl
#!/usr/bin/env yosys
yosys read_verilog build/terasic_deca/gateware/terasic_deca.v
yosys proc
yosys opt_clean
yosys opt
yosys write_verilog opt.v
Raw
opt_request_loop.v
/* Generated by Yosys 0.13+39 (git sha1 9c9366895, clang 10.0.0-4ubuntu1 -fPIC -Os) */
(* cells_not_processed = 1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:20.1-1810.10" *)
module terasic_deca(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_tdo, clk50, gpio, user_led, user_led_1, user_led_2, user_led_3, user_led_4, user_led_5, user_led_6, user_led_7);
(* src = "build/terasic_deca/gateware/terasic_deca.v:1663.1-1667.4" *)
wire [1:0] _000_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1663.1-1667.4" *)
wire [9:0] _001_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1663.1-1667.4" *)
wire [9:0] _002_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1668.1-1670.4" *)
wire [9:0] _003_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1353.41-1353.81" *)
wire [3:0] _004_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1379.41-1379.80" *)
wire [4:0] _005_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:758.54-758.102" *)
wire [2:0] _006_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:767.54-767.102" *)
wire [2:0] _007_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:797.54-797.102" *)
wire [2:0] _008_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:806.54-806.102" *)
wire [2:0] _009_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:828.40-828.65" *)
wire [2:0] _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:748.52-748.131" *)
wire _031_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:748.136-748.215" *)
wire _032_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:787.52-787.131" *)
wire _033_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:787.136-787.215" *)
wire _034_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:832.10-832.36" *)
wire _035_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1710.21-1710.30" *)
wire [9:0] _036_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:748.221-748.300" *)
wire _037_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:787.221-787.300" *)
wire _038_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:920.97-920.132" *)
wire _039_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:950.97-950.132" *)
wire _040_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:748.51-748.216" *)
wire _041_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:787.51-787.216" *)
wire _042_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:920.96-920.164" *)
wire _043_;
wire [7:0] _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire [3:0] _061_;
wire [3:0] _062_;
wire [3:0] _063_;
wire [3:0] _064_;
wire [3:0] _065_;
wire [3:0] _066_;
wire [3:0] _067_;
wire [3:0] _068_;
wire [3:0] _069_;
wire [3:0] _070_;
wire [3:0] _071_;
wire [3:0] _072_;
wire [3:0] _073_;
wire [3:0] _074_;
wire [3:0] _075_;
wire [4:0] _076_;
wire [4:0] _077_;
wire [4:0] _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire [1:0] _083_;
wire [1:0] _084_;
wire [1:0] _085_;
wire [1:0] _086_;
wire _087_;
wire _088_;
wire _089_;
wire [2:0] _090_;
wire [7:0] _091_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1361.41-1361.80" *)
wire [4:0] _092_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1383.41-1383.80" *)
wire [4:0] _093_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:22.14-22.33" *)
input altera_reserved_tck;
wire altera_reserved_tck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:23.14-23.33" *)
input altera_reserved_tdi;
wire altera_reserved_tdi;
(* src = "build/terasic_deca/gateware/terasic_deca.v:24.14-24.33" *)
output altera_reserved_tdo;
wire altera_reserved_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:21.14-21.33" *)
input altera_reserved_tms;
wire altera_reserved_tms;
(* src = "build/terasic_deca/gateware/terasic_deca.v:393.13-393.32" *)
wire [13:0] builder_basesoc_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:395.13-395.34" *)
wire [31:0] builder_basesoc_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:394.6-394.24" *)
wire builder_basesoc_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:397.13-397.41" *)
wire [29:0] builder_basesoc_wishbone_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:401.6-401.34" *)
wire builder_basesoc_wishbone_cyc;
(* src = "build/terasic_deca/gateware/terasic_deca.v:398.13-398.43" *)
wire [31:0] builder_basesoc_wishbone_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:400.12-400.40" *)
wire [3:0] builder_basesoc_wishbone_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:402.6-402.34" *)
wire builder_basesoc_wishbone_stb;
(* src = "build/terasic_deca/gateware/terasic_deca.v:404.6-404.33" *)
wire builder_basesoc_wishbone_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:392.12-392.24" *)
wire [1:0] builder_clks;
(* src = "build/terasic_deca/gateware/terasic_deca.v:426.12-426.37" *)
wire [5:0] builder_csr_bankarray_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:418.13-418.56" *)
wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:417.6-417.50" *)
wire builder_csr_bankarray_csrbank0_bus_errors_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:419.6-419.50" *)
wire builder_csr_bankarray_csrbank0_bus_errors_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:410.12-410.51" *)
wire [1:0] builder_csr_bankarray_csrbank0_reset0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:409.6-409.46" *)
wire builder_csr_bankarray_csrbank0_reset0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:411.6-411.46" *)
wire builder_csr_bankarray_csrbank0_reset0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:414.13-414.54" *)
wire [31:0] builder_csr_bankarray_csrbank0_scratch0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:413.6-413.48" *)
wire builder_csr_bankarray_csrbank0_scratch0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:415.6-415.48" *)
wire builder_csr_bankarray_csrbank0_scratch0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:421.6-421.40" *)
wire builder_csr_bankarray_csrbank0_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:443.6-443.42" *)
wire builder_csr_bankarray_csrbank1_en0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:442.6-442.43" *)
wire builder_csr_bankarray_csrbank1_en0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:444.6-444.43" *)
wire builder_csr_bankarray_csrbank1_en0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:463.6-463.49" *)
wire builder_csr_bankarray_csrbank1_ev_enable0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:462.6-462.50" *)
wire builder_csr_bankarray_csrbank1_ev_enable0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:464.6-464.50" *)
wire builder_csr_bankarray_csrbank1_ev_enable0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:459.6-459.49" *)
wire builder_csr_bankarray_csrbank1_ev_pending_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:458.6-458.50" *)
wire builder_csr_bankarray_csrbank1_ev_pending_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:460.6-460.50" *)
wire builder_csr_bankarray_csrbank1_ev_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:455.6-455.48" *)
wire builder_csr_bankarray_csrbank1_ev_status_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:454.6-454.49" *)
wire builder_csr_bankarray_csrbank1_ev_status_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:456.6-456.49" *)
wire builder_csr_bankarray_csrbank1_ev_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:435.13-435.51" *)
wire [31:0] builder_csr_bankarray_csrbank1_load0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:434.6-434.45" *)
wire builder_csr_bankarray_csrbank1_load0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:436.6-436.45" *)
wire builder_csr_bankarray_csrbank1_load0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:439.13-439.53" *)
wire [31:0] builder_csr_bankarray_csrbank1_reload0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:438.6-438.47" *)
wire builder_csr_bankarray_csrbank1_reload0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:440.6-440.47" *)
wire builder_csr_bankarray_csrbank1_reload0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:466.6-466.40" *)
wire builder_csr_bankarray_csrbank1_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:447.6-447.52" *)
wire builder_csr_bankarray_csrbank1_update_value0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:446.6-446.53" *)
wire builder_csr_bankarray_csrbank1_update_value0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:448.6-448.53" *)
wire builder_csr_bankarray_csrbank1_update_value0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:451.13-451.51" *)
wire [31:0] builder_csr_bankarray_csrbank1_value_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:450.6-450.45" *)
wire builder_csr_bankarray_csrbank1_value_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:452.6-452.45" *)
wire builder_csr_bankarray_csrbank1_value_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:488.12-488.55" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_enable0_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:487.6-487.50" *)
wire builder_csr_bankarray_csrbank2_ev_enable0_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:489.6-489.50" *)
wire builder_csr_bankarray_csrbank2_ev_enable0_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:484.12-484.55" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_pending_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:483.6-483.50" *)
wire builder_csr_bankarray_csrbank2_ev_pending_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:485.6-485.50" *)
wire builder_csr_bankarray_csrbank2_ev_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:480.12-480.54" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:479.6-479.49" *)
wire builder_csr_bankarray_csrbank2_ev_status_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:482.12-482.54" *)
(* unused_bits = "0" *)
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:481.6-481.49" *)
wire builder_csr_bankarray_csrbank2_ev_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:476.6-476.46" *)
wire builder_csr_bankarray_csrbank2_rxempty_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:475.6-475.47" *)
wire builder_csr_bankarray_csrbank2_rxempty_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:477.6-477.47" *)
wire builder_csr_bankarray_csrbank2_rxempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:496.6-496.45" *)
wire builder_csr_bankarray_csrbank2_rxfull_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:495.6-495.46" *)
wire builder_csr_bankarray_csrbank2_rxfull_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:497.6-497.46" *)
wire builder_csr_bankarray_csrbank2_rxfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:499.6-499.40" *)
wire builder_csr_bankarray_csrbank2_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:492.6-492.46" *)
wire builder_csr_bankarray_csrbank2_txempty_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:491.6-491.47" *)
wire builder_csr_bankarray_csrbank2_txempty_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:493.6-493.47" *)
wire builder_csr_bankarray_csrbank2_txempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:472.6-472.45" *)
wire builder_csr_bankarray_csrbank2_txfull_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:471.6-471.46" *)
wire builder_csr_bankarray_csrbank2_txfull_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:473.6-473.46" *)
wire builder_csr_bankarray_csrbank2_txfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:405.13-405.58" *)
wire [13:0] builder_csr_bankarray_interface0_bank_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:407.13-407.60" *)
wire [31:0] builder_csr_bankarray_interface0_bank_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:406.6-406.50" *)
wire builder_csr_bankarray_interface0_bank_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:430.13-430.58" *)
wire [13:0] builder_csr_bankarray_interface1_bank_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:432.13-432.60" *)
wire [31:0] builder_csr_bankarray_interface1_bank_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:431.6-431.50" *)
wire builder_csr_bankarray_interface1_bank_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:467.13-467.58" *)
wire [13:0] builder_csr_bankarray_interface2_bank_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:469.13-469.60" *)
wire [31:0] builder_csr_bankarray_interface2_bank_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:468.6-468.50" *)
wire builder_csr_bankarray_interface2_bank_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:428.6-428.31" *)
wire builder_csr_bankarray_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:422.13-422.47" *)
wire [13:0] builder_csr_bankarray_sram_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:424.13-424.49" *)
wire [31:0] builder_csr_bankarray_sram_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:423.6-423.39" *)
wire builder_csr_bankarray_sram_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:500.13-500.41" *)
wire [13:0] builder_csr_interconnect_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:502.13-502.43" *)
wire [31:0] builder_csr_interconnect_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:501.6-501.33" *)
wire builder_csr_interconnect_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:383.12-383.40" *)
wire [3:0] builder_max10jtag_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:382.12-382.35" *)
reg [3:0] builder_max10jtag_state = 4'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:507.12-507.39" *)
reg [2:0] builder_multiregimpl0_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:508.12-508.39" *)
reg [2:0] builder_multiregimpl0_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:509.12-509.39" *)
reg [2:0] builder_multiregimpl1_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:510.12-510.39" *)
reg [2:0] builder_multiregimpl1_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:511.12-511.39" *)
reg [2:0] builder_multiregimpl2_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:512.12-512.39" *)
reg [2:0] builder_multiregimpl2_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:513.12-513.39" *)
reg [2:0] builder_multiregimpl3_regs0 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:514.12-514.39" *)
reg [2:0] builder_multiregimpl3_regs1 = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:385.12-385.44" *)
wire [1:0] builder_resetinserter_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:384.12-384.39" *)
reg [1:0] builder_resetinserter_state = 2'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:506.6-506.23" *)
wire builder_rst_meta0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:515.6-515.23" *)
wire builder_rst_meta1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:516.6-516.23" *)
wire builder_rst_meta2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:25.14-25.19" *)
input clk50;
wire clk50;
(* src = "build/terasic_deca/gateware/terasic_deca.v:26.21-26.25" *)
input [43:0] gpio;
wire [43:0] gpio;
(* src = "build/terasic_deca/gateware/terasic_deca.v:375.6-375.14" *)
wire hdmi_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:376.6-376.14" *)
wire hdmi_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:133.6-133.14" *)
wire jtag_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:100.6-100.18" *)
wire jtag_inv_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:134.6-134.14" *)
wire jtag_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:61.13-61.29" *)
wire [10:0] main_basesoc_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:51.6-51.28" *)
wire main_basesoc_bus_error;
(* src = "build/terasic_deca/gateware/terasic_deca.v:49.6-49.32" *)
wire main_basesoc_bus_errors_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:79.12-79.30" *)
reg [2:0] main_basesoc_count = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:390.12-390.42" *)
wire [2:0] main_basesoc_count_next_value2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:391.6-391.39" *)
wire main_basesoc_count_next_value_ce2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:64.13-64.31" *)
wire [31:0] main_basesoc_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:78.12-78.29" *)
reg [7:0] main_basesoc_data = 8'h00;
(* src = "build/terasic_deca/gateware/terasic_deca.v:388.12-388.41" *)
wire [7:0] main_basesoc_data_next_value1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:389.6-389.38" *)
wire main_basesoc_data_next_value_ce1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:215.6-215.28" *)
wire main_basesoc_fsm_reset;
(* src = "build/terasic_deca/gateware/terasic_deca.v:108.6-108.34" *)
wire main_basesoc_jtag_CAPTURE_DR;
(* src = "build/terasic_deca/gateware/terasic_deca.v:102.6-102.40" *)
wire main_basesoc_jtag_TEST_LOGIC_RESET;
(* src = "build/terasic_deca/gateware/terasic_deca.v:91.6-91.43" *)
wire main_basesoc_jtag_altera_reserved_tck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:93.6-93.43" *)
wire main_basesoc_jtag_altera_reserved_tdi;
(* src = "build/terasic_deca/gateware/terasic_deca.v:94.6-94.43" *)
wire main_basesoc_jtag_altera_reserved_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:92.6-92.43" *)
wire main_basesoc_jtag_altera_reserved_tms;
(* src = "build/terasic_deca/gateware/terasic_deca.v:81.6-81.31" *)
reg main_basesoc_jtag_capture = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:85.6-85.28" *)
wire main_basesoc_jtag_drck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:101.6-101.35" *)
wire main_basesoc_jtag_is_ongoing0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:107.6-107.35" *)
wire main_basesoc_jtag_is_ongoing3;
(* src = "build/terasic_deca/gateware/terasic_deca.v:80.6-80.29" *)
reg main_basesoc_jtag_reset = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:84.6-84.31" *)
wire main_basesoc_jtag_runtest;
(* src = "build/terasic_deca/gateware/terasic_deca.v:86.6-86.27" *)
wire main_basesoc_jtag_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:82.6-82.29" *)
wire main_basesoc_jtag_shift;
(* src = "build/terasic_deca/gateware/terasic_deca.v:87.6-87.27" *)
wire main_basesoc_jtag_tck;
(* src = "build/terasic_deca/gateware/terasic_deca.v:97.6-97.31" *)
wire main_basesoc_jtag_tckutap;
(* src = "build/terasic_deca/gateware/terasic_deca.v:89.6-89.27" *)
wire main_basesoc_jtag_tdi;
(* src = "build/terasic_deca/gateware/terasic_deca.v:98.6-98.31" *)
wire main_basesoc_jtag_tdiutap;
(* src = "build/terasic_deca/gateware/terasic_deca.v:90.6-90.27" *)
wire main_basesoc_jtag_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:95.6-95.31" *)
reg main_basesoc_jtag_tdouser = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:88.6-88.27" *)
wire main_basesoc_jtag_tms;
(* src = "build/terasic_deca/gateware/terasic_deca.v:96.6-96.31" *)
wire main_basesoc_jtag_tmsutap;
(* src = "build/terasic_deca/gateware/terasic_deca.v:83.6-83.30" *)
wire main_basesoc_jtag_update;
(* src = "build/terasic_deca/gateware/terasic_deca.v:53.13-53.37" *)
wire [29:0] main_basesoc_ram_bus_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:57.6-57.30" *)
wire main_basesoc_ram_bus_cyc;
(* src = "build/terasic_deca/gateware/terasic_deca.v:54.13-54.39" *)
wire [31:0] main_basesoc_ram_bus_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:56.12-56.36" *)
wire [3:0] main_basesoc_ram_bus_sel;
(* src = "build/terasic_deca/gateware/terasic_deca.v:58.6-58.30" *)
wire main_basesoc_ram_bus_stb;
(* src = "build/terasic_deca/gateware/terasic_deca.v:60.6-60.29" *)
wire main_basesoc_ram_bus_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:189.12-189.45" *)
wire [9:0] main_basesoc_rx_cdc_asyncfifo_din;
(* src = "build/terasic_deca/gateware/terasic_deca.v:187.6-187.38" *)
wire main_basesoc_rx_cdc_asyncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:188.6-188.44" *)
wire main_basesoc_rx_cdc_asyncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:185.6-185.38" *)
wire main_basesoc_rx_cdc_asyncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:186.6-186.44" *)
wire main_basesoc_rx_cdc_asyncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:202.12-202.47" *)
wire [2:0] main_basesoc_rx_cdc_consume_wdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:210.6-210.39" *)
wire main_basesoc_rx_cdc_fifo_in_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:211.6-211.38" *)
wire main_basesoc_rx_cdc_fifo_in_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:209.12-209.52" *)
wire [7:0] main_basesoc_rx_cdc_fifo_in_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:191.6-191.41" *)
wire main_basesoc_rx_cdc_graycounter0_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:192.12-192.46" *)
reg [2:0] main_basesoc_rx_cdc_graycounter0_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:194.12-194.53" *)
reg [2:0] main_basesoc_rx_cdc_graycounter0_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:193.12-193.51" *)
wire [2:0] main_basesoc_rx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:195.12-195.58" *)
wire [2:0] main_basesoc_rx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:196.6-196.41" *)
wire main_basesoc_rx_cdc_graycounter1_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:197.12-197.46" *)
reg [2:0] main_basesoc_rx_cdc_graycounter1_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:199.12-199.53" *)
reg [2:0] main_basesoc_rx_cdc_graycounter1_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:198.12-198.51" *)
wire [2:0] main_basesoc_rx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:200.12-200.58" *)
wire [2:0] main_basesoc_rx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:201.12-201.47" *)
wire [2:0] main_basesoc_rx_cdc_produce_rdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:207.12-207.42" *)
wire [1:0] main_basesoc_rx_cdc_rdport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:177.6-177.36" *)
wire main_basesoc_rx_cdc_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:178.6-178.35" *)
wire main_basesoc_rx_cdc_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:179.12-179.49" *)
wire [7:0] main_basesoc_rx_cdc_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:176.6-176.36" *)
wire main_basesoc_rx_cdc_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:175.6-175.36" *)
wire main_basesoc_rx_cdc_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:181.6-181.38" *)
wire main_basesoc_rx_cdc_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:180.6-180.38" *)
wire main_basesoc_rx_cdc_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:203.12-203.42" *)
wire [1:0] main_basesoc_rx_cdc_wrport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:206.12-206.44" *)
wire [9:0] main_basesoc_rx_cdc_wrport_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:205.6-205.35" *)
wire main_basesoc_rx_cdc_wrport_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:69.6-69.34" *)
wire main_basesoc_sink_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:70.6-70.33" *)
wire main_basesoc_sink_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:71.12-71.47" *)
wire [7:0] main_basesoc_sink_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:68.6-68.34" *)
wire main_basesoc_sink_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:67.6-67.34" *)
wire main_basesoc_sink_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:73.6-73.38" *)
wire main_basesoc_source_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:72.6-72.38" *)
wire main_basesoc_source_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:365.6-365.35" *)
wire main_basesoc_timer_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:361.6-361.34" *)
wire main_basesoc_timer_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:351.6-351.33" *)
wire main_basesoc_timer_value_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:149.12-149.45" *)
wire [9:0] main_basesoc_tx_cdc_asyncfifo_din;
(* src = "build/terasic_deca/gateware/terasic_deca.v:150.12-150.46" *)
(* unused_bits = "8 9" *)
wire [9:0] main_basesoc_tx_cdc_asyncfifo_dout;
(* src = "build/terasic_deca/gateware/terasic_deca.v:147.6-147.38" *)
wire main_basesoc_tx_cdc_asyncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:148.6-148.44" *)
wire main_basesoc_tx_cdc_asyncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:145.6-145.38" *)
wire main_basesoc_tx_cdc_asyncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:146.6-146.44" *)
wire main_basesoc_tx_cdc_asyncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:162.12-162.47" *)
wire [2:0] main_basesoc_tx_cdc_consume_wdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:170.6-170.39" *)
wire main_basesoc_tx_cdc_fifo_in_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:171.6-171.38" *)
wire main_basesoc_tx_cdc_fifo_in_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:169.12-169.52" *)
wire [7:0] main_basesoc_tx_cdc_fifo_in_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:173.6-173.40" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_fifo_out_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:174.6-174.39" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_fifo_out_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:172.12-172.53" *)
wire [7:0] main_basesoc_tx_cdc_fifo_out_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:151.6-151.41" *)
wire main_basesoc_tx_cdc_graycounter0_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:152.12-152.46" *)
reg [2:0] main_basesoc_tx_cdc_graycounter0_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:154.12-154.53" *)
reg [2:0] main_basesoc_tx_cdc_graycounter0_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:153.12-153.51" *)
wire [2:0] main_basesoc_tx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:155.12-155.58" *)
wire [2:0] main_basesoc_tx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:156.6-156.41" *)
wire main_basesoc_tx_cdc_graycounter1_ce;
(* src = "build/terasic_deca/gateware/terasic_deca.v:157.12-157.46" *)
reg [2:0] main_basesoc_tx_cdc_graycounter1_q = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:159.12-159.53" *)
reg [2:0] main_basesoc_tx_cdc_graycounter1_q_binary = 3'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:158.12-158.51" *)
wire [2:0] main_basesoc_tx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:160.12-160.58" *)
wire [2:0] main_basesoc_tx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:161.12-161.47" *)
wire [2:0] main_basesoc_tx_cdc_produce_rdomain;
(* src = "build/terasic_deca/gateware/terasic_deca.v:167.12-167.42" *)
wire [1:0] main_basesoc_tx_cdc_rdport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:168.12-168.44" *)
(* unused_bits = "8 9" *)
wire [9:0] main_basesoc_tx_cdc_rdport_dat_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:137.6-137.36" *)
wire main_basesoc_tx_cdc_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:138.6-138.35" *)
wire main_basesoc_tx_cdc_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:139.12-139.49" *)
wire [7:0] main_basesoc_tx_cdc_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:136.6-136.36" *)
wire main_basesoc_tx_cdc_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:135.6-135.36" *)
wire main_basesoc_tx_cdc_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:142.6-142.38" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_source_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:143.6-143.37" *)
(* unused_bits = "0" *)
wire main_basesoc_tx_cdc_source_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:144.12-144.51" *)
wire [7:0] main_basesoc_tx_cdc_source_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:141.6-141.38" *)
wire main_basesoc_tx_cdc_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:140.6-140.38" *)
wire main_basesoc_tx_cdc_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:163.12-163.42" *)
wire [1:0] main_basesoc_tx_cdc_wrport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:166.12-166.44" *)
wire [9:0] main_basesoc_tx_cdc_wrport_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:165.6-165.35" *)
wire main_basesoc_tx_cdc_wrport_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:247.12-247.39" *)
wire [1:0] main_basesoc_uart_pending_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:246.6-246.34" *)
wire main_basesoc_uart_pending_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:245.6-245.34" *)
wire main_basesoc_uart_pending_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:238.6-238.27" *)
wire main_basesoc_uart_rx0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:235.6-235.32" *)
wire main_basesoc_uart_rx_clear;
(* src = "build/terasic_deca/gateware/terasic_deca.v:331.6-331.39" *)
wire main_basesoc_uart_rx_fifo_do_read;
(* src = "build/terasic_deca/gateware/terasic_deca.v:323.12-323.44" *)
reg [4:0] main_basesoc_uart_rx_fifo_level0 = 5'h00;
(* src = "build/terasic_deca/gateware/terasic_deca.v:334.6-334.41" *)
wire main_basesoc_uart_rx_fifo_rdport_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:315.6-315.34" *)
wire main_basesoc_uart_rx_fifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:316.6-316.40" *)
reg main_basesoc_uart_rx_fifo_readable = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:324.6-324.39" *)
wire main_basesoc_uart_rx_fifo_replace;
(* src = "build/terasic_deca/gateware/terasic_deca.v:306.6-306.42" *)
wire main_basesoc_uart_rx_fifo_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:305.6-305.42" *)
wire main_basesoc_uart_rx_fifo_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:311.6-311.44" *)
wire main_basesoc_uart_rx_fifo_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:310.6-310.44" *)
wire main_basesoc_uart_rx_fifo_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:319.6-319.43" *)
wire main_basesoc_uart_rx_fifo_syncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:320.6-320.49" *)
wire main_basesoc_uart_rx_fifo_syncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:317.6-317.43" *)
wire main_basesoc_uart_rx_fifo_syncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:318.6-318.49" *)
wire main_basesoc_uart_rx_fifo_syncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:232.6-232.33" *)
wire main_basesoc_uart_rx_status;
(* src = "build/terasic_deca/gateware/terasic_deca.v:234.6-234.34" *)
wire main_basesoc_uart_rx_trigger;
(* src = "build/terasic_deca/gateware/terasic_deca.v:224.6-224.34" *)
wire main_basesoc_uart_rxempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:256.6-256.33" *)
wire main_basesoc_uart_rxfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:217.12-217.36" *)
wire [7:0] main_basesoc_uart_rxtx_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:216.6-216.31" *)
wire main_basesoc_uart_rxtx_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:218.6-218.31" *)
wire main_basesoc_uart_rxtx_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:239.12-239.43" *)
(* unused_bits = "0" *)
wire [1:0] main_basesoc_uart_status_status;
(* src = "build/terasic_deca/gateware/terasic_deca.v:240.6-240.33" *)
wire main_basesoc_uart_status_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:237.6-237.27" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:289.12-289.45" *)
reg [3:0] main_basesoc_uart_tx_fifo_consume = 4'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:294.6-294.39" *)
wire main_basesoc_uart_tx_fifo_do_read;
(* src = "build/terasic_deca/gateware/terasic_deca.v:300.6-300.45" *)
wire main_basesoc_uart_tx_fifo_fifo_in_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:301.6-301.44" *)
wire main_basesoc_uart_tx_fifo_fifo_in_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:299.12-299.58" *)
wire [7:0] main_basesoc_uart_tx_fifo_fifo_in_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:303.6-303.46" *)
wire main_basesoc_uart_tx_fifo_fifo_out_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:304.6-304.45" *)
wire main_basesoc_uart_tx_fifo_fifo_out_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:302.12-302.59" *)
wire [7:0] main_basesoc_uart_tx_fifo_fifo_out_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:286.12-286.44" *)
reg [4:0] main_basesoc_uart_tx_fifo_level0 = 5'h00;
(* src = "build/terasic_deca/gateware/terasic_deca.v:295.12-295.48" *)
wire [3:0] main_basesoc_uart_tx_fifo_rdport_adr;
(* src = "build/terasic_deca/gateware/terasic_deca.v:296.12-296.50" *)
wire [9:0] main_basesoc_uart_tx_fifo_rdport_dat_r;
(* src = "build/terasic_deca/gateware/terasic_deca.v:297.6-297.41" *)
wire main_basesoc_uart_tx_fifo_rdport_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:278.6-278.34" *)
wire main_basesoc_uart_tx_fifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:279.6-279.40" *)
reg main_basesoc_uart_tx_fifo_readable = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:287.6-287.39" *)
wire main_basesoc_uart_tx_fifo_replace;
(* src = "build/terasic_deca/gateware/terasic_deca.v:270.6-270.42" *)
wire main_basesoc_uart_tx_fifo_sink_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:271.6-271.41" *)
wire main_basesoc_uart_tx_fifo_sink_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:272.12-272.55" *)
wire [7:0] main_basesoc_uart_tx_fifo_sink_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:269.6-269.42" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_fifo_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:268.6-268.42" *)
wire main_basesoc_uart_tx_fifo_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:275.6-275.44" *)
wire main_basesoc_uart_tx_fifo_source_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:276.6-276.43" *)
wire main_basesoc_uart_tx_fifo_source_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:277.12-277.57" *)
wire [7:0] main_basesoc_uart_tx_fifo_source_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:274.6-274.44" *)
wire main_basesoc_uart_tx_fifo_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:273.6-273.44" *)
wire main_basesoc_uart_tx_fifo_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:284.12-284.50" *)
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_din;
(* src = "build/terasic_deca/gateware/terasic_deca.v:285.12-285.51" *)
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_dout;
(* src = "build/terasic_deca/gateware/terasic_deca.v:282.6-282.43" *)
wire main_basesoc_uart_tx_fifo_syncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:283.6-283.49" *)
wire main_basesoc_uart_tx_fifo_syncfifo_readable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:280.6-280.43" *)
wire main_basesoc_uart_tx_fifo_syncfifo_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:281.6-281.49" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_fifo_syncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:293.12-293.50" *)
wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_w;
(* src = "build/terasic_deca/gateware/terasic_deca.v:292.6-292.41" *)
wire main_basesoc_uart_tx_fifo_wrport_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:227.6-227.33" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_status;
(* src = "build/terasic_deca/gateware/terasic_deca.v:229.6-229.34" *)
(* unused_bits = "0" *)
wire main_basesoc_uart_tx_trigger;
(* src = "build/terasic_deca/gateware/terasic_deca.v:253.6-253.34" *)
wire main_basesoc_uart_txempty_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:221.6-221.33" *)
wire main_basesoc_uart_txfull_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:259.6-259.39" *)
wire main_basesoc_uart_uart_sink_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:258.6-258.39" *)
wire main_basesoc_uart_uart_sink_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:265.6-265.41" *)
wire main_basesoc_uart_uart_source_first;
(* src = "build/terasic_deca/gateware/terasic_deca.v:266.6-266.40" *)
wire main_basesoc_uart_uart_source_last;
(* src = "build/terasic_deca/gateware/terasic_deca.v:267.12-267.54" *)
wire [7:0] main_basesoc_uart_uart_source_payload_data;
(* src = "build/terasic_deca/gateware/terasic_deca.v:264.6-264.41" *)
wire main_basesoc_uart_uart_source_ready;
(* src = "build/terasic_deca/gateware/terasic_deca.v:263.6-263.41" *)
wire main_basesoc_uart_uart_source_valid;
(* src = "build/terasic_deca/gateware/terasic_deca.v:77.6-77.24" *)
reg main_basesoc_valid = 1'h0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:386.6-386.36" *)
wire main_basesoc_valid_next_value0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:387.6-387.39" *)
wire main_basesoc_valid_next_value_ce0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:63.12-63.27" *)
wire [3:0] main_basesoc_we;
(* src = "build/terasic_deca/gateware/terasic_deca.v:379.6-379.20" *)
wire main_crg_clkin;
(* src = "build/terasic_deca/gateware/terasic_deca.v:380.6-380.22" *)
wire main_crg_clkout0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:381.6-381.22" *)
wire main_crg_clkout1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:378.6-378.21" *)
wire main_crg_locked;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1702.11-1702.25" *)
reg [9:0] storage_2_dat1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1662.11-1662.23" *)
(* unused_bits = "8 9" *)
reg [9:0] storage_dat1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:373.6-373.13" *)
wire sys_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:65.6-65.18" *)
wire sys_jtag_clk;
(* src = "build/terasic_deca/gateware/terasic_deca.v:66.6-66.18" *)
wire sys_jtag_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:374.6-374.13" *)
wire sys_rst;
(* src = "build/terasic_deca/gateware/terasic_deca.v:27.14-27.22" *)
output user_led;
wire user_led;
(* src = "build/terasic_deca/gateware/terasic_deca.v:28.14-28.24" *)
output user_led_1;
wire user_led_1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:29.14-29.24" *)
output user_led_2;
wire user_led_2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:30.14-30.24" *)
output user_led_3;
wire user_led_3;
(* src = "build/terasic_deca/gateware/terasic_deca.v:31.14-31.24" *)
output user_led_4;
wire user_led_4;
(* src = "build/terasic_deca/gateware/terasic_deca.v:32.14-32.24" *)
output user_led_5;
wire user_led_5;
(* src = "build/terasic_deca/gateware/terasic_deca.v:33.14-33.24" *)
output user_led_6;
wire user_led_6;
(* src = "build/terasic_deca/gateware/terasic_deca.v:34.14-34.24" *)
output user_led_7;
wire user_led_7;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1660.11-1660.18" *)
reg [9:0] storage [3:0];
always @(posedge builder_clks[0]) begin
if (_002_[9])
storage[_000_] <= _001_;
end
assign _003_ = storage[main_basesoc_tx_cdc_graycounter1_q_next_binary[1:0]];
(* src = "build/terasic_deca/gateware/terasic_deca.v:1700.11-1700.20" *)
reg [9:0] storage_2 [15:0];
always @(posedge builder_clks[0]) begin
end
assign _036_ = storage_2[main_basesoc_uart_tx_fifo_consume];
assign _004_ = main_basesoc_uart_tx_fifo_consume + (* src = "build/terasic_deca/gateware/terasic_deca.v:1353.41-1353.81" *) 1'h1;
assign _005_ = main_basesoc_uart_rx_fifo_level0 + (* src = "build/terasic_deca/gateware/terasic_deca.v:1379.41-1379.80" *) 1'h1;
assign _006_ = main_basesoc_tx_cdc_graycounter0_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:758.54-758.102" *) 1'h1;
assign _007_ = main_basesoc_tx_cdc_graycounter1_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:767.54-767.102" *) 1'h1;
assign _008_ = main_basesoc_rx_cdc_graycounter0_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:797.54-797.102" *) 1'h1;
assign _009_ = main_basesoc_rx_cdc_graycounter1_q_binary + (* src = "build/terasic_deca/gateware/terasic_deca.v:806.54-806.102" *) 1'h1;
assign _010_ = main_basesoc_count + (* src = "build/terasic_deca/gateware/terasic_deca.v:828.40-828.65" *) 1'h1;
assign main_basesoc_rx_cdc_graycounter1_ce = main_basesoc_rx_cdc_asyncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:1377.8-1377.91" *) main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_tx_cdc_graycounter0_ce = main_basesoc_tx_cdc_asyncfifo_writable & (* src = "build/terasic_deca/gateware/terasic_deca.v:746.47-746.120" *) main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_tx_cdc_graycounter1_ce = main_basesoc_tx_cdc_asyncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:747.47-747.120" *) main_basesoc_tx_cdc_asyncfifo_re;
assign main_basesoc_rx_cdc_graycounter0_ce = main_basesoc_rx_cdc_asyncfifo_writable & (* src = "build/terasic_deca/gateware/terasic_deca.v:785.47-785.120" *) main_basesoc_rx_cdc_asyncfifo_we;
assign main_basesoc_uart_tx_fifo_syncfifo_re = main_basesoc_uart_tx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:920.49-920.165" *) _043_;
assign main_basesoc_uart_tx_fifo_do_read = main_basesoc_uart_tx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:932.45-932.128" *) main_basesoc_uart_tx_fifo_syncfifo_re;
assign main_basesoc_uart_rx_fifo_syncfifo_re = main_basesoc_uart_rx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:950.49-950.165" *) _040_;
assign main_basesoc_uart_rx_fifo_do_read = main_basesoc_uart_rx_fifo_syncfifo_readable & (* src = "build/terasic_deca/gateware/terasic_deca.v:962.45-962.128" *) main_basesoc_uart_rx_fifo_syncfifo_re;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (_027_) builder_resetinserter_state <= 2'h0;
else if (_024_) builder_resetinserter_state <= builder_resetinserter_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (jtag_rst) builder_max10jtag_state <= 4'h0;
else if (_025_) builder_max10jtag_state <= builder_max10jtag_next_state;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_rx_cdc_graycounter0_q_binary <= 3'h0;
else main_basesoc_rx_cdc_graycounter0_q_binary <= main_basesoc_rx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_rx_cdc_graycounter0_q <= 3'h0;
else main_basesoc_rx_cdc_graycounter0_q <= main_basesoc_rx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_tx_cdc_graycounter1_q_binary <= 3'h0;
else main_basesoc_tx_cdc_graycounter1_q_binary <= main_basesoc_tx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (jtag_rst) main_basesoc_tx_cdc_graycounter1_q <= 3'h0;
else main_basesoc_tx_cdc_graycounter1_q <= main_basesoc_tx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (_027_) main_basesoc_count <= 3'h0;
else if (main_basesoc_count_next_value_ce2) main_basesoc_count <= main_basesoc_count_next_value2;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (_027_) main_basesoc_data <= 8'h00;
else if (main_basesoc_count_next_value_ce2) main_basesoc_data <= main_basesoc_data_next_value1;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
if (_027_) main_basesoc_valid <= 1'h0;
else if (main_basesoc_valid_next_value_ce0) main_basesoc_valid <= main_basesoc_valid_next_value0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1307.1-1316.4" *)
always @(negedge jtag_clk)
if (jtag_rst) main_basesoc_jtag_tdouser <= 1'h0;
else main_basesoc_jtag_tdouser <= main_basesoc_jtag_tdo;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1307.1-1316.4" *)
always @(negedge jtag_clk)
if (jtag_rst) main_basesoc_jtag_capture <= 1'h0;
else main_basesoc_jtag_capture <= main_basesoc_jtag_is_ongoing3;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1307.1-1316.4" *)
always @(negedge jtag_clk)
if (jtag_rst) main_basesoc_jtag_reset <= 1'h0;
else main_basesoc_jtag_reset <= main_basesoc_jtag_is_ongoing0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1318.1-1577.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_rx_fifo_level0 <= 5'h00;
else if (_026_) main_basesoc_uart_rx_fifo_level0 <= _078_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1318.1-1577.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_rx_fifo_readable <= 1'h0;
else if (main_basesoc_uart_rx_fifo_syncfifo_re) main_basesoc_uart_rx_fifo_readable <= _079_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1318.1-1577.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_tx_fifo_consume <= 4'h0;
else if (main_basesoc_uart_tx_fifo_do_read) main_basesoc_uart_tx_fifo_consume <= _004_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1318.1-1577.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_tx_fifo_level0 <= 5'h00;
else if (main_basesoc_uart_tx_fifo_do_read) main_basesoc_uart_tx_fifo_level0 <= _092_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1318.1-1577.4" *)
always @(posedge builder_clks[0])
if (sys_rst) main_basesoc_uart_tx_fifo_readable <= 1'h0;
else if (_023_) main_basesoc_uart_tx_fifo_readable <= _081_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1708.1-1711.4" *)
always @(posedge builder_clks[0])
if (main_basesoc_uart_tx_fifo_do_read) storage_2_dat1 <= _036_;
assign _011_ = | { _045_, _082_, main_basesoc_jtag_shift };
assign _012_ = { _082_, main_basesoc_jtag_shift } != 2'h2;
assign _013_ = { _045_, main_basesoc_jtag_shift } != 2'h2;
assign _014_ = { _045_, _035_, main_basesoc_jtag_shift } != 3'h5;
assign _015_ = { _048_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _016_ = { _050_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _017_ = { _055_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _018_ = { _057_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _019_ = { _060_, main_basesoc_jtag_tmsutap } != 2'h2;
assign _020_ = { _060_, _059_, _058_, _057_, _056_, _055_, _054_, _053_, _052_, _051_, _050_, _049_, _048_, _047_, _046_, main_basesoc_jtag_tmsutap } != 16'h0001;
assign _021_ = | { main_basesoc_rx_cdc_graycounter1_ce, main_basesoc_uart_rx_fifo_do_read };
assign _022_ = { main_basesoc_rx_cdc_graycounter1_ce, main_basesoc_uart_rx_fifo_do_read } != 2'h3;
assign _023_ = | { main_basesoc_uart_tx_fifo_syncfifo_re, main_basesoc_tx_cdc_asyncfifo_writable };
assign _024_ = & { _013_, _011_, _012_, _014_ };
assign _025_ = & { _017_, _018_, _019_, _020_, _015_, _016_ };
assign _026_ = & { _021_, _022_ };
assign _027_ = | { main_basesoc_fsm_reset, jtag_rst };
assign _028_ = | { _060_, _059_, _058_, _057_, _056_, _055_, _054_, _053_, _052_, _051_, _050_, _049_, _048_, _047_, _046_ };
assign _029_ = | { _045_, _082_ };
assign _030_ = | { _053_, _046_ };
assign _031_ = main_basesoc_tx_cdc_graycounter0_q[2] == (* src = "build/terasic_deca/gateware/terasic_deca.v:748.52-748.131" *) builder_multiregimpl1_regs1[2];
assign _032_ = main_basesoc_tx_cdc_graycounter0_q[1] == (* src = "build/terasic_deca/gateware/terasic_deca.v:748.136-748.215" *) builder_multiregimpl1_regs1[1];
assign _033_ = main_basesoc_rx_cdc_graycounter0_q[2] == (* src = "build/terasic_deca/gateware/terasic_deca.v:787.52-787.131" *) builder_multiregimpl3_regs1[2];
assign _034_ = main_basesoc_rx_cdc_graycounter0_q[1] == (* src = "build/terasic_deca/gateware/terasic_deca.v:787.136-787.215" *) builder_multiregimpl3_regs1[1];
assign _035_ = main_basesoc_count == (* src = "build/terasic_deca/gateware/terasic_deca.v:832.10-832.36" *) 3'h7;
assign _037_ = main_basesoc_tx_cdc_graycounter0_q[0] != (* src = "build/terasic_deca/gateware/terasic_deca.v:748.221-748.300" *) builder_multiregimpl1_regs1[0];
assign main_basesoc_tx_cdc_asyncfifo_readable = main_basesoc_tx_cdc_graycounter1_q != (* src = "build/terasic_deca/gateware/terasic_deca.v:749.50-749.123" *) builder_multiregimpl0_regs1;
assign _038_ = main_basesoc_rx_cdc_graycounter0_q[0] != (* src = "build/terasic_deca/gateware/terasic_deca.v:787.221-787.300" *) builder_multiregimpl3_regs1[0];
assign main_basesoc_rx_cdc_asyncfifo_readable = main_basesoc_rx_cdc_graycounter1_q != (* src = "build/terasic_deca/gateware/terasic_deca.v:788.50-788.123" *) builder_multiregimpl2_regs1;
assign main_basesoc_uart_tx_fifo_syncfifo_readable = | (* src = "build/terasic_deca/gateware/terasic_deca.v:937.55-937.95" *) main_basesoc_uart_tx_fifo_level0;
assign main_basesoc_rx_cdc_asyncfifo_re = main_basesoc_uart_rx_fifo_level0 != (* src = "build/terasic_deca/gateware/terasic_deca.v:966.55-966.96" *) 5'h10;
assign main_basesoc_uart_rx_fifo_syncfifo_readable = | (* src = "build/terasic_deca/gateware/terasic_deca.v:967.55-967.95" *) main_basesoc_uart_rx_fifo_level0;
assign _039_ = ~ (* src = "build/terasic_deca/gateware/terasic_deca.v:920.97-920.132" *) main_basesoc_uart_tx_fifo_readable;
assign _040_ = ~ (* src = "build/terasic_deca/gateware/terasic_deca.v:950.97-950.132" *) main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_fsm_reset = main_basesoc_jtag_reset | (* src = "build/terasic_deca/gateware/terasic_deca.v:554.34-554.85" *) main_basesoc_jtag_capture;
assign _041_ = _031_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:748.51-748.216" *) _032_;
assign main_basesoc_tx_cdc_asyncfifo_writable = _041_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:748.50-748.301" *) _037_;
assign _042_ = _033_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:787.51-787.216" *) _034_;
assign main_basesoc_rx_cdc_asyncfifo_writable = _042_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:787.50-787.301" *) _038_;
assign _043_ = _039_ | (* src = "build/terasic_deca/gateware/terasic_deca.v:920.96-920.164" *) main_basesoc_tx_cdc_asyncfifo_writable;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1668.1-1670.4" *)
always @(posedge jtag_clk)
storage_dat1 <= _003_;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
main_basesoc_tx_cdc_graycounter0_q <= main_basesoc_tx_cdc_graycounter0_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
main_basesoc_tx_cdc_graycounter0_q_binary <= main_basesoc_tx_cdc_graycounter0_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
main_basesoc_rx_cdc_graycounter1_q <= main_basesoc_rx_cdc_graycounter1_q_next;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
main_basesoc_rx_cdc_graycounter1_q_binary <= main_basesoc_rx_cdc_graycounter1_q_next_binary;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl1_regs0 <= main_basesoc_tx_cdc_graycounter1_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl1_regs1 <= builder_multiregimpl1_regs0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl2_regs0 <= main_basesoc_rx_cdc_graycounter0_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1579.1-1594.4" *)
always @(posedge builder_clks[0])
builder_multiregimpl2_regs1 <= builder_multiregimpl2_regs0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
builder_multiregimpl0_regs0 <= main_basesoc_tx_cdc_graycounter0_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
builder_multiregimpl0_regs1 <= builder_multiregimpl0_regs0;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
builder_multiregimpl3_regs0 <= main_basesoc_rx_cdc_graycounter1_q;
(* src = "build/terasic_deca/gateware/terasic_deca.v:1268.1-1305.4" *)
always @(posedge jtag_clk)
builder_multiregimpl3_regs1 <= builder_multiregimpl3_regs0;
assign _044_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:827.8-827.31|build/terasic_deca/gateware/terasic_deca.v:827.4-835.7" *) { main_basesoc_jtag_tdiutap, main_basesoc_data[7:1] } : 8'h00;
assign _045_ = builder_resetinserter_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) 2'h1;
assign main_basesoc_rx_cdc_graycounter1_q_next_binary = main_basesoc_rx_cdc_graycounter1_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:805.6-805.41|build/terasic_deca/gateware/terasic_deca.v:805.2-809.5" *) _009_ : main_basesoc_rx_cdc_graycounter1_q_binary;
assign main_basesoc_rx_cdc_graycounter0_q_next_binary = main_basesoc_rx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:796.6-796.41|build/terasic_deca/gateware/terasic_deca.v:796.2-800.5" *) _008_ : main_basesoc_rx_cdc_graycounter0_q_binary;
assign main_basesoc_tx_cdc_graycounter1_q_next_binary = main_basesoc_tx_cdc_graycounter1_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:766.6-766.41|build/terasic_deca/gateware/terasic_deca.v:766.2-770.5" *) _007_ : main_basesoc_tx_cdc_graycounter1_q_binary;
assign main_basesoc_tx_cdc_graycounter0_q_next_binary = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:757.6-757.41|build/terasic_deca/gateware/terasic_deca.v:757.2-761.5" *) _006_ : main_basesoc_tx_cdc_graycounter0_q_binary;
assign main_basesoc_jtag_is_ongoing0 = _028_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 1'h0 : 1'h1;
assign _046_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'hf;
assign _047_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'he;
assign _048_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'hd;
assign _049_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'hc;
assign _050_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'hb;
assign _051_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'ha;
assign _052_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h9;
assign _053_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h8;
assign _054_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h7;
assign _055_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h6;
assign _056_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h5;
assign _057_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h4;
assign _058_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h3;
assign _059_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h2;
assign _060_ = builder_max10jtag_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 4'h1;
assign _061_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:727.8-727.32|build/terasic_deca/gateware/terasic_deca.v:727.4-729.7" *) 4'hx : 4'h1;
assign _062_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:718.8-718.29|build/terasic_deca/gateware/terasic_deca.v:718.4-722.7" *) 4'h2 : 4'h1;
function [3:0] _208_;
input [3:0] a;
input [55:0] b;
input [13:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *)
(* parallel_case *)
casez (s)
14'b?????????????1:
_208_ = b[3:0];
14'b????????????1?:
_208_ = b[7:4];
14'b???????????1??:
_208_ = b[11:8];
14'b??????????1???:
_208_ = b[15:12];
14'b?????????1????:
_208_ = b[19:16];
14'b????????1?????:
_208_ = b[23:20];
14'b???????1??????:
_208_ = b[27:24];
14'b??????1???????:
_208_ = b[31:28];
14'b?????1????????:
_208_ = b[35:32];
14'b????1?????????:
_208_ = b[39:36];
14'b???1??????????:
_208_ = b[43:40];
14'b??1???????????:
_208_ = b[47:44];
14'b?1????????????:
_208_ = b[51:48];
14'b1?????????????:
_208_ = b[55:52];
default:
_208_ = a;
endcase
endfunction
assign builder_max10jtag_next_state = _208_(_061_, { _075_, _074_, _073_, _072_, _071_, _070_, _069_, _068_, _067_, _066_, _065_, _064_, _063_, _062_ }, { _060_, _059_, _058_, _057_, _056_, _055_, _054_, _052_, _051_, _050_, _049_, _048_, _047_, _030_ });
assign _063_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:709.8-709.29|build/terasic_deca/gateware/terasic_deca.v:709.4-713.7" *) 4'hf : 4'hb;
assign _064_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:702.8-702.29|build/terasic_deca/gateware/terasic_deca.v:702.4-704.7" *) 4'he : 4'hx;
assign _065_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:693.8-693.32|build/terasic_deca/gateware/terasic_deca.v:693.4-697.7" *) 4'hf : 4'hd;
assign _066_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:686.8-686.29|build/terasic_deca/gateware/terasic_deca.v:686.4-688.7" *) 4'hc : 4'hx;
assign _067_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:677.8-677.32|build/terasic_deca/gateware/terasic_deca.v:677.4-681.7" *) 4'hc : 4'hb;
assign _068_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:668.8-668.32|build/terasic_deca/gateware/terasic_deca.v:668.4-672.7" *) 4'h0 : 4'ha;
assign _069_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:650.8-650.29|build/terasic_deca/gateware/terasic_deca.v:650.4-654.7" *) 4'h8 : 4'h4;
assign _070_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:643.8-643.29|build/terasic_deca/gateware/terasic_deca.v:643.4-645.7" *) 4'h7 : 4'hx;
assign _071_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:634.8-634.32|build/terasic_deca/gateware/terasic_deca.v:634.4-638.7" *) 4'h8 : 4'h6;
assign _072_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:627.8-627.29|build/terasic_deca/gateware/terasic_deca.v:627.4-629.7" *) 4'h5 : 4'hx;
assign _073_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:618.8-618.32|build/terasic_deca/gateware/terasic_deca.v:618.4-622.7" *) 4'h5 : 4'h4;
assign _074_ = main_basesoc_jtag_tmsutap ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:609.8-609.32|build/terasic_deca/gateware/terasic_deca.v:609.4-613.7" *) 4'h9 : 4'h3;
assign _075_ = main_basesoc_jtag_tmsutap ? (* src = "build/terasic_deca/gateware/terasic_deca.v:602.8-602.29|build/terasic_deca/gateware/terasic_deca.v:602.4-604.7" *) 4'h2 : 4'hx;
assign main_basesoc_jtag_is_ongoing3 = _058_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:600.2-732.9" *) 1'h1 : 1'h0;
assign _002_[9] = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1664.6-1664.35|build/terasic_deca/gateware/terasic_deca.v:1664.2-1665.79" *) 1'h1 : 1'h0;
assign _001_ = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1664.6-1664.35|build/terasic_deca/gateware/terasic_deca.v:1664.2-1665.79" *) storage_2_dat1 : 10'hxxx;
assign _000_ = main_basesoc_tx_cdc_graycounter0_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1664.6-1664.35|build/terasic_deca/gateware/terasic_deca.v:1664.2-1665.79" *) main_basesoc_tx_cdc_graycounter0_q_binary[1:0] : 2'hx;
assign _076_ = main_basesoc_uart_rx_fifo_do_read ? (* src = "build/terasic_deca/gateware/terasic_deca.v:1382.7-1382.40|build/terasic_deca/gateware/terasic_deca.v:1382.3-1384.6" *) _093_ : 5'hxx;
assign _077_ = main_basesoc_uart_rx_fifo_do_read ? (* src = "build/terasic_deca/gateware/terasic_deca.v:1378.7-1378.43|build/terasic_deca/gateware/terasic_deca.v:1378.3-1380.6" *) 5'hxx : _005_;
assign _078_ = main_basesoc_rx_cdc_graycounter1_ce ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1377.6-1377.132|build/terasic_deca/gateware/terasic_deca.v:1377.2-1385.5" *) _077_ : _076_;
assign _079_ = main_basesoc_uart_rx_fifo_syncfifo_re ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1364.6-1364.43|build/terasic_deca/gateware/terasic_deca.v:1364.2-1370.5" *) 1'h1 : 1'hx;
assign _080_ = main_basesoc_tx_cdc_asyncfifo_writable ? (* src = "build/terasic_deca/gateware/terasic_deca.v:1345.7-1345.35|build/terasic_deca/gateware/terasic_deca.v:1345.3-1347.6" *) 1'h0 : 1'hx;
assign _081_ = main_basesoc_uart_tx_fifo_syncfifo_re ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:1342.6-1342.43|build/terasic_deca/gateware/terasic_deca.v:1342.2-1348.5" *) 1'h1 : _080_;
function [0:0] _232_;
input [0:0] a;
input [1:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *)
(* parallel_case *)
casez (s)
2'b?1:
_232_ = b[0:0];
2'b1?:
_232_ = b[1:1];
default:
_232_ = a;
endcase
endfunction
assign main_basesoc_jtag_tdo = _232_(main_basesoc_rx_cdc_asyncfifo_writable, { main_basesoc_data[0], main_basesoc_valid }, { _045_, _082_ });
assign _082_ = builder_resetinserter_state == (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) 2'h2;
assign _083_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:846.8-846.31|build/terasic_deca/gateware/terasic_deca.v:846.4-855.7" *) 2'h1 : 2'hx;
assign _084_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:839.8-839.31|build/terasic_deca/gateware/terasic_deca.v:839.4-842.7" *) 2'h0 : 2'hx;
function [1:0] _236_;
input [1:0] a;
input [3:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *)
(* parallel_case *)
casez (s)
2'b?1:
_236_ = b[1:0];
2'b1?:
_236_ = b[3:2];
default:
_236_ = a;
endcase
endfunction
assign builder_resetinserter_next_state = _236_(_083_, { _086_, _084_ }, { _045_, _082_ });
assign _085_ = _035_ ? (* src = "build/terasic_deca/gateware/terasic_deca.v:832.9-832.37|build/terasic_deca/gateware/terasic_deca.v:832.5-834.8" *) 2'h2 : 2'hx;
assign _086_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:827.8-827.31|build/terasic_deca/gateware/terasic_deca.v:827.4-835.7" *) _085_ : 2'hx;
assign _087_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:846.8-846.31|build/terasic_deca/gateware/terasic_deca.v:846.4-855.7" *) 1'h1 : 1'h0;
assign main_basesoc_valid_next_value_ce0 = _029_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) 1'h0 : _087_;
assign _088_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:846.8-846.31|build/terasic_deca/gateware/terasic_deca.v:846.4-855.7" *) main_basesoc_tx_cdc_asyncfifo_readable : 1'h0;
assign main_basesoc_valid_next_value0 = _029_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) 1'h0 : _088_;
assign _089_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:839.8-839.31|build/terasic_deca/gateware/terasic_deca.v:839.4-842.7" *) main_basesoc_jtag_tdiutap : 1'h0;
assign main_basesoc_rx_cdc_asyncfifo_we = _082_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) _089_ : 1'h0;
assign main_basesoc_count_next_value_ce2 = _082_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) 1'h0 : _087_;
assign main_basesoc_tx_cdc_asyncfifo_re = _029_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) 1'h0 : _089_;
assign _090_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:827.8-827.31|build/terasic_deca/gateware/terasic_deca.v:827.4-835.7" *) _010_ : 3'h0;
assign main_basesoc_count_next_value2 = _045_ ? (* full_case = 32'd1 *) (* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *) _090_ : 3'h0;
assign _091_ = main_basesoc_jtag_shift ? (* src = "build/terasic_deca/gateware/terasic_deca.v:846.8-846.31|build/terasic_deca/gateware/terasic_deca.v:846.4-855.7" *) storage_dat1[7:0] : 8'h00;
function [7:0] _250_;
input [7:0] a;
input [15:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:0.0-0.0|build/terasic_deca/gateware/terasic_deca.v:824.2-857.9" *)
(* parallel_case *)
casez (s)
2'b?1:
_250_ = b[7:0];
2'b1?:
_250_ = b[15:8];
default:
_250_ = a;
endcase
endfunction
assign main_basesoc_data_next_value1 = _250_(_091_, { _044_, 8'h00 }, { _045_, _082_ });
assign _092_ = main_basesoc_uart_tx_fifo_level0 - (* src = "build/terasic_deca/gateware/terasic_deca.v:1361.41-1361.80" *) 1'h1;
assign _093_ = main_basesoc_uart_rx_fifo_level0 - (* src = "build/terasic_deca/gateware/terasic_deca.v:1383.41-1383.80" *) 1'h1;
assign main_basesoc_tx_cdc_graycounter0_q_next = main_basesoc_tx_cdc_graycounter0_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:763.51-763.151" *) main_basesoc_tx_cdc_graycounter0_q_next_binary[2:1];
assign main_basesoc_tx_cdc_graycounter1_q_next = main_basesoc_tx_cdc_graycounter1_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:772.51-772.151" *) main_basesoc_tx_cdc_graycounter1_q_next_binary[2:1];
assign main_basesoc_rx_cdc_graycounter0_q_next = main_basesoc_rx_cdc_graycounter0_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:802.51-802.151" *) main_basesoc_rx_cdc_graycounter0_q_next_binary[2:1];
assign main_basesoc_rx_cdc_graycounter1_q_next = main_basesoc_rx_cdc_graycounter1_q_next_binary ^ (* src = "build/terasic_deca/gateware/terasic_deca.v:811.51-811.151" *) main_basesoc_rx_cdc_graycounter1_q_next_binary[2:1];
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1750.3-1760.2" *)
ALTPLL #(
.BANDWIDTH_TYPE("AUTO"),
.CLK0_DIVIDE_BY(5'h19),
.CLK0_DUTY_CYCLE(6'h32),
.CLK0_MULTIPLY_BY(5'h19),
.CLK0_PHASE_SHIFT(1'h0),
.CLK1_DIVIDE_BY(5'h1f),
.CLK1_DUTY_CYCLE(6'h32),
.CLK1_MULTIPLY_BY(5'h19),
.CLK1_PHASE_SHIFT(1'h0),
.COMPENSATE_CLOCK("CLK0"),
.INCLK0_INPUT_FREQUENCY(15'h4e20),
.OPERATION_MODE("NORMAL")
) ALTPLL (
.ARESET(1'h0),
.CLK(builder_clks),
.CLKENA(5'h1f),
.EXTCLKENA(4'hf),
.FBIN(1'h1),
.INCLK(clk50),
.LOCKED(main_crg_locked),
.PFDENA(1'h1),
.PLLENA(1'h1)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1762.5-1768.2" *)
DFF DFF (
.clk(jtag_clk),
.clrn(1'h1),
.d(1'h0),
.prn(1'h1),
.q(builder_rst_meta0)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1770.5-1776.2" *)
DFF DFF_1 (
.clk(jtag_clk),
.clrn(1'h1),
.d(builder_rst_meta0),
.prn(1'h1),
.q(jtag_rst)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1778.5-1784.2" *)
DFF DFF_2 (
.clk(builder_clks[0]),
.clrn(1'h1),
.d(1'h0),
.prn(main_crg_locked),
.q(builder_rst_meta1)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1786.5-1792.2" *)
DFF DFF_3 (
.clk(builder_clks[0]),
.clrn(1'h1),
.d(builder_rst_meta1),
.prn(main_crg_locked),
.q(sys_rst)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1794.5-1800.2" *)
DFF DFF_4 (
.clk(builder_clks[1]),
.clrn(1'h1),
.d(1'h0),
.prn(main_crg_locked),
.q(builder_rst_meta2)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1802.5-1808.2" *)
DFF DFF_5 (
.clk(builder_clks[1]),
.clrn(1'h1),
.d(builder_rst_meta2),
.prn(main_crg_locked),
.q(hdmi_rst)
);
(* module_not_derived = 32'd1 *)
(* src = "build/terasic_deca/gateware/terasic_deca.v:1639.18-1653.2" *)
fiftyfivenm_jtag fiftyfivenm_jtag (
.clkdruser(main_basesoc_jtag_drck),
.runidleuser(main_basesoc_jtag_runtest),
.shiftuser(main_basesoc_jtag_shift),
.tck(altera_reserved_tck),
.tckutap(jtag_clk),
.tdi(altera_reserved_tdi),
.tdiutap(main_basesoc_jtag_tdiutap),
.tdo(main_basesoc_jtag_altera_reserved_tdo),
.tdouser(main_basesoc_jtag_tdouser),
.tms(altera_reserved_tms),
.tmsutap(main_basesoc_jtag_tmsutap),
.updateuser(main_basesoc_jtag_update),
.usr1user(main_basesoc_jtag_sel)
);
assign _002_[8:0] = { _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9], _002_[9] };
assign altera_reserved_tdo = main_basesoc_jtag_altera_reserved_tdo;
assign builder_basesoc_adr = 14'h0000;
assign builder_basesoc_dat_w = 32'd0;
assign builder_basesoc_we = 1'h0;
assign builder_basesoc_wishbone_adr = 30'h00000000;
assign builder_basesoc_wishbone_cyc = 1'h0;
assign builder_basesoc_wishbone_dat_w = 32'd0;
assign builder_basesoc_wishbone_sel = 4'h0;
assign builder_basesoc_wishbone_stb = 1'h0;
assign builder_basesoc_wishbone_we = 1'h0;
assign builder_csr_bankarray_adr = 6'h00;
assign builder_csr_bankarray_csrbank0_bus_errors_r = 32'd0;
assign builder_csr_bankarray_csrbank0_bus_errors_re = 1'h0;
assign builder_csr_bankarray_csrbank0_bus_errors_we = 1'h0;
assign builder_csr_bankarray_csrbank0_reset0_r = 2'h0;
assign builder_csr_bankarray_csrbank0_reset0_re = 1'h0;
assign builder_csr_bankarray_csrbank0_reset0_we = 1'h1;
assign builder_csr_bankarray_csrbank0_scratch0_r = 32'd0;
assign builder_csr_bankarray_csrbank0_scratch0_re = 1'h0;
assign builder_csr_bankarray_csrbank0_scratch0_we = 1'h0;
assign builder_csr_bankarray_csrbank0_sel = 1'h1;
assign builder_csr_bankarray_csrbank1_en0_r = 1'h0;
assign builder_csr_bankarray_csrbank1_en0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_en0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_enable0_r = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_enable0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_enable0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_pending_r = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_pending_re = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_pending_we = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_status_r = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_status_re = 1'h0;
assign builder_csr_bankarray_csrbank1_ev_status_we = 1'h0;
assign builder_csr_bankarray_csrbank1_load0_r = 32'd0;
assign builder_csr_bankarray_csrbank1_load0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_load0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_reload0_r = 32'd0;
assign builder_csr_bankarray_csrbank1_reload0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_reload0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_sel = 1'h0;
assign builder_csr_bankarray_csrbank1_update_value0_r = 1'h0;
assign builder_csr_bankarray_csrbank1_update_value0_re = 1'h0;
assign builder_csr_bankarray_csrbank1_update_value0_we = 1'h0;
assign builder_csr_bankarray_csrbank1_value_r = 32'd0;
assign builder_csr_bankarray_csrbank1_value_re = 1'h0;
assign builder_csr_bankarray_csrbank1_value_we = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_enable0_r = 2'h0;
assign builder_csr_bankarray_csrbank2_ev_enable0_re = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_enable0_we = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_pending_r = 2'h0;
assign builder_csr_bankarray_csrbank2_ev_pending_re = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_pending_we = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_status_r = 2'h0;
assign builder_csr_bankarray_csrbank2_ev_status_re = 1'h0;
assign builder_csr_bankarray_csrbank2_ev_status_w[1] = main_basesoc_uart_rx_fifo_readable;
assign builder_csr_bankarray_csrbank2_ev_status_we = 1'h0;
assign builder_csr_bankarray_csrbank2_rxempty_r = 1'h0;
assign builder_csr_bankarray_csrbank2_rxempty_re = 1'h0;
assign builder_csr_bankarray_csrbank2_rxempty_we = 1'h0;
assign builder_csr_bankarray_csrbank2_rxfull_r = 1'h0;
assign builder_csr_bankarray_csrbank2_rxfull_re = 1'h0;
assign builder_csr_bankarray_csrbank2_rxfull_we = 1'h0;
assign builder_csr_bankarray_csrbank2_sel = 1'h0;
assign builder_csr_bankarray_csrbank2_txempty_r = 1'h0;
assign builder_csr_bankarray_csrbank2_txempty_re = 1'h0;
assign builder_csr_bankarray_csrbank2_txempty_we = 1'h0;
assign builder_csr_bankarray_csrbank2_txfull_r = 1'h0;
assign builder_csr_bankarray_csrbank2_txfull_re = 1'h0;
assign builder_csr_bankarray_csrbank2_txfull_we = 1'h0;
assign builder_csr_bankarray_interface0_bank_bus_adr = 14'h0000;
assign builder_csr_bankarray_interface0_bank_bus_dat_w = 32'd0;
assign builder_csr_bankarray_interface0_bank_bus_we = 1'h0;
assign builder_csr_bankarray_interface1_bank_bus_adr = 14'h0000;
assign builder_csr_bankarray_interface1_bank_bus_dat_w = 32'd0;
assign builder_csr_bankarray_interface1_bank_bus_we = 1'h0;
assign builder_csr_bankarray_interface2_bank_bus_adr = 14'h0000;
assign builder_csr_bankarray_interface2_bank_bus_dat_w = 32'd0;
assign builder_csr_bankarray_interface2_bank_bus_we = 1'h0;
assign builder_csr_bankarray_sel = 1'h0;
assign builder_csr_bankarray_sram_bus_adr = 14'h0000;
assign builder_csr_bankarray_sram_bus_dat_w = 32'd0;
assign builder_csr_bankarray_sram_bus_we = 1'h0;
assign builder_csr_interconnect_adr = 14'h0000;
assign builder_csr_interconnect_dat_w = 32'd0;
assign builder_csr_interconnect_we = 1'h0;
assign hdmi_clk = builder_clks[1];
assign jtag_inv_rst = jtag_rst;
assign main_basesoc_adr = 11'h000;
assign main_basesoc_bus_error = 1'h0;
assign main_basesoc_bus_errors_we = 1'h0;
assign main_basesoc_dat_w = 32'd0;
assign main_basesoc_data_next_value_ce1 = main_basesoc_count_next_value_ce2;
assign main_basesoc_jtag_CAPTURE_DR = main_basesoc_jtag_is_ongoing3;
assign main_basesoc_jtag_TEST_LOGIC_RESET = main_basesoc_jtag_is_ongoing0;
assign main_basesoc_jtag_altera_reserved_tck = altera_reserved_tck;
assign main_basesoc_jtag_altera_reserved_tdi = altera_reserved_tdi;
assign main_basesoc_jtag_altera_reserved_tms = altera_reserved_tms;
assign main_basesoc_jtag_tck = jtag_clk;
assign main_basesoc_jtag_tckutap = jtag_clk;
assign main_basesoc_jtag_tdi = main_basesoc_jtag_tdiutap;
assign main_basesoc_jtag_tms = main_basesoc_jtag_tmsutap;
assign main_basesoc_ram_bus_adr = 30'h00000000;
assign main_basesoc_ram_bus_cyc = 1'h0;
assign main_basesoc_ram_bus_dat_w = 32'd0;
assign main_basesoc_ram_bus_sel = 4'h0;
assign main_basesoc_ram_bus_stb = 1'h0;
assign main_basesoc_ram_bus_we = 1'h0;
assign main_basesoc_rx_cdc_asyncfifo_din = { 2'h0, main_basesoc_data };
assign main_basesoc_rx_cdc_consume_wdomain = builder_multiregimpl3_regs1;
assign main_basesoc_rx_cdc_fifo_in_first = 1'h0;
assign main_basesoc_rx_cdc_fifo_in_last = 1'h0;
assign main_basesoc_rx_cdc_fifo_in_payload_data = main_basesoc_data;
assign main_basesoc_rx_cdc_produce_rdomain = builder_multiregimpl2_regs1;
assign main_basesoc_rx_cdc_rdport_adr = main_basesoc_rx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_rx_cdc_sink_first = 1'h0;
assign main_basesoc_rx_cdc_sink_last = 1'h0;
assign main_basesoc_rx_cdc_sink_payload_data = main_basesoc_data;
assign main_basesoc_rx_cdc_sink_ready = main_basesoc_rx_cdc_asyncfifo_writable;
assign main_basesoc_rx_cdc_sink_valid = main_basesoc_rx_cdc_asyncfifo_we;
assign main_basesoc_rx_cdc_source_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_rx_cdc_source_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_rx_cdc_wrport_adr = main_basesoc_rx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_rx_cdc_wrport_dat_w = { 2'h0, main_basesoc_data };
assign main_basesoc_rx_cdc_wrport_we = main_basesoc_rx_cdc_graycounter0_ce;
assign main_basesoc_sink_sink_first = storage_2_dat1[8];
assign main_basesoc_sink_sink_last = storage_2_dat1[9];
assign main_basesoc_sink_sink_payload_data = storage_2_dat1[7:0];
assign main_basesoc_sink_sink_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_sink_sink_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_source_source_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_source_source_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_timer_pending_we = 1'h0;
assign main_basesoc_timer_status_we = 1'h0;
assign main_basesoc_timer_value_we = 1'h0;
assign main_basesoc_tx_cdc_asyncfifo_din = storage_2_dat1;
assign main_basesoc_tx_cdc_asyncfifo_dout = storage_dat1;
assign main_basesoc_tx_cdc_asyncfifo_we = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_tx_cdc_consume_wdomain = builder_multiregimpl1_regs1;
assign main_basesoc_tx_cdc_fifo_in_first = storage_2_dat1[8];
assign main_basesoc_tx_cdc_fifo_in_last = storage_2_dat1[9];
assign main_basesoc_tx_cdc_fifo_in_payload_data = storage_2_dat1[7:0];
assign main_basesoc_tx_cdc_fifo_out_first = storage_dat1[8];
assign main_basesoc_tx_cdc_fifo_out_last = storage_dat1[9];
assign main_basesoc_tx_cdc_fifo_out_payload_data = storage_dat1[7:0];
assign main_basesoc_tx_cdc_produce_rdomain = builder_multiregimpl0_regs1;
assign main_basesoc_tx_cdc_rdport_adr = main_basesoc_tx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_tx_cdc_rdport_dat_r = storage_dat1;
assign main_basesoc_tx_cdc_sink_first = storage_2_dat1[8];
assign main_basesoc_tx_cdc_sink_last = storage_2_dat1[9];
assign main_basesoc_tx_cdc_sink_payload_data = storage_2_dat1[7:0];
assign main_basesoc_tx_cdc_sink_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_tx_cdc_sink_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_tx_cdc_source_first = storage_dat1[8];
assign main_basesoc_tx_cdc_source_last = storage_dat1[9];
assign main_basesoc_tx_cdc_source_payload_data = storage_dat1[7:0];
assign main_basesoc_tx_cdc_source_ready = main_basesoc_tx_cdc_asyncfifo_re;
assign main_basesoc_tx_cdc_source_valid = main_basesoc_tx_cdc_asyncfifo_readable;
assign main_basesoc_tx_cdc_wrport_adr = main_basesoc_tx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_tx_cdc_wrport_dat_w = storage_2_dat1;
assign main_basesoc_tx_cdc_wrport_we = main_basesoc_tx_cdc_graycounter0_ce;
assign main_basesoc_uart_pending_r = 2'h0;
assign main_basesoc_uart_pending_re = 1'h0;
assign main_basesoc_uart_pending_we = 1'h0;
assign main_basesoc_uart_rx0 = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_clear = 1'h0;
assign main_basesoc_uart_rx_fifo_rdport_re = main_basesoc_uart_rx_fifo_do_read;
assign main_basesoc_uart_rx_fifo_re = 1'h0;
assign main_basesoc_uart_rx_fifo_replace = 1'h0;
assign main_basesoc_uart_rx_fifo_sink_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_uart_rx_fifo_sink_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_uart_rx_fifo_source_ready = 1'h0;
assign main_basesoc_uart_rx_fifo_source_valid = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_fifo_syncfifo_we = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_uart_rx_fifo_syncfifo_writable = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_uart_rx_status = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_trigger = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rxempty_we = 1'h0;
assign main_basesoc_uart_rxfull_we = 1'h0;
assign main_basesoc_uart_rxtx_r = 8'h00;
assign main_basesoc_uart_rxtx_re = 1'h0;
assign main_basesoc_uart_rxtx_we = 1'h0;
assign main_basesoc_uart_status_status = { main_basesoc_uart_rx_fifo_readable, builder_csr_bankarray_csrbank2_ev_status_w[0] };
assign main_basesoc_uart_status_we = 1'h0;
assign main_basesoc_uart_tx0 = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_fifo_fifo_in_first = 1'h0;
assign main_basesoc_uart_tx_fifo_fifo_in_last = 1'h0;
assign main_basesoc_uart_tx_fifo_fifo_in_payload_data = 8'h00;
assign main_basesoc_uart_tx_fifo_fifo_out_first = storage_2_dat1[8];
assign main_basesoc_uart_tx_fifo_fifo_out_last = storage_2_dat1[9];
assign main_basesoc_uart_tx_fifo_fifo_out_payload_data = storage_2_dat1[7:0];
assign main_basesoc_uart_tx_fifo_rdport_adr = main_basesoc_uart_tx_fifo_consume;
assign main_basesoc_uart_tx_fifo_rdport_dat_r = storage_2_dat1;
assign main_basesoc_uart_tx_fifo_rdport_re = main_basesoc_uart_tx_fifo_do_read;
assign main_basesoc_uart_tx_fifo_re = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_uart_tx_fifo_replace = 1'h0;
assign main_basesoc_uart_tx_fifo_sink_first = 1'h0;
assign main_basesoc_uart_tx_fifo_sink_last = 1'h0;
assign main_basesoc_uart_tx_fifo_sink_payload_data = 8'h00;
assign main_basesoc_uart_tx_fifo_sink_ready = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_fifo_sink_valid = 1'h0;
assign main_basesoc_uart_tx_fifo_source_first = storage_2_dat1[8];
assign main_basesoc_uart_tx_fifo_source_last = storage_2_dat1[9];
assign main_basesoc_uart_tx_fifo_source_payload_data = storage_2_dat1[7:0];
assign main_basesoc_uart_tx_fifo_source_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_uart_tx_fifo_source_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_uart_tx_fifo_syncfifo_din = 10'h000;
assign main_basesoc_uart_tx_fifo_syncfifo_dout = storage_2_dat1;
assign main_basesoc_uart_tx_fifo_syncfifo_we = 1'h0;
assign main_basesoc_uart_tx_fifo_syncfifo_writable = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_fifo_wrport_dat_w = 10'h000;
assign main_basesoc_uart_tx_fifo_wrport_we = 1'h0;
assign main_basesoc_uart_tx_status = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_tx_trigger = builder_csr_bankarray_csrbank2_ev_status_w[0];
assign main_basesoc_uart_txempty_we = 1'h0;
assign main_basesoc_uart_txfull_we = 1'h0;
assign main_basesoc_uart_uart_sink_ready = main_basesoc_rx_cdc_asyncfifo_re;
assign main_basesoc_uart_uart_sink_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_uart_uart_source_first = storage_2_dat1[8];
assign main_basesoc_uart_uart_source_last = storage_2_dat1[9];
assign main_basesoc_uart_uart_source_payload_data = storage_2_dat1[7:0];
assign main_basesoc_uart_uart_source_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_uart_uart_source_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_we = 4'h0;
assign main_crg_clkin = clk50;
assign main_crg_clkout0 = builder_clks[0];
assign main_crg_clkout1 = builder_clks[1];
assign sys_clk = builder_clks[0];
assign sys_jtag_clk = builder_clks[0];
assign sys_jtag_rst = 1'h0;
assign user_led = gpio[0];
assign user_led_1 = gpio[1];
assign user_led_2 = gpio[2];
assign user_led_3 = gpio[3];
assign user_led_4 = gpio[4];
assign user_led_5 = gpio[5];
assign user_led_6 = gpio[6];
assign user_led_7 = gpio[7];
endmodule
Raw
request_all.v
// -----------------------------------------------------------------------------
// Auto-Generated by: __ _ __ _ __
// / / (_) /____ | |/_/
// / /__/ / __/ -_)> <
// /____/_/\__/\__/_/|_|
// Build your hardware, easily!
// https://github.com/enjoy-digital/litex
//
// Filename : terasic_deca.v
// Device : 10M50DAF484C6GES
// LiteX sha1 : 145c74f7
// Date : 2022-02-08 16:32:20
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------
module terasic_deca (
input wire altera_reserved_tms,
input wire altera_reserved_tck,
input wire altera_reserved_tdi,
output wire altera_reserved_tdo,
input wire clk50,
input wire [43:0] gpio,
output reg user_led0,
output reg user_led1,
output reg user_led2,
output reg user_led3,
output reg user_led4,
output reg user_led5,
output reg user_led6,
output reg user_led7
);
//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------
reg main_basesoc_soc_rst = 1'd0;
wire main_basesoc_cpu_rst;
reg [1:0] main_basesoc_reset_storage = 2'd0;
reg main_basesoc_reset_re = 1'd0;
reg [31:0] main_basesoc_scratch_storage = 32'd305419896;
reg main_basesoc_scratch_re = 1'd0;
wire [31:0] main_basesoc_bus_errors_status;
wire main_basesoc_bus_errors_we;
reg main_basesoc_bus_errors_re = 1'd0;
reg main_basesoc_bus_error = 1'd0;
reg [31:0] main_basesoc_bus_errors = 32'd0;
reg [29:0] main_basesoc_ram_bus_adr = 30'd0;
reg [31:0] main_basesoc_ram_bus_dat_w = 32'd0;
wire [31:0] main_basesoc_ram_bus_dat_r;
reg [3:0] main_basesoc_ram_bus_sel = 4'd0;
reg main_basesoc_ram_bus_cyc = 1'd0;
reg main_basesoc_ram_bus_stb = 1'd0;
reg main_basesoc_ram_bus_ack = 1'd0;
reg main_basesoc_ram_bus_we = 1'd0;
wire [10:0] main_basesoc_adr;
wire [31:0] main_basesoc_dat_r;
reg [3:0] main_basesoc_we = 4'd0;
wire [31:0] main_basesoc_dat_w;
wire sys_jtag_clk;
reg sys_jtag_rst = 1'd0;
wire main_basesoc_sink_sink_valid;
wire main_basesoc_sink_sink_ready;
wire main_basesoc_sink_sink_first;
wire main_basesoc_sink_sink_last;
wire [7:0] main_basesoc_sink_sink_payload_data;
wire main_basesoc_source_source_valid;
wire main_basesoc_source_source_ready;
wire main_basesoc_source_source_first;
wire main_basesoc_source_source_last;
wire [7:0] main_basesoc_source_source_payload_data;
reg main_basesoc_valid = 1'd0;
reg [7:0] main_basesoc_data = 8'd0;
reg [2:0] main_basesoc_count = 3'd0;
reg main_basesoc_jtag_reset = 1'd0;
reg main_basesoc_jtag_capture = 1'd0;
wire main_basesoc_jtag_shift;
wire main_basesoc_jtag_update;
wire main_basesoc_jtag_runtest;
wire main_basesoc_jtag_drck;
wire main_basesoc_jtag_sel;
wire main_basesoc_jtag_tck;
wire main_basesoc_jtag_tms;
wire main_basesoc_jtag_tdi;
reg main_basesoc_jtag_tdo = 1'd0;
wire main_basesoc_jtag_altera_reserved_tck;
wire main_basesoc_jtag_altera_reserved_tms;
wire main_basesoc_jtag_altera_reserved_tdi;
wire main_basesoc_jtag_altera_reserved_tdo;
reg main_basesoc_jtag_tdouser = 1'd0;
wire main_basesoc_jtag_tmsutap;
wire main_basesoc_jtag_tckutap;
wire main_basesoc_jtag_tdiutap;
wire jtag_inv_clk;
wire jtag_inv_rst;
reg main_basesoc_jtag_is_ongoing0 = 1'd1;
wire main_basesoc_jtag_TEST_LOGIC_RESET;
reg main_basesoc_jtag_is_ongoing1 = 1'd0;
wire main_basesoc_jtag_RUN_TEST_IDLE;
reg main_basesoc_jtag_is_ongoing2 = 1'd0;
wire main_basesoc_jtag_SELECT_DR_SCAN;
reg main_basesoc_jtag_is_ongoing3 = 1'd0;
wire main_basesoc_jtag_CAPTURE_DR;
reg main_basesoc_jtag_is_ongoing4 = 1'd0;
wire main_basesoc_jtag_SHIFT_DR;
reg main_basesoc_jtag_is_ongoing5 = 1'd0;
wire main_basesoc_jtag_EXIT1_DR;
reg main_basesoc_jtag_is_ongoing6 = 1'd0;
wire main_basesoc_jtag_PAUSE_DR;
reg main_basesoc_jtag_is_ongoing7 = 1'd0;
wire main_basesoc_jtag_EXIT2_DR;
reg main_basesoc_jtag_is_ongoing8 = 1'd0;
wire main_basesoc_jtag_UPDATE_DR;
reg main_basesoc_jtag_is_ongoing9 = 1'd0;
wire main_basesoc_jtag_SELECT_IR_SCAN;
reg main_basesoc_jtag_is_ongoing10 = 1'd0;
wire main_basesoc_jtag_CAPTURE_IR;
reg main_basesoc_jtag_is_ongoing11 = 1'd0;
wire main_basesoc_jtag_SHIFT_IR;
reg main_basesoc_jtag_is_ongoing12 = 1'd0;
wire main_basesoc_jtag_EXIT1_IR;
reg main_basesoc_jtag_is_ongoing13 = 1'd0;
wire main_basesoc_jtag_PAUSE_IR;
reg main_basesoc_jtag_is_ongoing14 = 1'd0;
wire main_basesoc_jtag_EXIT2_IR;
reg main_basesoc_jtag_is_ongoing15 = 1'd0;
wire main_basesoc_jtag_UPDATE_IR;
wire jtag_clk;
wire jtag_rst;
wire main_basesoc_tx_cdc_sink_valid;
wire main_basesoc_tx_cdc_sink_ready;
wire main_basesoc_tx_cdc_sink_first;
wire main_basesoc_tx_cdc_sink_last;
wire [7:0] main_basesoc_tx_cdc_sink_payload_data;
wire main_basesoc_tx_cdc_source_valid;
reg main_basesoc_tx_cdc_source_ready = 1'd0;
wire main_basesoc_tx_cdc_source_first;
wire main_basesoc_tx_cdc_source_last;
wire [7:0] main_basesoc_tx_cdc_source_payload_data;
wire main_basesoc_tx_cdc_asyncfifo_we;
wire main_basesoc_tx_cdc_asyncfifo_writable;
wire main_basesoc_tx_cdc_asyncfifo_re;
wire main_basesoc_tx_cdc_asyncfifo_readable;
wire [9:0] main_basesoc_tx_cdc_asyncfifo_din;
wire [9:0] main_basesoc_tx_cdc_asyncfifo_dout;
wire main_basesoc_tx_cdc_graycounter0_ce;
reg [2:0] main_basesoc_tx_cdc_graycounter0_q = 3'd0;
wire [2:0] main_basesoc_tx_cdc_graycounter0_q_next;
reg [2:0] main_basesoc_tx_cdc_graycounter0_q_binary = 3'd0;
reg [2:0] main_basesoc_tx_cdc_graycounter0_q_next_binary = 3'd0;
wire main_basesoc_tx_cdc_graycounter1_ce;
reg [2:0] main_basesoc_tx_cdc_graycounter1_q = 3'd0;
wire [2:0] main_basesoc_tx_cdc_graycounter1_q_next;
reg [2:0] main_basesoc_tx_cdc_graycounter1_q_binary = 3'd0;
reg [2:0] main_basesoc_tx_cdc_graycounter1_q_next_binary = 3'd0;
wire [2:0] main_basesoc_tx_cdc_produce_rdomain;
wire [2:0] main_basesoc_tx_cdc_consume_wdomain;
wire [1:0] main_basesoc_tx_cdc_wrport_adr;
wire [9:0] main_basesoc_tx_cdc_wrport_dat_r;
wire main_basesoc_tx_cdc_wrport_we;
wire [9:0] main_basesoc_tx_cdc_wrport_dat_w;
wire [1:0] main_basesoc_tx_cdc_rdport_adr;
wire [9:0] main_basesoc_tx_cdc_rdport_dat_r;
wire [7:0] main_basesoc_tx_cdc_fifo_in_payload_data;
wire main_basesoc_tx_cdc_fifo_in_first;
wire main_basesoc_tx_cdc_fifo_in_last;
wire [7:0] main_basesoc_tx_cdc_fifo_out_payload_data;
wire main_basesoc_tx_cdc_fifo_out_first;
wire main_basesoc_tx_cdc_fifo_out_last;
reg main_basesoc_rx_cdc_sink_valid = 1'd0;
wire main_basesoc_rx_cdc_sink_ready;
reg main_basesoc_rx_cdc_sink_first = 1'd0;
reg main_basesoc_rx_cdc_sink_last = 1'd0;
wire [7:0] main_basesoc_rx_cdc_sink_payload_data;
wire main_basesoc_rx_cdc_source_valid;
wire main_basesoc_rx_cdc_source_ready;
wire main_basesoc_rx_cdc_source_first;
wire main_basesoc_rx_cdc_source_last;
wire [7:0] main_basesoc_rx_cdc_source_payload_data;
wire main_basesoc_rx_cdc_asyncfifo_we;
wire main_basesoc_rx_cdc_asyncfifo_writable;
wire main_basesoc_rx_cdc_asyncfifo_re;
wire main_basesoc_rx_cdc_asyncfifo_readable;
wire [9:0] main_basesoc_rx_cdc_asyncfifo_din;
wire [9:0] main_basesoc_rx_cdc_asyncfifo_dout;
wire main_basesoc_rx_cdc_graycounter0_ce;
reg [2:0] main_basesoc_rx_cdc_graycounter0_q = 3'd0;
wire [2:0] main_basesoc_rx_cdc_graycounter0_q_next;
reg [2:0] main_basesoc_rx_cdc_graycounter0_q_binary = 3'd0;
reg [2:0] main_basesoc_rx_cdc_graycounter0_q_next_binary = 3'd0;
wire main_basesoc_rx_cdc_graycounter1_ce;
reg [2:0] main_basesoc_rx_cdc_graycounter1_q = 3'd0;
wire [2:0] main_basesoc_rx_cdc_graycounter1_q_next;
reg [2:0] main_basesoc_rx_cdc_graycounter1_q_binary = 3'd0;
reg [2:0] main_basesoc_rx_cdc_graycounter1_q_next_binary = 3'd0;
wire [2:0] main_basesoc_rx_cdc_produce_rdomain;
wire [2:0] main_basesoc_rx_cdc_consume_wdomain;
wire [1:0] main_basesoc_rx_cdc_wrport_adr;
wire [9:0] main_basesoc_rx_cdc_wrport_dat_r;
wire main_basesoc_rx_cdc_wrport_we;
wire [9:0] main_basesoc_rx_cdc_wrport_dat_w;
wire [1:0] main_basesoc_rx_cdc_rdport_adr;
wire [9:0] main_basesoc_rx_cdc_rdport_dat_r;
wire [7:0] main_basesoc_rx_cdc_fifo_in_payload_data;
wire main_basesoc_rx_cdc_fifo_in_first;
wire main_basesoc_rx_cdc_fifo_in_last;
wire [7:0] main_basesoc_rx_cdc_fifo_out_payload_data;
wire main_basesoc_rx_cdc_fifo_out_first;
wire main_basesoc_rx_cdc_fifo_out_last;
wire main_basesoc_fsm_reset;
reg main_basesoc_uart_rxtx_re = 1'd0;
wire [7:0] main_basesoc_uart_rxtx_r;
reg main_basesoc_uart_rxtx_we = 1'd0;
wire [7:0] main_basesoc_uart_rxtx_w;
wire main_basesoc_uart_txfull_status;
wire main_basesoc_uart_txfull_we;
reg main_basesoc_uart_txfull_re = 1'd0;
wire main_basesoc_uart_rxempty_status;
wire main_basesoc_uart_rxempty_we;
reg main_basesoc_uart_rxempty_re = 1'd0;
wire main_basesoc_uart_irq;
wire main_basesoc_uart_tx_status;
reg main_basesoc_uart_tx_pending = 1'd0;
wire main_basesoc_uart_tx_trigger;
reg main_basesoc_uart_tx_clear = 1'd0;
reg main_basesoc_uart_tx_trigger_d = 1'd0;
wire main_basesoc_uart_rx_status;
reg main_basesoc_uart_rx_pending = 1'd0;
wire main_basesoc_uart_rx_trigger;
reg main_basesoc_uart_rx_clear = 1'd0;
reg main_basesoc_uart_rx_trigger_d = 1'd0;
wire main_basesoc_uart_tx0;
wire main_basesoc_uart_rx0;
reg [1:0] main_basesoc_uart_status_status = 2'd0;
wire main_basesoc_uart_status_we;
reg main_basesoc_uart_status_re = 1'd0;
wire main_basesoc_uart_tx1;
wire main_basesoc_uart_rx1;
reg [1:0] main_basesoc_uart_pending_status = 2'd0;
wire main_basesoc_uart_pending_we;
reg main_basesoc_uart_pending_re = 1'd0;
reg [1:0] main_basesoc_uart_pending_r = 2'd0;
wire main_basesoc_uart_tx2;
wire main_basesoc_uart_rx2;
reg [1:0] main_basesoc_uart_enable_storage = 2'd0;
reg main_basesoc_uart_enable_re = 1'd0;
wire main_basesoc_uart_txempty_status;
wire main_basesoc_uart_txempty_we;
reg main_basesoc_uart_txempty_re = 1'd0;
wire main_basesoc_uart_rxfull_status;
wire main_basesoc_uart_rxfull_we;
reg main_basesoc_uart_rxfull_re = 1'd0;
wire main_basesoc_uart_uart_sink_valid;
wire main_basesoc_uart_uart_sink_ready;
wire main_basesoc_uart_uart_sink_first;
wire main_basesoc_uart_uart_sink_last;
wire [7:0] main_basesoc_uart_uart_sink_payload_data;
wire main_basesoc_uart_uart_source_valid;
wire main_basesoc_uart_uart_source_ready;
wire main_basesoc_uart_uart_source_first;
wire main_basesoc_uart_uart_source_last;
wire [7:0] main_basesoc_uart_uart_source_payload_data;
wire main_basesoc_uart_tx_fifo_sink_valid;
wire main_basesoc_uart_tx_fifo_sink_ready;
reg main_basesoc_uart_tx_fifo_sink_first = 1'd0;
reg main_basesoc_uart_tx_fifo_sink_last = 1'd0;
wire [7:0] main_basesoc_uart_tx_fifo_sink_payload_data;
wire main_basesoc_uart_tx_fifo_source_valid;
wire main_basesoc_uart_tx_fifo_source_ready;
wire main_basesoc_uart_tx_fifo_source_first;
wire main_basesoc_uart_tx_fifo_source_last;
wire [7:0] main_basesoc_uart_tx_fifo_source_payload_data;
wire main_basesoc_uart_tx_fifo_re;
reg main_basesoc_uart_tx_fifo_readable = 1'd0;
wire main_basesoc_uart_tx_fifo_syncfifo_we;
wire main_basesoc_uart_tx_fifo_syncfifo_writable;
wire main_basesoc_uart_tx_fifo_syncfifo_re;
wire main_basesoc_uart_tx_fifo_syncfifo_readable;
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_din;
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_dout;
reg [4:0] main_basesoc_uart_tx_fifo_level0 = 5'd0;
reg main_basesoc_uart_tx_fifo_replace = 1'd0;
reg [3:0] main_basesoc_uart_tx_fifo_produce = 4'd0;
reg [3:0] main_basesoc_uart_tx_fifo_consume = 4'd0;
reg [3:0] main_basesoc_uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_r;
wire main_basesoc_uart_tx_fifo_wrport_we;
wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_w;
wire main_basesoc_uart_tx_fifo_do_read;
wire [3:0] main_basesoc_uart_tx_fifo_rdport_adr;
wire [9:0] main_basesoc_uart_tx_fifo_rdport_dat_r;
wire main_basesoc_uart_tx_fifo_rdport_re;
wire [4:0] main_basesoc_uart_tx_fifo_level1;
wire [7:0] main_basesoc_uart_tx_fifo_fifo_in_payload_data;
wire main_basesoc_uart_tx_fifo_fifo_in_first;
wire main_basesoc_uart_tx_fifo_fifo_in_last;
wire [7:0] main_basesoc_uart_tx_fifo_fifo_out_payload_data;
wire main_basesoc_uart_tx_fifo_fifo_out_first;
wire main_basesoc_uart_tx_fifo_fifo_out_last;
wire main_basesoc_uart_rx_fifo_sink_valid;
wire main_basesoc_uart_rx_fifo_sink_ready;
wire main_basesoc_uart_rx_fifo_sink_first;
wire main_basesoc_uart_rx_fifo_sink_last;
wire [7:0] main_basesoc_uart_rx_fifo_sink_payload_data;
wire main_basesoc_uart_rx_fifo_source_valid;
wire main_basesoc_uart_rx_fifo_source_ready;
wire main_basesoc_uart_rx_fifo_source_first;
wire main_basesoc_uart_rx_fifo_source_last;
wire [7:0] main_basesoc_uart_rx_fifo_source_payload_data;
wire main_basesoc_uart_rx_fifo_re;
reg main_basesoc_uart_rx_fifo_readable = 1'd0;
wire main_basesoc_uart_rx_fifo_syncfifo_we;
wire main_basesoc_uart_rx_fifo_syncfifo_writable;
wire main_basesoc_uart_rx_fifo_syncfifo_re;
wire main_basesoc_uart_rx_fifo_syncfifo_readable;
wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_din;
wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_dout;
reg [4:0] main_basesoc_uart_rx_fifo_level0 = 5'd0;
reg main_basesoc_uart_rx_fifo_replace = 1'd0;
reg [3:0] main_basesoc_uart_rx_fifo_produce = 4'd0;
reg [3:0] main_basesoc_uart_rx_fifo_consume = 4'd0;
reg [3:0] main_basesoc_uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_r;
wire main_basesoc_uart_rx_fifo_wrport_we;
wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_w;
wire main_basesoc_uart_rx_fifo_do_read;
wire [3:0] main_basesoc_uart_rx_fifo_rdport_adr;
wire [9:0] main_basesoc_uart_rx_fifo_rdport_dat_r;
wire main_basesoc_uart_rx_fifo_rdport_re;
wire [4:0] main_basesoc_uart_rx_fifo_level1;
wire [7:0] main_basesoc_uart_rx_fifo_fifo_in_payload_data;
wire main_basesoc_uart_rx_fifo_fifo_in_first;
wire main_basesoc_uart_rx_fifo_fifo_in_last;
wire [7:0] main_basesoc_uart_rx_fifo_fifo_out_payload_data;
wire main_basesoc_uart_rx_fifo_fifo_out_first;
wire main_basesoc_uart_rx_fifo_fifo_out_last;
reg [31:0] main_basesoc_timer_load_storage = 32'd0;
reg main_basesoc_timer_load_re = 1'd0;
reg [31:0] main_basesoc_timer_reload_storage = 32'd0;
reg main_basesoc_timer_reload_re = 1'd0;
reg main_basesoc_timer_en_storage = 1'd0;
reg main_basesoc_timer_en_re = 1'd0;
reg main_basesoc_timer_update_value_storage = 1'd0;
reg main_basesoc_timer_update_value_re = 1'd0;
reg [31:0] main_basesoc_timer_value_status = 32'd0;
wire main_basesoc_timer_value_we;
reg main_basesoc_timer_value_re = 1'd0;
wire main_basesoc_timer_irq;
wire main_basesoc_timer_zero_status;
reg main_basesoc_timer_zero_pending = 1'd0;
wire main_basesoc_timer_zero_trigger;
reg main_basesoc_timer_zero_clear = 1'd0;
reg main_basesoc_timer_zero_trigger_d = 1'd0;
wire main_basesoc_timer_zero0;
wire main_basesoc_timer_status_status;
wire main_basesoc_timer_status_we;
reg main_basesoc_timer_status_re = 1'd0;
wire main_basesoc_timer_zero1;
wire main_basesoc_timer_pending_status;
wire main_basesoc_timer_pending_we;
reg main_basesoc_timer_pending_re = 1'd0;
reg main_basesoc_timer_pending_r = 1'd0;
wire main_basesoc_timer_zero2;
reg main_basesoc_timer_enable_storage = 1'd0;
reg main_basesoc_timer_enable_re = 1'd0;
reg [31:0] main_basesoc_timer_value = 32'd0;
wire main_crg_rst;
wire sys_clk;
wire sys_rst;
wire hdmi_clk;
wire hdmi_rst;
wire main_crg_reset;
wire main_crg_locked;
wire main_crg_clkin;
wire main_crg_clkout0;
wire main_crg_clkout1;
reg [3:0] builder_max10jtag_state = 4'd0;
reg [3:0] builder_max10jtag_next_state = 4'd0;
reg [1:0] builder_resetinserter_state = 2'd0;
reg [1:0] builder_resetinserter_next_state = 2'd0;
reg main_basesoc_valid_next_value0 = 1'd0;
reg main_basesoc_valid_next_value_ce0 = 1'd0;
reg [7:0] main_basesoc_data_next_value1 = 8'd0;
reg main_basesoc_data_next_value_ce1 = 1'd0;
reg [2:0] main_basesoc_count_next_value2 = 3'd0;
reg main_basesoc_count_next_value_ce2 = 1'd0;
wire [1:0] builder_clks;
reg [13:0] builder_basesoc_adr = 14'd0;
reg builder_basesoc_we = 1'd0;
reg [31:0] builder_basesoc_dat_w = 32'd0;
wire [31:0] builder_basesoc_dat_r;
reg [29:0] builder_basesoc_wishbone_adr = 30'd0;
reg [31:0] builder_basesoc_wishbone_dat_w = 32'd0;
reg [31:0] builder_basesoc_wishbone_dat_r = 32'd0;
reg [3:0] builder_basesoc_wishbone_sel = 4'd0;
reg builder_basesoc_wishbone_cyc = 1'd0;
reg builder_basesoc_wishbone_stb = 1'd0;
reg builder_basesoc_wishbone_ack = 1'd0;
reg builder_basesoc_wishbone_we = 1'd0;
wire [13:0] builder_csr_bankarray_interface0_bank_bus_adr;
wire builder_csr_bankarray_interface0_bank_bus_we;
wire [31:0] builder_csr_bankarray_interface0_bank_bus_dat_w;
reg [31:0] builder_csr_bankarray_interface0_bank_bus_dat_r = 32'd0;
reg builder_csr_bankarray_csrbank0_reset0_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank0_reset0_r;
reg builder_csr_bankarray_csrbank0_reset0_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank0_reset0_w;
reg builder_csr_bankarray_csrbank0_scratch0_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_scratch0_r;
reg builder_csr_bankarray_csrbank0_scratch0_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_scratch0_w;
reg builder_csr_bankarray_csrbank0_bus_errors_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_r;
reg builder_csr_bankarray_csrbank0_bus_errors_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_w;
wire builder_csr_bankarray_csrbank0_sel;
wire [13:0] builder_csr_bankarray_sram_bus_adr;
wire builder_csr_bankarray_sram_bus_we;
wire [31:0] builder_csr_bankarray_sram_bus_dat_w;
reg [31:0] builder_csr_bankarray_sram_bus_dat_r = 32'd0;
wire [5:0] builder_csr_bankarray_adr;
wire [7:0] builder_csr_bankarray_dat_r;
wire builder_csr_bankarray_sel;
reg builder_csr_bankarray_sel_r = 1'd0;
wire [13:0] builder_csr_bankarray_interface1_bank_bus_adr;
wire builder_csr_bankarray_interface1_bank_bus_we;
wire [31:0] builder_csr_bankarray_interface1_bank_bus_dat_w;
reg [31:0] builder_csr_bankarray_interface1_bank_bus_dat_r = 32'd0;
reg builder_csr_bankarray_csrbank1_load0_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_load0_r;
reg builder_csr_bankarray_csrbank1_load0_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_load0_w;
reg builder_csr_bankarray_csrbank1_reload0_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_reload0_r;
reg builder_csr_bankarray_csrbank1_reload0_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_reload0_w;
reg builder_csr_bankarray_csrbank1_en0_re = 1'd0;
wire builder_csr_bankarray_csrbank1_en0_r;
reg builder_csr_bankarray_csrbank1_en0_we = 1'd0;
wire builder_csr_bankarray_csrbank1_en0_w;
reg builder_csr_bankarray_csrbank1_update_value0_re = 1'd0;
wire builder_csr_bankarray_csrbank1_update_value0_r;
reg builder_csr_bankarray_csrbank1_update_value0_we = 1'd0;
wire builder_csr_bankarray_csrbank1_update_value0_w;
reg builder_csr_bankarray_csrbank1_value_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_value_r;
reg builder_csr_bankarray_csrbank1_value_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_value_w;
reg builder_csr_bankarray_csrbank1_ev_status_re = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_status_r;
reg builder_csr_bankarray_csrbank1_ev_status_we = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_status_w;
reg builder_csr_bankarray_csrbank1_ev_pending_re = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_pending_r;
reg builder_csr_bankarray_csrbank1_ev_pending_we = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_pending_w;
reg builder_csr_bankarray_csrbank1_ev_enable0_re = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_enable0_r;
reg builder_csr_bankarray_csrbank1_ev_enable0_we = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_enable0_w;
wire builder_csr_bankarray_csrbank1_sel;
wire [13:0] builder_csr_bankarray_interface2_bank_bus_adr;
wire builder_csr_bankarray_interface2_bank_bus_we;
wire [31:0] builder_csr_bankarray_interface2_bank_bus_dat_w;
reg [31:0] builder_csr_bankarray_interface2_bank_bus_dat_r = 32'd0;
reg builder_csr_bankarray_csrbank2_txfull_re = 1'd0;
wire builder_csr_bankarray_csrbank2_txfull_r;
reg builder_csr_bankarray_csrbank2_txfull_we = 1'd0;
wire builder_csr_bankarray_csrbank2_txfull_w;
reg builder_csr_bankarray_csrbank2_rxempty_re = 1'd0;
wire builder_csr_bankarray_csrbank2_rxempty_r;
reg builder_csr_bankarray_csrbank2_rxempty_we = 1'd0;
wire builder_csr_bankarray_csrbank2_rxempty_w;
reg builder_csr_bankarray_csrbank2_ev_status_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_r;
reg builder_csr_bankarray_csrbank2_ev_status_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_w;
reg builder_csr_bankarray_csrbank2_ev_pending_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_pending_r;
reg builder_csr_bankarray_csrbank2_ev_pending_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_pending_w;
reg builder_csr_bankarray_csrbank2_ev_enable0_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_enable0_r;
reg builder_csr_bankarray_csrbank2_ev_enable0_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_enable0_w;
reg builder_csr_bankarray_csrbank2_txempty_re = 1'd0;
wire builder_csr_bankarray_csrbank2_txempty_r;
reg builder_csr_bankarray_csrbank2_txempty_we = 1'd0;
wire builder_csr_bankarray_csrbank2_txempty_w;
reg builder_csr_bankarray_csrbank2_rxfull_re = 1'd0;
wire builder_csr_bankarray_csrbank2_rxfull_r;
reg builder_csr_bankarray_csrbank2_rxfull_we = 1'd0;
wire builder_csr_bankarray_csrbank2_rxfull_w;
wire builder_csr_bankarray_csrbank2_sel;
wire [13:0] builder_csr_interconnect_adr;
wire builder_csr_interconnect_we;
wire [31:0] builder_csr_interconnect_dat_w;
wire [31:0] builder_csr_interconnect_dat_r;
reg builder_state = 1'd0;
reg builder_next_state = 1'd0;
wire [7:0] builder_slice_proxy0;
wire [7:0] builder_slice_proxy1;
wire [7:0] builder_slice_proxy2;
wire [7:0] builder_slice_proxy3;
wire [7:0] builder_slice_proxy4;
wire [7:0] builder_slice_proxy5;
wire [7:0] builder_slice_proxy6;
wire [7:0] builder_slice_proxy7;
wire builder_rst_meta0;
reg [2:0] builder_multiregimpl0_regs0 = 3'd0;
reg [2:0] builder_multiregimpl0_regs1 = 3'd0;
reg [2:0] builder_multiregimpl1_regs0 = 3'd0;
reg [2:0] builder_multiregimpl1_regs1 = 3'd0;
reg [2:0] builder_multiregimpl2_regs0 = 3'd0;
reg [2:0] builder_multiregimpl2_regs1 = 3'd0;
reg [2:0] builder_multiregimpl3_regs0 = 3'd0;
reg [2:0] builder_multiregimpl3_regs1 = 3'd0;
wire builder_rst_meta1;
wire builder_rst_meta2;
//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------
assign sys_jtag_clk = sys_clk;
assign builder_slice_proxy0[0] = gpio[0];
assign builder_slice_proxy1[1] = gpio[1];
assign builder_slice_proxy2[2] = gpio[2];
assign builder_slice_proxy3[3] = gpio[3];
assign builder_slice_proxy4[4] = gpio[4];
assign builder_slice_proxy5[5] = gpio[5];
assign builder_slice_proxy6[6] = gpio[6];
assign builder_slice_proxy7[7] = gpio[7];
assign main_crg_rst = main_basesoc_soc_rst;
assign main_basesoc_bus_errors_status = main_basesoc_bus_errors;
always @(*) begin
main_basesoc_we <= 4'd0;
main_basesoc_we[0] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[0]);
main_basesoc_we[1] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[1]);
main_basesoc_we[2] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[2]);
main_basesoc_we[3] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[3]);
end
assign main_basesoc_adr = main_basesoc_ram_bus_adr[10:0];
assign main_basesoc_ram_bus_dat_r = main_basesoc_dat_r;
assign main_basesoc_dat_w = main_basesoc_ram_bus_dat_w;
assign jtag_clk = main_basesoc_jtag_tck;
assign main_basesoc_tx_cdc_sink_valid = main_basesoc_sink_sink_valid;
assign main_basesoc_sink_sink_ready = main_basesoc_tx_cdc_sink_ready;
assign main_basesoc_tx_cdc_sink_first = main_basesoc_sink_sink_first;
assign main_basesoc_tx_cdc_sink_last = main_basesoc_sink_sink_last;
assign main_basesoc_tx_cdc_sink_payload_data = main_basesoc_sink_sink_payload_data;
assign main_basesoc_source_source_valid = main_basesoc_rx_cdc_source_valid;
assign main_basesoc_rx_cdc_source_ready = main_basesoc_source_source_ready;
assign main_basesoc_source_source_first = main_basesoc_rx_cdc_source_first;
assign main_basesoc_source_source_last = main_basesoc_rx_cdc_source_last;
assign main_basesoc_source_source_payload_data = main_basesoc_rx_cdc_source_payload_data;
assign main_basesoc_fsm_reset = (main_basesoc_jtag_reset | main_basesoc_jtag_capture);
assign main_basesoc_rx_cdc_sink_payload_data = main_basesoc_data;
assign jtag_inv_clk = (~jtag_clk);
assign jtag_inv_rst = jtag_rst;
assign main_basesoc_jtag_altera_reserved_tms = altera_reserved_tms;
assign main_basesoc_jtag_altera_reserved_tck = altera_reserved_tck;
assign main_basesoc_jtag_altera_reserved_tdi = altera_reserved_tdi;
assign altera_reserved_tdo = main_basesoc_jtag_altera_reserved_tdo;
assign main_basesoc_jtag_tck = main_basesoc_jtag_tckutap;
assign main_basesoc_jtag_tms = main_basesoc_jtag_tmsutap;
assign main_basesoc_jtag_tdi = main_basesoc_jtag_tdiutap;
assign main_basesoc_jtag_TEST_LOGIC_RESET = main_basesoc_jtag_is_ongoing0;
assign main_basesoc_jtag_RUN_TEST_IDLE = main_basesoc_jtag_is_ongoing1;
assign main_basesoc_jtag_SELECT_DR_SCAN = main_basesoc_jtag_is_ongoing2;
assign main_basesoc_jtag_CAPTURE_DR = main_basesoc_jtag_is_ongoing3;
assign main_basesoc_jtag_SHIFT_DR = main_basesoc_jtag_is_ongoing4;
assign main_basesoc_jtag_EXIT1_DR = main_basesoc_jtag_is_ongoing5;
assign main_basesoc_jtag_PAUSE_DR = main_basesoc_jtag_is_ongoing6;
assign main_basesoc_jtag_EXIT2_DR = main_basesoc_jtag_is_ongoing7;
assign main_basesoc_jtag_UPDATE_DR = main_basesoc_jtag_is_ongoing8;
assign main_basesoc_jtag_SELECT_IR_SCAN = main_basesoc_jtag_is_ongoing9;
assign main_basesoc_jtag_CAPTURE_IR = main_basesoc_jtag_is_ongoing10;
assign main_basesoc_jtag_SHIFT_IR = main_basesoc_jtag_is_ongoing11;
assign main_basesoc_jtag_EXIT1_IR = main_basesoc_jtag_is_ongoing12;
assign main_basesoc_jtag_PAUSE_IR = main_basesoc_jtag_is_ongoing13;
assign main_basesoc_jtag_EXIT2_IR = main_basesoc_jtag_is_ongoing14;
assign main_basesoc_jtag_UPDATE_IR = main_basesoc_jtag_is_ongoing15;
always @(*) begin
main_basesoc_jtag_is_ongoing12 <= 1'd0;
main_basesoc_jtag_is_ongoing0 <= 1'd1;
main_basesoc_jtag_is_ongoing13 <= 1'd0;
main_basesoc_jtag_is_ongoing1 <= 1'd0;
main_basesoc_jtag_is_ongoing14 <= 1'd0;
builder_max10jtag_next_state <= 4'd0;
main_basesoc_jtag_is_ongoing2 <= 1'd0;
main_basesoc_jtag_is_ongoing15 <= 1'd0;
main_basesoc_jtag_is_ongoing3 <= 1'd0;
main_basesoc_jtag_is_ongoing4 <= 1'd0;
main_basesoc_jtag_is_ongoing5 <= 1'd0;
main_basesoc_jtag_is_ongoing6 <= 1'd0;
main_basesoc_jtag_is_ongoing7 <= 1'd0;
main_basesoc_jtag_is_ongoing8 <= 1'd0;
main_basesoc_jtag_is_ongoing9 <= 1'd0;
main_basesoc_jtag_is_ongoing10 <= 1'd0;
main_basesoc_jtag_is_ongoing11 <= 1'd0;
builder_max10jtag_next_state <= builder_max10jtag_state;
case (builder_max10jtag_state)
1'd1: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 2'd2;
end
main_basesoc_jtag_is_ongoing1 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
2'd2: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 2'd3;
end else begin
builder_max10jtag_next_state <= 4'd9;
end
main_basesoc_jtag_is_ongoing2 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
2'd3: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 3'd4;
end else begin
builder_max10jtag_next_state <= 3'd5;
end
main_basesoc_jtag_is_ongoing3 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd4: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 3'd5;
end
main_basesoc_jtag_is_ongoing4 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd5: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 3'd6;
end else begin
builder_max10jtag_next_state <= 4'd8;
end
main_basesoc_jtag_is_ongoing5 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd6: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 3'd7;
end
main_basesoc_jtag_is_ongoing6 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd7: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd8;
end else begin
builder_max10jtag_next_state <= 3'd4;
end
main_basesoc_jtag_is_ongoing7 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd8: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 2'd2;
end else begin
builder_max10jtag_next_state <= 1'd1;
end
main_basesoc_jtag_is_ongoing8 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd9: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 4'd10;
end else begin
builder_max10jtag_next_state <= 1'd0;
end
main_basesoc_jtag_is_ongoing9 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd10: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 4'd11;
end else begin
builder_max10jtag_next_state <= 4'd12;
end
main_basesoc_jtag_is_ongoing10 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd11: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd12;
end
main_basesoc_jtag_is_ongoing11 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd12: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 4'd13;
end else begin
builder_max10jtag_next_state <= 4'd15;
end
main_basesoc_jtag_is_ongoing12 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd13: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd14;
end
main_basesoc_jtag_is_ongoing13 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd14: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd15;
end else begin
builder_max10jtag_next_state <= 4'd11;
end
main_basesoc_jtag_is_ongoing14 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd15: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 2'd2;
end else begin
builder_max10jtag_next_state <= 1'd1;
end
main_basesoc_jtag_is_ongoing15 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
default: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 1'd1;
end
main_basesoc_jtag_is_ongoing0 <= 1'd1;
end
endcase
end
assign main_basesoc_tx_cdc_asyncfifo_din = {main_basesoc_tx_cdc_fifo_in_last, main_basesoc_tx_cdc_fifo_in_first, main_basesoc_tx_cdc_fifo_in_payload_data};
assign {main_basesoc_tx_cdc_fifo_out_last, main_basesoc_tx_cdc_fifo_out_first, main_basesoc_tx_cdc_fifo_out_payload_data} = main_basesoc_tx_cdc_asyncfifo_dout;
assign main_basesoc_tx_cdc_sink_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_tx_cdc_asyncfifo_we = main_basesoc_tx_cdc_sink_valid;
assign main_basesoc_tx_cdc_fifo_in_first = main_basesoc_tx_cdc_sink_first;
assign main_basesoc_tx_cdc_fifo_in_last = main_basesoc_tx_cdc_sink_last;
assign main_basesoc_tx_cdc_fifo_in_payload_data = main_basesoc_tx_cdc_sink_payload_data;
assign main_basesoc_tx_cdc_source_valid = main_basesoc_tx_cdc_asyncfifo_readable;
assign main_basesoc_tx_cdc_source_first = main_basesoc_tx_cdc_fifo_out_first;
assign main_basesoc_tx_cdc_source_last = main_basesoc_tx_cdc_fifo_out_last;
assign main_basesoc_tx_cdc_source_payload_data = main_basesoc_tx_cdc_fifo_out_payload_data;
assign main_basesoc_tx_cdc_asyncfifo_re = main_basesoc_tx_cdc_source_ready;
assign main_basesoc_tx_cdc_graycounter0_ce = (main_basesoc_tx_cdc_asyncfifo_writable & main_basesoc_tx_cdc_asyncfifo_we);
assign main_basesoc_tx_cdc_graycounter1_ce = (main_basesoc_tx_cdc_asyncfifo_readable & main_basesoc_tx_cdc_asyncfifo_re);
assign main_basesoc_tx_cdc_asyncfifo_writable = (((main_basesoc_tx_cdc_graycounter0_q[2] == main_basesoc_tx_cdc_consume_wdomain[2]) | (main_basesoc_tx_cdc_graycounter0_q[1] == main_basesoc_tx_cdc_consume_wdomain[1])) | (main_basesoc_tx_cdc_graycounter0_q[0] != main_basesoc_tx_cdc_consume_wdomain[0]));
assign main_basesoc_tx_cdc_asyncfifo_readable = (main_basesoc_tx_cdc_graycounter1_q != main_basesoc_tx_cdc_produce_rdomain);
assign main_basesoc_tx_cdc_wrport_adr = main_basesoc_tx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_tx_cdc_wrport_dat_w = main_basesoc_tx_cdc_asyncfifo_din;
assign main_basesoc_tx_cdc_wrport_we = main_basesoc_tx_cdc_graycounter0_ce;
assign main_basesoc_tx_cdc_rdport_adr = main_basesoc_tx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_tx_cdc_asyncfifo_dout = main_basesoc_tx_cdc_rdport_dat_r;
always @(*) begin
main_basesoc_tx_cdc_graycounter0_q_next_binary <= 3'd0;
if (main_basesoc_tx_cdc_graycounter0_ce) begin
main_basesoc_tx_cdc_graycounter0_q_next_binary <= (main_basesoc_tx_cdc_graycounter0_q_binary + 1'd1);
end else begin
main_basesoc_tx_cdc_graycounter0_q_next_binary <= main_basesoc_tx_cdc_graycounter0_q_binary;
end
end
assign main_basesoc_tx_cdc_graycounter0_q_next = (main_basesoc_tx_cdc_graycounter0_q_next_binary ^ main_basesoc_tx_cdc_graycounter0_q_next_binary[2:1]);
always @(*) begin
main_basesoc_tx_cdc_graycounter1_q_next_binary <= 3'd0;
if (main_basesoc_tx_cdc_graycounter1_ce) begin
main_basesoc_tx_cdc_graycounter1_q_next_binary <= (main_basesoc_tx_cdc_graycounter1_q_binary + 1'd1);
end else begin
main_basesoc_tx_cdc_graycounter1_q_next_binary <= main_basesoc_tx_cdc_graycounter1_q_binary;
end
end
assign main_basesoc_tx_cdc_graycounter1_q_next = (main_basesoc_tx_cdc_graycounter1_q_next_binary ^ main_basesoc_tx_cdc_graycounter1_q_next_binary[2:1]);
assign main_basesoc_rx_cdc_asyncfifo_din = {main_basesoc_rx_cdc_fifo_in_last, main_basesoc_rx_cdc_fifo_in_first, main_basesoc_rx_cdc_fifo_in_payload_data};
assign {main_basesoc_rx_cdc_fifo_out_last, main_basesoc_rx_cdc_fifo_out_first, main_basesoc_rx_cdc_fifo_out_payload_data} = main_basesoc_rx_cdc_asyncfifo_dout;
assign main_basesoc_rx_cdc_sink_ready = main_basesoc_rx_cdc_asyncfifo_writable;
assign main_basesoc_rx_cdc_asyncfifo_we = main_basesoc_rx_cdc_sink_valid;
assign main_basesoc_rx_cdc_fifo_in_first = main_basesoc_rx_cdc_sink_first;
assign main_basesoc_rx_cdc_fifo_in_last = main_basesoc_rx_cdc_sink_last;
assign main_basesoc_rx_cdc_fifo_in_payload_data = main_basesoc_rx_cdc_sink_payload_data;
assign main_basesoc_rx_cdc_source_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_rx_cdc_source_first = main_basesoc_rx_cdc_fifo_out_first;
assign main_basesoc_rx_cdc_source_last = main_basesoc_rx_cdc_fifo_out_last;
assign main_basesoc_rx_cdc_source_payload_data = main_basesoc_rx_cdc_fifo_out_payload_data;
assign main_basesoc_rx_cdc_asyncfifo_re = main_basesoc_rx_cdc_source_ready;
assign main_basesoc_rx_cdc_graycounter0_ce = (main_basesoc_rx_cdc_asyncfifo_writable & main_basesoc_rx_cdc_asyncfifo_we);
assign main_basesoc_rx_cdc_graycounter1_ce = (main_basesoc_rx_cdc_asyncfifo_readable & main_basesoc_rx_cdc_asyncfifo_re);
assign main_basesoc_rx_cdc_asyncfifo_writable = (((main_basesoc_rx_cdc_graycounter0_q[2] == main_basesoc_rx_cdc_consume_wdomain[2]) | (main_basesoc_rx_cdc_graycounter0_q[1] == main_basesoc_rx_cdc_consume_wdomain[1])) | (main_basesoc_rx_cdc_graycounter0_q[0] != main_basesoc_rx_cdc_consume_wdomain[0]));
assign main_basesoc_rx_cdc_asyncfifo_readable = (main_basesoc_rx_cdc_graycounter1_q != main_basesoc_rx_cdc_produce_rdomain);
assign main_basesoc_rx_cdc_wrport_adr = main_basesoc_rx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_rx_cdc_wrport_dat_w = main_basesoc_rx_cdc_asyncfifo_din;
assign main_basesoc_rx_cdc_wrport_we = main_basesoc_rx_cdc_graycounter0_ce;
assign main_basesoc_rx_cdc_rdport_adr = main_basesoc_rx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_rx_cdc_asyncfifo_dout = main_basesoc_rx_cdc_rdport_dat_r;
always @(*) begin
main_basesoc_rx_cdc_graycounter0_q_next_binary <= 3'd0;
if (main_basesoc_rx_cdc_graycounter0_ce) begin
main_basesoc_rx_cdc_graycounter0_q_next_binary <= (main_basesoc_rx_cdc_graycounter0_q_binary + 1'd1);
end else begin
main_basesoc_rx_cdc_graycounter0_q_next_binary <= main_basesoc_rx_cdc_graycounter0_q_binary;
end
end
assign main_basesoc_rx_cdc_graycounter0_q_next = (main_basesoc_rx_cdc_graycounter0_q_next_binary ^ main_basesoc_rx_cdc_graycounter0_q_next_binary[2:1]);
always @(*) begin
main_basesoc_rx_cdc_graycounter1_q_next_binary <= 3'd0;
if (main_basesoc_rx_cdc_graycounter1_ce) begin
main_basesoc_rx_cdc_graycounter1_q_next_binary <= (main_basesoc_rx_cdc_graycounter1_q_binary + 1'd1);
end else begin
main_basesoc_rx_cdc_graycounter1_q_next_binary <= main_basesoc_rx_cdc_graycounter1_q_binary;
end
end
assign main_basesoc_rx_cdc_graycounter1_q_next = (main_basesoc_rx_cdc_graycounter1_q_next_binary ^ main_basesoc_rx_cdc_graycounter1_q_next_binary[2:1]);
always @(*) begin
main_basesoc_jtag_tdo <= 1'd0;
builder_resetinserter_next_state <= 2'd0;
main_basesoc_valid_next_value0 <= 1'd0;
main_basesoc_valid_next_value_ce0 <= 1'd0;
main_basesoc_tx_cdc_source_ready <= 1'd0;
main_basesoc_data_next_value1 <= 8'd0;
main_basesoc_data_next_value_ce1 <= 1'd0;
main_basesoc_rx_cdc_sink_valid <= 1'd0;
main_basesoc_count_next_value2 <= 3'd0;
main_basesoc_count_next_value_ce2 <= 1'd0;
builder_resetinserter_next_state <= builder_resetinserter_state;
case (builder_resetinserter_state)
1'd1: begin
main_basesoc_jtag_tdo <= main_basesoc_data;
if (main_basesoc_jtag_shift) begin
main_basesoc_count_next_value2 <= (main_basesoc_count + 1'd1);
main_basesoc_count_next_value_ce2 <= 1'd1;
main_basesoc_data_next_value1 <= {main_basesoc_jtag_tdi, main_basesoc_data[7:1]};
main_basesoc_data_next_value_ce1 <= 1'd1;
if ((main_basesoc_count == 3'd7)) begin
builder_resetinserter_next_state <= 2'd2;
end
end
end
2'd2: begin
main_basesoc_jtag_tdo <= main_basesoc_valid;
if (main_basesoc_jtag_shift) begin
main_basesoc_rx_cdc_sink_valid <= main_basesoc_jtag_tdi;
builder_resetinserter_next_state <= 1'd0;
end
end
default: begin
main_basesoc_jtag_tdo <= main_basesoc_rx_cdc_sink_ready;
if (main_basesoc_jtag_shift) begin
main_basesoc_tx_cdc_source_ready <= main_basesoc_jtag_tdi;
main_basesoc_valid_next_value0 <= main_basesoc_tx_cdc_source_valid;
main_basesoc_valid_next_value_ce0 <= 1'd1;
main_basesoc_data_next_value1 <= main_basesoc_tx_cdc_source_payload_data;
main_basesoc_data_next_value_ce1 <= 1'd1;
main_basesoc_count_next_value2 <= 1'd0;
main_basesoc_count_next_value_ce2 <= 1'd1;
builder_resetinserter_next_state <= 1'd1;
end
end
endcase
end
assign main_basesoc_uart_uart_sink_valid = main_basesoc_source_source_valid;
assign main_basesoc_source_source_ready = main_basesoc_uart_uart_sink_ready;
assign main_basesoc_uart_uart_sink_first = main_basesoc_source_source_first;
assign main_basesoc_uart_uart_sink_last = main_basesoc_source_source_last;
assign main_basesoc_uart_uart_sink_payload_data = main_basesoc_source_source_payload_data;
assign main_basesoc_sink_sink_valid = main_basesoc_uart_uart_source_valid;
assign main_basesoc_uart_uart_source_ready = main_basesoc_sink_sink_ready;
assign main_basesoc_sink_sink_first = main_basesoc_uart_uart_source_first;
assign main_basesoc_sink_sink_last = main_basesoc_uart_uart_source_last;
assign main_basesoc_sink_sink_payload_data = main_basesoc_uart_uart_source_payload_data;
assign main_basesoc_uart_tx_fifo_sink_valid = main_basesoc_uart_rxtx_re;
assign main_basesoc_uart_tx_fifo_sink_payload_data = main_basesoc_uart_rxtx_r;
assign main_basesoc_uart_uart_source_valid = main_basesoc_uart_tx_fifo_source_valid;
assign main_basesoc_uart_tx_fifo_source_ready = main_basesoc_uart_uart_source_ready;
assign main_basesoc_uart_uart_source_first = main_basesoc_uart_tx_fifo_source_first;
assign main_basesoc_uart_uart_source_last = main_basesoc_uart_tx_fifo_source_last;
assign main_basesoc_uart_uart_source_payload_data = main_basesoc_uart_tx_fifo_source_payload_data;
assign main_basesoc_uart_txfull_status = (~main_basesoc_uart_tx_fifo_sink_ready);
assign main_basesoc_uart_txempty_status = (~main_basesoc_uart_tx_fifo_source_valid);
assign main_basesoc_uart_tx_trigger = main_basesoc_uart_tx_fifo_sink_ready;
assign main_basesoc_uart_rx_fifo_sink_valid = main_basesoc_uart_uart_sink_valid;
assign main_basesoc_uart_uart_sink_ready = main_basesoc_uart_rx_fifo_sink_ready;
assign main_basesoc_uart_rx_fifo_sink_first = main_basesoc_uart_uart_sink_first;
assign main_basesoc_uart_rx_fifo_sink_last = main_basesoc_uart_uart_sink_last;
assign main_basesoc_uart_rx_fifo_sink_payload_data = main_basesoc_uart_uart_sink_payload_data;
assign main_basesoc_uart_rxtx_w = main_basesoc_uart_rx_fifo_source_payload_data;
assign main_basesoc_uart_rx_fifo_source_ready = (main_basesoc_uart_rx_clear | (1'd0 & main_basesoc_uart_rxtx_we));
assign main_basesoc_uart_rxempty_status = (~main_basesoc_uart_rx_fifo_source_valid);
assign main_basesoc_uart_rxfull_status = (~main_basesoc_uart_rx_fifo_sink_ready);
assign main_basesoc_uart_rx_trigger = main_basesoc_uart_rx_fifo_source_valid;
assign main_basesoc_uart_tx0 = main_basesoc_uart_tx_status;
assign main_basesoc_uart_tx1 = main_basesoc_uart_tx_pending;
always @(*) begin
main_basesoc_uart_tx_clear <= 1'd0;
if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[0])) begin
main_basesoc_uart_tx_clear <= 1'd1;
end
end
assign main_basesoc_uart_rx0 = main_basesoc_uart_rx_status;
assign main_basesoc_uart_rx1 = main_basesoc_uart_rx_pending;
always @(*) begin
main_basesoc_uart_rx_clear <= 1'd0;
if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[1])) begin
main_basesoc_uart_rx_clear <= 1'd1;
end
end
assign main_basesoc_uart_irq = ((main_basesoc_uart_pending_status[0] & main_basesoc_uart_enable_storage[0]) | (main_basesoc_uart_pending_status[1] & main_basesoc_uart_enable_storage[1]));
assign main_basesoc_uart_tx_status = main_basesoc_uart_tx_trigger;
assign main_basesoc_uart_rx_status = main_basesoc_uart_rx_trigger;
assign main_basesoc_uart_tx_fifo_syncfifo_din = {main_basesoc_uart_tx_fifo_fifo_in_last, main_basesoc_uart_tx_fifo_fifo_in_first, main_basesoc_uart_tx_fifo_fifo_in_payload_data};
assign {main_basesoc_uart_tx_fifo_fifo_out_last, main_basesoc_uart_tx_fifo_fifo_out_first, main_basesoc_uart_tx_fifo_fifo_out_payload_data} = main_basesoc_uart_tx_fifo_syncfifo_dout;
assign main_basesoc_uart_tx_fifo_sink_ready = main_basesoc_uart_tx_fifo_syncfifo_writable;
assign main_basesoc_uart_tx_fifo_syncfifo_we = main_basesoc_uart_tx_fifo_sink_valid;
assign main_basesoc_uart_tx_fifo_fifo_in_first = main_basesoc_uart_tx_fifo_sink_first;
assign main_basesoc_uart_tx_fifo_fifo_in_last = main_basesoc_uart_tx_fifo_sink_last;
assign main_basesoc_uart_tx_fifo_fifo_in_payload_data = main_basesoc_uart_tx_fifo_sink_payload_data;
assign main_basesoc_uart_tx_fifo_source_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_uart_tx_fifo_source_first = main_basesoc_uart_tx_fifo_fifo_out_first;
assign main_basesoc_uart_tx_fifo_source_last = main_basesoc_uart_tx_fifo_fifo_out_last;
assign main_basesoc_uart_tx_fifo_source_payload_data = main_basesoc_uart_tx_fifo_fifo_out_payload_data;
assign main_basesoc_uart_tx_fifo_re = main_basesoc_uart_tx_fifo_source_ready;
assign main_basesoc_uart_tx_fifo_syncfifo_re = (main_basesoc_uart_tx_fifo_syncfifo_readable & ((~main_basesoc_uart_tx_fifo_readable) | main_basesoc_uart_tx_fifo_re));
assign main_basesoc_uart_tx_fifo_level1 = (main_basesoc_uart_tx_fifo_level0 + main_basesoc_uart_tx_fifo_readable);
always @(*) begin
main_basesoc_uart_tx_fifo_wrport_adr <= 4'd0;
if (main_basesoc_uart_tx_fifo_replace) begin
main_basesoc_uart_tx_fifo_wrport_adr <= (main_basesoc_uart_tx_fifo_produce - 1'd1);
end else begin
main_basesoc_uart_tx_fifo_wrport_adr <= main_basesoc_uart_tx_fifo_produce;
end
end
assign main_basesoc_uart_tx_fifo_wrport_dat_w = main_basesoc_uart_tx_fifo_syncfifo_din;
assign main_basesoc_uart_tx_fifo_wrport_we = (main_basesoc_uart_tx_fifo_syncfifo_we & (main_basesoc_uart_tx_fifo_syncfifo_writable | main_basesoc_uart_tx_fifo_replace));
assign main_basesoc_uart_tx_fifo_do_read = (main_basesoc_uart_tx_fifo_syncfifo_readable & main_basesoc_uart_tx_fifo_syncfifo_re);
assign main_basesoc_uart_tx_fifo_rdport_adr = main_basesoc_uart_tx_fifo_consume;
assign main_basesoc_uart_tx_fifo_syncfifo_dout = main_basesoc_uart_tx_fifo_rdport_dat_r;
assign main_basesoc_uart_tx_fifo_rdport_re = main_basesoc_uart_tx_fifo_do_read;
assign main_basesoc_uart_tx_fifo_syncfifo_writable = (main_basesoc_uart_tx_fifo_level0 != 5'h10);
assign main_basesoc_uart_tx_fifo_syncfifo_readable = (main_basesoc_uart_tx_fifo_level0 != 1'd0);
assign main_basesoc_uart_rx_fifo_syncfifo_din = {main_basesoc_uart_rx_fifo_fifo_in_last, main_basesoc_uart_rx_fifo_fifo_in_first, main_basesoc_uart_rx_fifo_fifo_in_payload_data};
assign {main_basesoc_uart_rx_fifo_fifo_out_last, main_basesoc_uart_rx_fifo_fifo_out_first, main_basesoc_uart_rx_fifo_fifo_out_payload_data} = main_basesoc_uart_rx_fifo_syncfifo_dout;
assign main_basesoc_uart_rx_fifo_sink_ready = main_basesoc_uart_rx_fifo_syncfifo_writable;
assign main_basesoc_uart_rx_fifo_syncfifo_we = main_basesoc_uart_rx_fifo_sink_valid;
assign main_basesoc_uart_rx_fifo_fifo_in_first = main_basesoc_uart_rx_fifo_sink_first;
assign main_basesoc_uart_rx_fifo_fifo_in_last = main_basesoc_uart_rx_fifo_sink_last;
assign main_basesoc_uart_rx_fifo_fifo_in_payload_data = main_basesoc_uart_rx_fifo_sink_payload_data;
assign main_basesoc_uart_rx_fifo_source_valid = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_fifo_source_first = main_basesoc_uart_rx_fifo_fifo_out_first;
assign main_basesoc_uart_rx_fifo_source_last = main_basesoc_uart_rx_fifo_fifo_out_last;
assign main_basesoc_uart_rx_fifo_source_payload_data = main_basesoc_uart_rx_fifo_fifo_out_payload_data;
assign main_basesoc_uart_rx_fifo_re = main_basesoc_uart_rx_fifo_source_ready;
assign main_basesoc_uart_rx_fifo_syncfifo_re = (main_basesoc_uart_rx_fifo_syncfifo_readable & ((~main_basesoc_uart_rx_fifo_readable) | main_basesoc_uart_rx_fifo_re));
assign main_basesoc_uart_rx_fifo_level1 = (main_basesoc_uart_rx_fifo_level0 + main_basesoc_uart_rx_fifo_readable);
always @(*) begin
main_basesoc_uart_rx_fifo_wrport_adr <= 4'd0;
if (main_basesoc_uart_rx_fifo_replace) begin
main_basesoc_uart_rx_fifo_wrport_adr <= (main_basesoc_uart_rx_fifo_produce - 1'd1);
end else begin
main_basesoc_uart_rx_fifo_wrport_adr <= main_basesoc_uart_rx_fifo_produce;
end
end
assign main_basesoc_uart_rx_fifo_wrport_dat_w = main_basesoc_uart_rx_fifo_syncfifo_din;
assign main_basesoc_uart_rx_fifo_wrport_we = (main_basesoc_uart_rx_fifo_syncfifo_we & (main_basesoc_uart_rx_fifo_syncfifo_writable | main_basesoc_uart_rx_fifo_replace));
assign main_basesoc_uart_rx_fifo_do_read = (main_basesoc_uart_rx_fifo_syncfifo_readable & main_basesoc_uart_rx_fifo_syncfifo_re);
assign main_basesoc_uart_rx_fifo_rdport_adr = main_basesoc_uart_rx_fifo_consume;
assign main_basesoc_uart_rx_fifo_syncfifo_dout = main_basesoc_uart_rx_fifo_rdport_dat_r;
assign main_basesoc_uart_rx_fifo_rdport_re = main_basesoc_uart_rx_fifo_do_read;
assign main_basesoc_uart_rx_fifo_syncfifo_writable = (main_basesoc_uart_rx_fifo_level0 != 5'h10);
assign main_basesoc_uart_rx_fifo_syncfifo_readable = (main_basesoc_uart_rx_fifo_level0 != 1'd0);
assign main_basesoc_timer_zero_trigger = (main_basesoc_timer_value == 1'd0);
assign main_basesoc_timer_zero0 = main_basesoc_timer_zero_status;
assign main_basesoc_timer_zero1 = main_basesoc_timer_zero_pending;
always @(*) begin
main_basesoc_timer_zero_clear <= 1'd0;
if ((main_basesoc_timer_pending_re & main_basesoc_timer_pending_r)) begin
main_basesoc_timer_zero_clear <= 1'd1;
end
end
assign main_basesoc_timer_irq = (main_basesoc_timer_pending_status & main_basesoc_timer_enable_storage);
assign main_basesoc_timer_zero_status = main_basesoc_timer_zero_trigger;
assign main_crg_reset = main_crg_rst;
assign main_crg_clkin = clk50;
assign sys_clk = main_crg_clkout0;
assign hdmi_clk = main_crg_clkout1;
assign main_crg_clkout0 = builder_clks[0];
assign main_crg_clkout1 = builder_clks[1];
always @(*) begin
builder_basesoc_wishbone_dat_r <= 32'd0;
builder_basesoc_dat_w <= 32'd0;
builder_basesoc_adr <= 14'd0;
builder_basesoc_we <= 1'd0;
builder_basesoc_wishbone_ack <= 1'd0;
builder_next_state <= 1'd0;
builder_next_state <= builder_state;
case (builder_state)
1'd1: begin
builder_basesoc_wishbone_ack <= 1'd1;
builder_basesoc_wishbone_dat_r <= builder_basesoc_dat_r;
builder_next_state <= 1'd0;
end
default: begin
builder_basesoc_dat_w <= builder_basesoc_wishbone_dat_w;
if ((builder_basesoc_wishbone_cyc & builder_basesoc_wishbone_stb)) begin
builder_basesoc_adr <= builder_basesoc_wishbone_adr;
builder_basesoc_we <= (builder_basesoc_wishbone_we & (builder_basesoc_wishbone_sel != 1'd0));
builder_next_state <= 1'd1;
end
end
endcase
end
assign builder_csr_bankarray_csrbank0_sel = (builder_csr_bankarray_interface0_bank_bus_adr[13:9] == 1'd0);
assign builder_csr_bankarray_csrbank0_reset0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank0_reset0_re <= 1'd0;
builder_csr_bankarray_csrbank0_reset0_we <= 1'd0;
if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin
builder_csr_bankarray_csrbank0_reset0_re <= builder_csr_bankarray_interface0_bank_bus_we;
builder_csr_bankarray_csrbank0_reset0_we <= (~builder_csr_bankarray_interface0_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank0_scratch0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank0_scratch0_we <= 1'd0;
builder_csr_bankarray_csrbank0_scratch0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd1))) begin
builder_csr_bankarray_csrbank0_scratch0_re <= builder_csr_bankarray_interface0_bank_bus_we;
builder_csr_bankarray_csrbank0_scratch0_we <= (~builder_csr_bankarray_interface0_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank0_bus_errors_r = builder_csr_bankarray_interface0_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank0_bus_errors_re <= 1'd0;
builder_csr_bankarray_csrbank0_bus_errors_we <= 1'd0;
if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 2'd2))) begin
builder_csr_bankarray_csrbank0_bus_errors_re <= builder_csr_bankarray_interface0_bank_bus_we;
builder_csr_bankarray_csrbank0_bus_errors_we <= (~builder_csr_bankarray_interface0_bank_bus_we);
end
end
always @(*) begin
main_basesoc_soc_rst <= 1'd0;
if (main_basesoc_reset_re) begin
main_basesoc_soc_rst <= main_basesoc_reset_storage[0];
end
end
assign main_basesoc_cpu_rst = main_basesoc_reset_storage[1];
assign builder_csr_bankarray_csrbank0_reset0_w = main_basesoc_reset_storage[1:0];
assign builder_csr_bankarray_csrbank0_scratch0_w = main_basesoc_scratch_storage[31:0];
assign builder_csr_bankarray_csrbank0_bus_errors_w = main_basesoc_bus_errors_status[31:0];
assign main_basesoc_bus_errors_we = builder_csr_bankarray_csrbank0_bus_errors_we;
assign builder_csr_bankarray_sel = (builder_csr_bankarray_sram_bus_adr[13:9] == 1'd1);
always @(*) begin
builder_csr_bankarray_sram_bus_dat_r <= 32'd0;
if (builder_csr_bankarray_sel_r) begin
builder_csr_bankarray_sram_bus_dat_r <= builder_csr_bankarray_dat_r;
end
end
assign builder_csr_bankarray_adr = builder_csr_bankarray_sram_bus_adr[5:0];
assign builder_csr_bankarray_csrbank1_sel = (builder_csr_bankarray_interface1_bank_bus_adr[13:9] == 2'd2);
assign builder_csr_bankarray_csrbank1_load0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank1_load0_we <= 1'd0;
builder_csr_bankarray_csrbank1_load0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin
builder_csr_bankarray_csrbank1_load0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_load0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_reload0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank1_reload0_we <= 1'd0;
builder_csr_bankarray_csrbank1_reload0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin
builder_csr_bankarray_csrbank1_reload0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_reload0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_en0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_en0_re <= 1'd0;
builder_csr_bankarray_csrbank1_en0_we <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin
builder_csr_bankarray_csrbank1_en0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_en0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_update_value0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_update_value0_we <= 1'd0;
builder_csr_bankarray_csrbank1_update_value0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd3))) begin
builder_csr_bankarray_csrbank1_update_value0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_update_value0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_value_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank1_value_re <= 1'd0;
builder_csr_bankarray_csrbank1_value_we <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd4))) begin
builder_csr_bankarray_csrbank1_value_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_value_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_ev_status_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_ev_status_re <= 1'd0;
builder_csr_bankarray_csrbank1_ev_status_we <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd5))) begin
builder_csr_bankarray_csrbank1_ev_status_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_ev_status_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_ev_pending_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_ev_pending_we <= 1'd0;
builder_csr_bankarray_csrbank1_ev_pending_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd6))) begin
builder_csr_bankarray_csrbank1_ev_pending_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_ev_pending_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_ev_enable0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_ev_enable0_we <= 1'd0;
builder_csr_bankarray_csrbank1_ev_enable0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd7))) begin
builder_csr_bankarray_csrbank1_ev_enable0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_ev_enable0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_load0_w = main_basesoc_timer_load_storage[31:0];
assign builder_csr_bankarray_csrbank1_reload0_w = main_basesoc_timer_reload_storage[31:0];
assign builder_csr_bankarray_csrbank1_en0_w = main_basesoc_timer_en_storage;
assign builder_csr_bankarray_csrbank1_update_value0_w = main_basesoc_timer_update_value_storage;
assign builder_csr_bankarray_csrbank1_value_w = main_basesoc_timer_value_status[31:0];
assign main_basesoc_timer_value_we = builder_csr_bankarray_csrbank1_value_we;
assign main_basesoc_timer_status_status = main_basesoc_timer_zero0;
assign builder_csr_bankarray_csrbank1_ev_status_w = main_basesoc_timer_status_status;
assign main_basesoc_timer_status_we = builder_csr_bankarray_csrbank1_ev_status_we;
assign main_basesoc_timer_pending_status = main_basesoc_timer_zero1;
assign builder_csr_bankarray_csrbank1_ev_pending_w = main_basesoc_timer_pending_status;
assign main_basesoc_timer_pending_we = builder_csr_bankarray_csrbank1_ev_pending_we;
assign main_basesoc_timer_zero2 = main_basesoc_timer_enable_storage;
assign builder_csr_bankarray_csrbank1_ev_enable0_w = main_basesoc_timer_enable_storage;
assign builder_csr_bankarray_csrbank2_sel = (builder_csr_bankarray_interface2_bank_bus_adr[13:9] == 2'd3);
assign main_basesoc_uart_rxtx_r = builder_csr_bankarray_interface2_bank_bus_dat_w[7:0];
always @(*) begin
main_basesoc_uart_rxtx_re <= 1'd0;
main_basesoc_uart_rxtx_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin
main_basesoc_uart_rxtx_re <= builder_csr_bankarray_interface2_bank_bus_we;
main_basesoc_uart_rxtx_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_txfull_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_txfull_re <= 1'd0;
builder_csr_bankarray_csrbank2_txfull_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd1))) begin
builder_csr_bankarray_csrbank2_txfull_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_txfull_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_rxempty_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_rxempty_re <= 1'd0;
builder_csr_bankarray_csrbank2_rxempty_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 2'd2))) begin
builder_csr_bankarray_csrbank2_rxempty_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_rxempty_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_ev_status_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank2_ev_status_we <= 1'd0;
builder_csr_bankarray_csrbank2_ev_status_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 2'd3))) begin
builder_csr_bankarray_csrbank2_ev_status_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_ev_status_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_ev_pending_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank2_ev_pending_we <= 1'd0;
builder_csr_bankarray_csrbank2_ev_pending_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd4))) begin
builder_csr_bankarray_csrbank2_ev_pending_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_ev_pending_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_ev_enable0_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank2_ev_enable0_re <= 1'd0;
builder_csr_bankarray_csrbank2_ev_enable0_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd5))) begin
builder_csr_bankarray_csrbank2_ev_enable0_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_ev_enable0_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_txempty_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_txempty_we <= 1'd0;
builder_csr_bankarray_csrbank2_txempty_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd6))) begin
builder_csr_bankarray_csrbank2_txempty_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_txempty_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_rxfull_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_rxfull_we <= 1'd0;
builder_csr_bankarray_csrbank2_rxfull_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd7))) begin
builder_csr_bankarray_csrbank2_rxfull_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_rxfull_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_txfull_w = main_basesoc_uart_txfull_status;
assign main_basesoc_uart_txfull_we = builder_csr_bankarray_csrbank2_txfull_we;
assign builder_csr_bankarray_csrbank2_rxempty_w = main_basesoc_uart_rxempty_status;
assign main_basesoc_uart_rxempty_we = builder_csr_bankarray_csrbank2_rxempty_we;
always @(*) begin
main_basesoc_uart_status_status <= 2'd0;
main_basesoc_uart_status_status[0] <= main_basesoc_uart_tx0;
main_basesoc_uart_status_status[1] <= main_basesoc_uart_rx0;
end
assign builder_csr_bankarray_csrbank2_ev_status_w = main_basesoc_uart_status_status[1:0];
assign main_basesoc_uart_status_we = builder_csr_bankarray_csrbank2_ev_status_we;
always @(*) begin
main_basesoc_uart_pending_status <= 2'd0;
main_basesoc_uart_pending_status[0] <= main_basesoc_uart_tx1;
main_basesoc_uart_pending_status[1] <= main_basesoc_uart_rx1;
end
assign builder_csr_bankarray_csrbank2_ev_pending_w = main_basesoc_uart_pending_status[1:0];
assign main_basesoc_uart_pending_we = builder_csr_bankarray_csrbank2_ev_pending_we;
assign main_basesoc_uart_tx2 = main_basesoc_uart_enable_storage[0];
assign main_basesoc_uart_rx2 = main_basesoc_uart_enable_storage[1];
assign builder_csr_bankarray_csrbank2_ev_enable0_w = main_basesoc_uart_enable_storage[1:0];
assign builder_csr_bankarray_csrbank2_txempty_w = main_basesoc_uart_txempty_status;
assign main_basesoc_uart_txempty_we = builder_csr_bankarray_csrbank2_txempty_we;
assign builder_csr_bankarray_csrbank2_rxfull_w = main_basesoc_uart_rxfull_status;
assign main_basesoc_uart_rxfull_we = builder_csr_bankarray_csrbank2_rxfull_we;
assign builder_csr_interconnect_adr = builder_basesoc_adr;
assign builder_csr_interconnect_we = builder_basesoc_we;
assign builder_csr_interconnect_dat_w = builder_basesoc_dat_w;
assign builder_basesoc_dat_r = builder_csr_interconnect_dat_r;
assign builder_csr_bankarray_interface0_bank_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_interface1_bank_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_interface2_bank_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_sram_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_interface0_bank_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_interface1_bank_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_interface2_bank_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_sram_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_bankarray_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_bankarray_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_bankarray_sram_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_interconnect_dat_r = (((builder_csr_bankarray_interface0_bank_bus_dat_r | builder_csr_bankarray_interface1_bank_bus_dat_r) | builder_csr_bankarray_interface2_bank_bus_dat_r) | builder_csr_bankarray_sram_bus_dat_r);
always @(*) begin
user_led0 <= 1'd0;
user_led1 <= 1'd0;
user_led2 <= 1'd0;
user_led3 <= 1'd0;
user_led4 <= 1'd0;
user_led5 <= 1'd0;
user_led6 <= 1'd0;
user_led7 <= 1'd0;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy0;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy1;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy2;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy3;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy4;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy5;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy6;
{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= builder_slice_proxy7;
end
assign main_basesoc_tx_cdc_produce_rdomain = builder_multiregimpl0_regs1;
assign main_basesoc_tx_cdc_consume_wdomain = builder_multiregimpl1_regs1;
assign main_basesoc_rx_cdc_produce_rdomain = builder_multiregimpl2_regs1;
assign main_basesoc_rx_cdc_consume_wdomain = builder_multiregimpl3_regs1;
//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------
always @(posedge jtag_clk) begin
builder_max10jtag_state <= builder_max10jtag_next_state;
main_basesoc_tx_cdc_graycounter1_q_binary <= main_basesoc_tx_cdc_graycounter1_q_next_binary;
main_basesoc_tx_cdc_graycounter1_q <= main_basesoc_tx_cdc_graycounter1_q_next;
main_basesoc_rx_cdc_graycounter0_q_binary <= main_basesoc_rx_cdc_graycounter0_q_next_binary;
main_basesoc_rx_cdc_graycounter0_q <= main_basesoc_rx_cdc_graycounter0_q_next;
builder_resetinserter_state <= builder_resetinserter_next_state;
if (main_basesoc_valid_next_value_ce0) begin
main_basesoc_valid <= main_basesoc_valid_next_value0;
end
if (main_basesoc_data_next_value_ce1) begin
main_basesoc_data <= main_basesoc_data_next_value1;
end
if (main_basesoc_count_next_value_ce2) begin
main_basesoc_count <= main_basesoc_count_next_value2;
end
if (main_basesoc_fsm_reset) begin
main_basesoc_valid <= 1'd0;
main_basesoc_data <= 8'd0;
main_basesoc_count <= 3'd0;
builder_resetinserter_state <= 2'd0;
end
if (jtag_rst) begin
main_basesoc_valid <= 1'd0;
main_basesoc_data <= 8'd0;
main_basesoc_count <= 3'd0;
main_basesoc_tx_cdc_graycounter1_q <= 3'd0;
main_basesoc_tx_cdc_graycounter1_q_binary <= 3'd0;
main_basesoc_rx_cdc_graycounter0_q <= 3'd0;
main_basesoc_rx_cdc_graycounter0_q_binary <= 3'd0;
builder_max10jtag_state <= 4'd0;
builder_resetinserter_state <= 2'd0;
end
builder_multiregimpl0_regs0 <= main_basesoc_tx_cdc_graycounter0_q;
builder_multiregimpl0_regs1 <= builder_multiregimpl0_regs0;
builder_multiregimpl3_regs0 <= main_basesoc_rx_cdc_graycounter1_q;
builder_multiregimpl3_regs1 <= builder_multiregimpl3_regs0;
end
always @(posedge jtag_inv_clk) begin
main_basesoc_jtag_reset <= main_basesoc_jtag_TEST_LOGIC_RESET;
main_basesoc_jtag_capture <= main_basesoc_jtag_CAPTURE_DR;
main_basesoc_jtag_tdouser <= main_basesoc_jtag_tdo;
if (jtag_inv_rst) begin
main_basesoc_jtag_reset <= 1'd0;
main_basesoc_jtag_capture <= 1'd0;
main_basesoc_jtag_tdouser <= 1'd0;
end
end
always @(posedge sys_clk) begin
if ((main_basesoc_bus_errors != 32'hffffffff)) begin
if (main_basesoc_bus_error) begin
main_basesoc_bus_errors <= (main_basesoc_bus_errors + 1'd1);
end
end
main_basesoc_ram_bus_ack <= 1'd0;
if (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & (~main_basesoc_ram_bus_ack))) begin
main_basesoc_ram_bus_ack <= 1'd1;
end
if (main_basesoc_uart_tx_clear) begin
main_basesoc_uart_tx_pending <= 1'd0;
end
main_basesoc_uart_tx_trigger_d <= main_basesoc_uart_tx_trigger;
if ((main_basesoc_uart_tx_trigger & (~main_basesoc_uart_tx_trigger_d))) begin
main_basesoc_uart_tx_pending <= 1'd1;
end
if (main_basesoc_uart_rx_clear) begin
main_basesoc_uart_rx_pending <= 1'd0;
end
main_basesoc_uart_rx_trigger_d <= main_basesoc_uart_rx_trigger;
if ((main_basesoc_uart_rx_trigger & (~main_basesoc_uart_rx_trigger_d))) begin
main_basesoc_uart_rx_pending <= 1'd1;
end
if (main_basesoc_uart_tx_fifo_syncfifo_re) begin
main_basesoc_uart_tx_fifo_readable <= 1'd1;
end else begin
if (main_basesoc_uart_tx_fifo_re) begin
main_basesoc_uart_tx_fifo_readable <= 1'd0;
end
end
if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin
main_basesoc_uart_tx_fifo_produce <= (main_basesoc_uart_tx_fifo_produce + 1'd1);
end
if (main_basesoc_uart_tx_fifo_do_read) begin
main_basesoc_uart_tx_fifo_consume <= (main_basesoc_uart_tx_fifo_consume + 1'd1);
end
if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin
if ((~main_basesoc_uart_tx_fifo_do_read)) begin
main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (main_basesoc_uart_tx_fifo_do_read) begin
main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 - 1'd1);
end
end
if (main_basesoc_uart_rx_fifo_syncfifo_re) begin
main_basesoc_uart_rx_fifo_readable <= 1'd1;
end else begin
if (main_basesoc_uart_rx_fifo_re) begin
main_basesoc_uart_rx_fifo_readable <= 1'd0;
end
end
if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin
main_basesoc_uart_rx_fifo_produce <= (main_basesoc_uart_rx_fifo_produce + 1'd1);
end
if (main_basesoc_uart_rx_fifo_do_read) begin
main_basesoc_uart_rx_fifo_consume <= (main_basesoc_uart_rx_fifo_consume + 1'd1);
end
if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin
if ((~main_basesoc_uart_rx_fifo_do_read)) begin
main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (main_basesoc_uart_rx_fifo_do_read) begin
main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 - 1'd1);
end
end
if (main_basesoc_timer_en_storage) begin
if ((main_basesoc_timer_value == 1'd0)) begin
main_basesoc_timer_value <= main_basesoc_timer_reload_storage;
end else begin
main_basesoc_timer_value <= (main_basesoc_timer_value - 1'd1);
end
end else begin
main_basesoc_timer_value <= main_basesoc_timer_load_storage;
end
if (main_basesoc_timer_update_value_re) begin
main_basesoc_timer_value_status <= main_basesoc_timer_value;
end
if (main_basesoc_timer_zero_clear) begin
main_basesoc_timer_zero_pending <= 1'd0;
end
main_basesoc_timer_zero_trigger_d <= main_basesoc_timer_zero_trigger;
if ((main_basesoc_timer_zero_trigger & (~main_basesoc_timer_zero_trigger_d))) begin
main_basesoc_timer_zero_pending <= 1'd1;
end
builder_state <= builder_next_state;
builder_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0;
if (builder_csr_bankarray_csrbank0_sel) begin
case (builder_csr_bankarray_interface0_bank_bus_adr[8:0])
1'd0: begin
builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_reset0_w;
end
1'd1: begin
builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_scratch0_w;
end
2'd2: begin
builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_bus_errors_w;
end
endcase
end
if (builder_csr_bankarray_csrbank0_reset0_re) begin
main_basesoc_reset_storage[1:0] <= builder_csr_bankarray_csrbank0_reset0_r;
end
main_basesoc_reset_re <= builder_csr_bankarray_csrbank0_reset0_re;
if (builder_csr_bankarray_csrbank0_scratch0_re) begin
main_basesoc_scratch_storage[31:0] <= builder_csr_bankarray_csrbank0_scratch0_r;
end
main_basesoc_scratch_re <= builder_csr_bankarray_csrbank0_scratch0_re;
main_basesoc_bus_errors_re <= builder_csr_bankarray_csrbank0_bus_errors_re;
builder_csr_bankarray_sel_r <= builder_csr_bankarray_sel;
builder_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0;
if (builder_csr_bankarray_csrbank1_sel) begin
case (builder_csr_bankarray_interface1_bank_bus_adr[8:0])
1'd0: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_load0_w;
end
1'd1: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_reload0_w;
end
2'd2: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_en0_w;
end
2'd3: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_update_value0_w;
end
3'd4: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_value_w;
end
3'd5: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_ev_status_w;
end
3'd6: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_ev_pending_w;
end
3'd7: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_ev_enable0_w;
end
endcase
end
if (builder_csr_bankarray_csrbank1_load0_re) begin
main_basesoc_timer_load_storage[31:0] <= builder_csr_bankarray_csrbank1_load0_r;
end
main_basesoc_timer_load_re <= builder_csr_bankarray_csrbank1_load0_re;
if (builder_csr_bankarray_csrbank1_reload0_re) begin
main_basesoc_timer_reload_storage[31:0] <= builder_csr_bankarray_csrbank1_reload0_r;
end
main_basesoc_timer_reload_re <= builder_csr_bankarray_csrbank1_reload0_re;
if (builder_csr_bankarray_csrbank1_en0_re) begin
main_basesoc_timer_en_storage <= builder_csr_bankarray_csrbank1_en0_r;
end
main_basesoc_timer_en_re <= builder_csr_bankarray_csrbank1_en0_re;
if (builder_csr_bankarray_csrbank1_update_value0_re) begin
main_basesoc_timer_update_value_storage <= builder_csr_bankarray_csrbank1_update_value0_r;
end
main_basesoc_timer_update_value_re <= builder_csr_bankarray_csrbank1_update_value0_re;
main_basesoc_timer_value_re <= builder_csr_bankarray_csrbank1_value_re;
main_basesoc_timer_status_re <= builder_csr_bankarray_csrbank1_ev_status_re;
if (builder_csr_bankarray_csrbank1_ev_pending_re) begin
main_basesoc_timer_pending_r <= builder_csr_bankarray_csrbank1_ev_pending_r;
end
main_basesoc_timer_pending_re <= builder_csr_bankarray_csrbank1_ev_pending_re;
if (builder_csr_bankarray_csrbank1_ev_enable0_re) begin
main_basesoc_timer_enable_storage <= builder_csr_bankarray_csrbank1_ev_enable0_r;
end
main_basesoc_timer_enable_re <= builder_csr_bankarray_csrbank1_ev_enable0_re;
builder_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0;
if (builder_csr_bankarray_csrbank2_sel) begin
case (builder_csr_bankarray_interface2_bank_bus_adr[8:0])
1'd0: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= main_basesoc_uart_rxtx_w;
end
1'd1: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_txfull_w;
end
2'd2: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_rxempty_w;
end
2'd3: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_ev_status_w;
end
3'd4: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_ev_pending_w;
end
3'd5: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_ev_enable0_w;
end
3'd6: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_txempty_w;
end
3'd7: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_rxfull_w;
end
endcase
end
main_basesoc_uart_txfull_re <= builder_csr_bankarray_csrbank2_txfull_re;
main_basesoc_uart_rxempty_re <= builder_csr_bankarray_csrbank2_rxempty_re;
main_basesoc_uart_status_re <= builder_csr_bankarray_csrbank2_ev_status_re;
if (builder_csr_bankarray_csrbank2_ev_pending_re) begin
main_basesoc_uart_pending_r[1:0] <= builder_csr_bankarray_csrbank2_ev_pending_r;
end
main_basesoc_uart_pending_re <= builder_csr_bankarray_csrbank2_ev_pending_re;
if (builder_csr_bankarray_csrbank2_ev_enable0_re) begin
main_basesoc_uart_enable_storage[1:0] <= builder_csr_bankarray_csrbank2_ev_enable0_r;
end
main_basesoc_uart_enable_re <= builder_csr_bankarray_csrbank2_ev_enable0_re;
main_basesoc_uart_txempty_re <= builder_csr_bankarray_csrbank2_txempty_re;
main_basesoc_uart_rxfull_re <= builder_csr_bankarray_csrbank2_rxfull_re;
if (sys_rst) begin
main_basesoc_reset_storage <= 2'd0;
main_basesoc_reset_re <= 1'd0;
main_basesoc_scratch_storage <= 32'd305419896;
main_basesoc_scratch_re <= 1'd0;
main_basesoc_bus_errors_re <= 1'd0;
main_basesoc_bus_errors <= 32'd0;
main_basesoc_ram_bus_ack <= 1'd0;
main_basesoc_uart_txfull_re <= 1'd0;
main_basesoc_uart_rxempty_re <= 1'd0;
main_basesoc_uart_tx_pending <= 1'd0;
main_basesoc_uart_tx_trigger_d <= 1'd0;
main_basesoc_uart_rx_pending <= 1'd0;
main_basesoc_uart_rx_trigger_d <= 1'd0;
main_basesoc_uart_status_re <= 1'd0;
main_basesoc_uart_pending_re <= 1'd0;
main_basesoc_uart_pending_r <= 2'd0;
main_basesoc_uart_enable_storage <= 2'd0;
main_basesoc_uart_enable_re <= 1'd0;
main_basesoc_uart_txempty_re <= 1'd0;
main_basesoc_uart_rxfull_re <= 1'd0;
main_basesoc_uart_tx_fifo_readable <= 1'd0;
main_basesoc_uart_tx_fifo_level0 <= 5'd0;
main_basesoc_uart_tx_fifo_produce <= 4'd0;
main_basesoc_uart_tx_fifo_consume <= 4'd0;
main_basesoc_uart_rx_fifo_readable <= 1'd0;
main_basesoc_uart_rx_fifo_level0 <= 5'd0;
main_basesoc_uart_rx_fifo_produce <= 4'd0;
main_basesoc_uart_rx_fifo_consume <= 4'd0;
main_basesoc_timer_load_storage <= 32'd0;
main_basesoc_timer_load_re <= 1'd0;
main_basesoc_timer_reload_storage <= 32'd0;
main_basesoc_timer_reload_re <= 1'd0;
main_basesoc_timer_en_storage <= 1'd0;
main_basesoc_timer_en_re <= 1'd0;
main_basesoc_timer_update_value_storage <= 1'd0;
main_basesoc_timer_update_value_re <= 1'd0;
main_basesoc_timer_value_status <= 32'd0;
main_basesoc_timer_value_re <= 1'd0;
main_basesoc_timer_zero_pending <= 1'd0;
main_basesoc_timer_zero_trigger_d <= 1'd0;
main_basesoc_timer_status_re <= 1'd0;
main_basesoc_timer_pending_re <= 1'd0;
main_basesoc_timer_pending_r <= 1'd0;
main_basesoc_timer_enable_storage <= 1'd0;
main_basesoc_timer_enable_re <= 1'd0;
main_basesoc_timer_value <= 32'd0;
builder_csr_bankarray_sel_r <= 1'd0;
builder_state <= 1'd0;
end
end
always @(posedge sys_jtag_clk) begin
main_basesoc_tx_cdc_graycounter0_q_binary <= main_basesoc_tx_cdc_graycounter0_q_next_binary;
main_basesoc_tx_cdc_graycounter0_q <= main_basesoc_tx_cdc_graycounter0_q_next;
main_basesoc_rx_cdc_graycounter1_q_binary <= main_basesoc_rx_cdc_graycounter1_q_next_binary;
main_basesoc_rx_cdc_graycounter1_q <= main_basesoc_rx_cdc_graycounter1_q_next;
if (sys_jtag_rst) begin
main_basesoc_tx_cdc_graycounter0_q <= 3'd0;
main_basesoc_tx_cdc_graycounter0_q_binary <= 3'd0;
main_basesoc_rx_cdc_graycounter1_q <= 3'd0;
main_basesoc_rx_cdc_graycounter1_q_binary <= 3'd0;
end
builder_multiregimpl1_regs0 <= main_basesoc_tx_cdc_graycounter1_q;
builder_multiregimpl1_regs1 <= builder_multiregimpl1_regs0;
builder_multiregimpl2_regs0 <= main_basesoc_rx_cdc_graycounter0_q;
builder_multiregimpl2_regs1 <= builder_multiregimpl2_regs0;
end
//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Memory mem: 2048-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
reg [31:0] mem[0:2047];
initial begin
$readmemh("mem.init", mem);
end
reg [10:0] mem_adr0;
always @(posedge sys_clk) begin
if (main_basesoc_we[0])
mem[main_basesoc_adr][7:0] <= main_basesoc_dat_w[7:0];
if (main_basesoc_we[1])
mem[main_basesoc_adr][15:8] <= main_basesoc_dat_w[15:8];
if (main_basesoc_we[2])
mem[main_basesoc_adr][23:16] <= main_basesoc_dat_w[23:16];
if (main_basesoc_we[3])
mem[main_basesoc_adr][31:24] <= main_basesoc_dat_w[31:24];
mem_adr0 <= main_basesoc_adr;
end
assign main_basesoc_dat_r = mem[mem_adr0];
//------------------------------------------------------------------------------
// Memory mem_1: 46-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: ---- |
reg [7:0] mem_1[0:45];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [5:0] mem_1_adr0;
always @(posedge sys_clk) begin
mem_1_adr0 <= builder_csr_bankarray_adr;
end
assign builder_csr_bankarray_dat_r = mem_1[mem_1_adr0];
fiftyfivenm_jtag fiftyfivenm_jtag(
.tck(main_basesoc_jtag_altera_reserved_tck),
.tdi(main_basesoc_jtag_altera_reserved_tdi),
.tdouser(main_basesoc_jtag_tdouser),
.tms(main_basesoc_jtag_altera_reserved_tms),
.clkdruser(main_basesoc_jtag_drck),
.runidleuser(main_basesoc_jtag_runtest),
.shiftuser(main_basesoc_jtag_shift),
.tckutap(main_basesoc_jtag_tckutap),
.tdiutap(main_basesoc_jtag_tdiutap),
.tdo(main_basesoc_jtag_altera_reserved_tdo),
.tmsutap(main_basesoc_jtag_tmsutap),
.updateuser(main_basesoc_jtag_update),
.usr1user(main_basesoc_jtag_sel)
);
//------------------------------------------------------------------------------
// Memory storage: 4-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage[0:3];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
always @(posedge sys_jtag_clk) begin
if (main_basesoc_tx_cdc_wrport_we)
storage[main_basesoc_tx_cdc_wrport_adr] <= main_basesoc_tx_cdc_wrport_dat_w;
storage_dat0 <= storage[main_basesoc_tx_cdc_wrport_adr];
end
always @(posedge jtag_clk) begin
storage_dat1 <= storage[main_basesoc_tx_cdc_rdport_adr];
end
assign main_basesoc_tx_cdc_wrport_dat_r = storage_dat0;
assign main_basesoc_tx_cdc_rdport_dat_r = storage_dat1;
//------------------------------------------------------------------------------
// Memory storage_1: 4-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_1[0:3];
reg [9:0] storage_1_dat0;
reg [9:0] storage_1_dat1;
always @(posedge jtag_clk) begin
if (main_basesoc_rx_cdc_wrport_we)
storage_1[main_basesoc_rx_cdc_wrport_adr] <= main_basesoc_rx_cdc_wrport_dat_w;
storage_1_dat0 <= storage_1[main_basesoc_rx_cdc_wrport_adr];
end
always @(posedge sys_jtag_clk) begin
storage_1_dat1 <= storage_1[main_basesoc_rx_cdc_rdport_adr];
end
assign main_basesoc_rx_cdc_wrport_dat_r = storage_1_dat0;
assign main_basesoc_rx_cdc_rdport_dat_r = storage_1_dat1;
//------------------------------------------------------------------------------
// Memory storage_2: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_2[0:15];
reg [9:0] storage_2_dat0;
reg [9:0] storage_2_dat1;
always @(posedge sys_clk) begin
if (main_basesoc_uart_tx_fifo_wrport_we)
storage_2[main_basesoc_uart_tx_fifo_wrport_adr] <= main_basesoc_uart_tx_fifo_wrport_dat_w;
storage_2_dat0 <= storage_2[main_basesoc_uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_basesoc_uart_tx_fifo_rdport_re)
storage_2_dat1 <= storage_2[main_basesoc_uart_tx_fifo_rdport_adr];
end
assign main_basesoc_uart_tx_fifo_wrport_dat_r = storage_2_dat0;
assign main_basesoc_uart_tx_fifo_rdport_dat_r = storage_2_dat1;
//------------------------------------------------------------------------------
// Memory storage_3: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_3[0:15];
reg [9:0] storage_3_dat0;
reg [9:0] storage_3_dat1;
always @(posedge sys_clk) begin
if (main_basesoc_uart_rx_fifo_wrport_we)
storage_3[main_basesoc_uart_rx_fifo_wrport_adr] <= main_basesoc_uart_rx_fifo_wrport_dat_w;
storage_3_dat0 <= storage_3[main_basesoc_uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_basesoc_uart_rx_fifo_rdport_re)
storage_3_dat1 <= storage_3[main_basesoc_uart_rx_fifo_rdport_adr];
end
assign main_basesoc_uart_rx_fifo_wrport_dat_r = storage_3_dat0;
assign main_basesoc_uart_rx_fifo_rdport_dat_r = storage_3_dat1;
ALTPLL #(
.BANDWIDTH_TYPE("AUTO"),
.CLK0_DIVIDE_BY(5'd25),
.CLK0_DUTY_CYCLE(6'd50),
.CLK0_MULTIPLY_BY(5'd25),
.CLK0_PHASE_SHIFT(1'd0),
.CLK1_DIVIDE_BY(5'd31),
.CLK1_DUTY_CYCLE(6'd50),
.CLK1_MULTIPLY_BY(5'd25),
.CLK1_PHASE_SHIFT(1'd0),
.COMPENSATE_CLOCK("CLK0"),
.INCLK0_INPUT_FREQUENCY(15'd20000),
.OPERATION_MODE("NORMAL")
) ALTPLL (
.ARESET(1'd0),
.CLKENA(5'd31),
.EXTCLKENA(4'd15),
.FBIN(1'd1),
.INCLK(main_crg_clkin),
.PFDENA(1'd1),
.PLLENA(1'd1),
.CLK(builder_clks),
.LOCKED(main_crg_locked)
);
DFF DFF(
.clk(jtag_clk),
.clrn(1'd1),
.d(1'd0),
.prn((~sys_jtag_rst)),
.q(builder_rst_meta0)
);
DFF DFF_1(
.clk(jtag_clk),
.clrn(1'd1),
.d(builder_rst_meta0),
.prn((~sys_jtag_rst)),
.q(jtag_rst)
);
DFF DFF_2(
.clk(sys_clk),
.clrn(1'd1),
.d(1'd0),
.prn((~(~main_crg_locked))),
.q(builder_rst_meta1)
);
DFF DFF_3(
.clk(sys_clk),
.clrn(1'd1),
.d(builder_rst_meta1),
.prn((~(~main_crg_locked))),
.q(sys_rst)
);
DFF DFF_4(
.clk(hdmi_clk),
.clrn(1'd1),
.d(1'd0),
.prn((~(~main_crg_locked))),
.q(builder_rst_meta2)
);
DFF DFF_5(
.clk(hdmi_clk),
.clrn(1'd1),
.d(builder_rst_meta2),
.prn((~(~main_crg_locked))),
.q(hdmi_rst)
);
endmodule
// -----------------------------------------------------------------------------
// Auto-Generated by LiteX on 2022-02-08 16:32:20.
//------------------------------------------------------------------------------
Raw
request_loop.v
// -----------------------------------------------------------------------------
// Auto-Generated by: __ _ __ _ __
// / / (_) /____ | |/_/
// / /__/ / __/ -_)> <
// /____/_/\__/\__/_/|_|
// Build your hardware, easily!
// https://github.com/enjoy-digital/litex
//
// Filename : terasic_deca.v
// Device : 10M50DAF484C6GES
// LiteX sha1 : 145c74f7
// Date : 2022-02-08 16:31:25
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------
module terasic_deca (
input wire altera_reserved_tms,
input wire altera_reserved_tck,
input wire altera_reserved_tdi,
output wire altera_reserved_tdo,
input wire clk50,
input wire [43:0] gpio,
output wire user_led,
output wire user_led_1,
output wire user_led_2,
output wire user_led_3,
output wire user_led_4,
output wire user_led_5,
output wire user_led_6,
output wire user_led_7
);
//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------
reg main_basesoc_soc_rst = 1'd0;
wire main_basesoc_cpu_rst;
reg [1:0] main_basesoc_reset_storage = 2'd0;
reg main_basesoc_reset_re = 1'd0;
reg [31:0] main_basesoc_scratch_storage = 32'd305419896;
reg main_basesoc_scratch_re = 1'd0;
wire [31:0] main_basesoc_bus_errors_status;
wire main_basesoc_bus_errors_we;
reg main_basesoc_bus_errors_re = 1'd0;
reg main_basesoc_bus_error = 1'd0;
reg [31:0] main_basesoc_bus_errors = 32'd0;
reg [29:0] main_basesoc_ram_bus_adr = 30'd0;
reg [31:0] main_basesoc_ram_bus_dat_w = 32'd0;
wire [31:0] main_basesoc_ram_bus_dat_r;
reg [3:0] main_basesoc_ram_bus_sel = 4'd0;
reg main_basesoc_ram_bus_cyc = 1'd0;
reg main_basesoc_ram_bus_stb = 1'd0;
reg main_basesoc_ram_bus_ack = 1'd0;
reg main_basesoc_ram_bus_we = 1'd0;
wire [10:0] main_basesoc_adr;
wire [31:0] main_basesoc_dat_r;
reg [3:0] main_basesoc_we = 4'd0;
wire [31:0] main_basesoc_dat_w;
wire sys_jtag_clk;
reg sys_jtag_rst = 1'd0;
wire main_basesoc_sink_sink_valid;
wire main_basesoc_sink_sink_ready;
wire main_basesoc_sink_sink_first;
wire main_basesoc_sink_sink_last;
wire [7:0] main_basesoc_sink_sink_payload_data;
wire main_basesoc_source_source_valid;
wire main_basesoc_source_source_ready;
wire main_basesoc_source_source_first;
wire main_basesoc_source_source_last;
wire [7:0] main_basesoc_source_source_payload_data;
reg main_basesoc_valid = 1'd0;
reg [7:0] main_basesoc_data = 8'd0;
reg [2:0] main_basesoc_count = 3'd0;
reg main_basesoc_jtag_reset = 1'd0;
reg main_basesoc_jtag_capture = 1'd0;
wire main_basesoc_jtag_shift;
wire main_basesoc_jtag_update;
wire main_basesoc_jtag_runtest;
wire main_basesoc_jtag_drck;
wire main_basesoc_jtag_sel;
wire main_basesoc_jtag_tck;
wire main_basesoc_jtag_tms;
wire main_basesoc_jtag_tdi;
reg main_basesoc_jtag_tdo = 1'd0;
wire main_basesoc_jtag_altera_reserved_tck;
wire main_basesoc_jtag_altera_reserved_tms;
wire main_basesoc_jtag_altera_reserved_tdi;
wire main_basesoc_jtag_altera_reserved_tdo;
reg main_basesoc_jtag_tdouser = 1'd0;
wire main_basesoc_jtag_tmsutap;
wire main_basesoc_jtag_tckutap;
wire main_basesoc_jtag_tdiutap;
wire jtag_inv_clk;
wire jtag_inv_rst;
reg main_basesoc_jtag_is_ongoing0 = 1'd1;
wire main_basesoc_jtag_TEST_LOGIC_RESET;
reg main_basesoc_jtag_is_ongoing1 = 1'd0;
wire main_basesoc_jtag_RUN_TEST_IDLE;
reg main_basesoc_jtag_is_ongoing2 = 1'd0;
wire main_basesoc_jtag_SELECT_DR_SCAN;
reg main_basesoc_jtag_is_ongoing3 = 1'd0;
wire main_basesoc_jtag_CAPTURE_DR;
reg main_basesoc_jtag_is_ongoing4 = 1'd0;
wire main_basesoc_jtag_SHIFT_DR;
reg main_basesoc_jtag_is_ongoing5 = 1'd0;
wire main_basesoc_jtag_EXIT1_DR;
reg main_basesoc_jtag_is_ongoing6 = 1'd0;
wire main_basesoc_jtag_PAUSE_DR;
reg main_basesoc_jtag_is_ongoing7 = 1'd0;
wire main_basesoc_jtag_EXIT2_DR;
reg main_basesoc_jtag_is_ongoing8 = 1'd0;
wire main_basesoc_jtag_UPDATE_DR;
reg main_basesoc_jtag_is_ongoing9 = 1'd0;
wire main_basesoc_jtag_SELECT_IR_SCAN;
reg main_basesoc_jtag_is_ongoing10 = 1'd0;
wire main_basesoc_jtag_CAPTURE_IR;
reg main_basesoc_jtag_is_ongoing11 = 1'd0;
wire main_basesoc_jtag_SHIFT_IR;
reg main_basesoc_jtag_is_ongoing12 = 1'd0;
wire main_basesoc_jtag_EXIT1_IR;
reg main_basesoc_jtag_is_ongoing13 = 1'd0;
wire main_basesoc_jtag_PAUSE_IR;
reg main_basesoc_jtag_is_ongoing14 = 1'd0;
wire main_basesoc_jtag_EXIT2_IR;
reg main_basesoc_jtag_is_ongoing15 = 1'd0;
wire main_basesoc_jtag_UPDATE_IR;
wire jtag_clk;
wire jtag_rst;
wire main_basesoc_tx_cdc_sink_valid;
wire main_basesoc_tx_cdc_sink_ready;
wire main_basesoc_tx_cdc_sink_first;
wire main_basesoc_tx_cdc_sink_last;
wire [7:0] main_basesoc_tx_cdc_sink_payload_data;
wire main_basesoc_tx_cdc_source_valid;
reg main_basesoc_tx_cdc_source_ready = 1'd0;
wire main_basesoc_tx_cdc_source_first;
wire main_basesoc_tx_cdc_source_last;
wire [7:0] main_basesoc_tx_cdc_source_payload_data;
wire main_basesoc_tx_cdc_asyncfifo_we;
wire main_basesoc_tx_cdc_asyncfifo_writable;
wire main_basesoc_tx_cdc_asyncfifo_re;
wire main_basesoc_tx_cdc_asyncfifo_readable;
wire [9:0] main_basesoc_tx_cdc_asyncfifo_din;
wire [9:0] main_basesoc_tx_cdc_asyncfifo_dout;
wire main_basesoc_tx_cdc_graycounter0_ce;
reg [2:0] main_basesoc_tx_cdc_graycounter0_q = 3'd0;
wire [2:0] main_basesoc_tx_cdc_graycounter0_q_next;
reg [2:0] main_basesoc_tx_cdc_graycounter0_q_binary = 3'd0;
reg [2:0] main_basesoc_tx_cdc_graycounter0_q_next_binary = 3'd0;
wire main_basesoc_tx_cdc_graycounter1_ce;
reg [2:0] main_basesoc_tx_cdc_graycounter1_q = 3'd0;
wire [2:0] main_basesoc_tx_cdc_graycounter1_q_next;
reg [2:0] main_basesoc_tx_cdc_graycounter1_q_binary = 3'd0;
reg [2:0] main_basesoc_tx_cdc_graycounter1_q_next_binary = 3'd0;
wire [2:0] main_basesoc_tx_cdc_produce_rdomain;
wire [2:0] main_basesoc_tx_cdc_consume_wdomain;
wire [1:0] main_basesoc_tx_cdc_wrport_adr;
wire [9:0] main_basesoc_tx_cdc_wrport_dat_r;
wire main_basesoc_tx_cdc_wrport_we;
wire [9:0] main_basesoc_tx_cdc_wrport_dat_w;
wire [1:0] main_basesoc_tx_cdc_rdport_adr;
wire [9:0] main_basesoc_tx_cdc_rdport_dat_r;
wire [7:0] main_basesoc_tx_cdc_fifo_in_payload_data;
wire main_basesoc_tx_cdc_fifo_in_first;
wire main_basesoc_tx_cdc_fifo_in_last;
wire [7:0] main_basesoc_tx_cdc_fifo_out_payload_data;
wire main_basesoc_tx_cdc_fifo_out_first;
wire main_basesoc_tx_cdc_fifo_out_last;
reg main_basesoc_rx_cdc_sink_valid = 1'd0;
wire main_basesoc_rx_cdc_sink_ready;
reg main_basesoc_rx_cdc_sink_first = 1'd0;
reg main_basesoc_rx_cdc_sink_last = 1'd0;
wire [7:0] main_basesoc_rx_cdc_sink_payload_data;
wire main_basesoc_rx_cdc_source_valid;
wire main_basesoc_rx_cdc_source_ready;
wire main_basesoc_rx_cdc_source_first;
wire main_basesoc_rx_cdc_source_last;
wire [7:0] main_basesoc_rx_cdc_source_payload_data;
wire main_basesoc_rx_cdc_asyncfifo_we;
wire main_basesoc_rx_cdc_asyncfifo_writable;
wire main_basesoc_rx_cdc_asyncfifo_re;
wire main_basesoc_rx_cdc_asyncfifo_readable;
wire [9:0] main_basesoc_rx_cdc_asyncfifo_din;
wire [9:0] main_basesoc_rx_cdc_asyncfifo_dout;
wire main_basesoc_rx_cdc_graycounter0_ce;
reg [2:0] main_basesoc_rx_cdc_graycounter0_q = 3'd0;
wire [2:0] main_basesoc_rx_cdc_graycounter0_q_next;
reg [2:0] main_basesoc_rx_cdc_graycounter0_q_binary = 3'd0;
reg [2:0] main_basesoc_rx_cdc_graycounter0_q_next_binary = 3'd0;
wire main_basesoc_rx_cdc_graycounter1_ce;
reg [2:0] main_basesoc_rx_cdc_graycounter1_q = 3'd0;
wire [2:0] main_basesoc_rx_cdc_graycounter1_q_next;
reg [2:0] main_basesoc_rx_cdc_graycounter1_q_binary = 3'd0;
reg [2:0] main_basesoc_rx_cdc_graycounter1_q_next_binary = 3'd0;
wire [2:0] main_basesoc_rx_cdc_produce_rdomain;
wire [2:0] main_basesoc_rx_cdc_consume_wdomain;
wire [1:0] main_basesoc_rx_cdc_wrport_adr;
wire [9:0] main_basesoc_rx_cdc_wrport_dat_r;
wire main_basesoc_rx_cdc_wrport_we;
wire [9:0] main_basesoc_rx_cdc_wrport_dat_w;
wire [1:0] main_basesoc_rx_cdc_rdport_adr;
wire [9:0] main_basesoc_rx_cdc_rdport_dat_r;
wire [7:0] main_basesoc_rx_cdc_fifo_in_payload_data;
wire main_basesoc_rx_cdc_fifo_in_first;
wire main_basesoc_rx_cdc_fifo_in_last;
wire [7:0] main_basesoc_rx_cdc_fifo_out_payload_data;
wire main_basesoc_rx_cdc_fifo_out_first;
wire main_basesoc_rx_cdc_fifo_out_last;
wire main_basesoc_fsm_reset;
reg main_basesoc_uart_rxtx_re = 1'd0;
wire [7:0] main_basesoc_uart_rxtx_r;
reg main_basesoc_uart_rxtx_we = 1'd0;
wire [7:0] main_basesoc_uart_rxtx_w;
wire main_basesoc_uart_txfull_status;
wire main_basesoc_uart_txfull_we;
reg main_basesoc_uart_txfull_re = 1'd0;
wire main_basesoc_uart_rxempty_status;
wire main_basesoc_uart_rxempty_we;
reg main_basesoc_uart_rxempty_re = 1'd0;
wire main_basesoc_uart_irq;
wire main_basesoc_uart_tx_status;
reg main_basesoc_uart_tx_pending = 1'd0;
wire main_basesoc_uart_tx_trigger;
reg main_basesoc_uart_tx_clear = 1'd0;
reg main_basesoc_uart_tx_trigger_d = 1'd0;
wire main_basesoc_uart_rx_status;
reg main_basesoc_uart_rx_pending = 1'd0;
wire main_basesoc_uart_rx_trigger;
reg main_basesoc_uart_rx_clear = 1'd0;
reg main_basesoc_uart_rx_trigger_d = 1'd0;
wire main_basesoc_uart_tx0;
wire main_basesoc_uart_rx0;
reg [1:0] main_basesoc_uart_status_status = 2'd0;
wire main_basesoc_uart_status_we;
reg main_basesoc_uart_status_re = 1'd0;
wire main_basesoc_uart_tx1;
wire main_basesoc_uart_rx1;
reg [1:0] main_basesoc_uart_pending_status = 2'd0;
wire main_basesoc_uart_pending_we;
reg main_basesoc_uart_pending_re = 1'd0;
reg [1:0] main_basesoc_uart_pending_r = 2'd0;
wire main_basesoc_uart_tx2;
wire main_basesoc_uart_rx2;
reg [1:0] main_basesoc_uart_enable_storage = 2'd0;
reg main_basesoc_uart_enable_re = 1'd0;
wire main_basesoc_uart_txempty_status;
wire main_basesoc_uart_txempty_we;
reg main_basesoc_uart_txempty_re = 1'd0;
wire main_basesoc_uart_rxfull_status;
wire main_basesoc_uart_rxfull_we;
reg main_basesoc_uart_rxfull_re = 1'd0;
wire main_basesoc_uart_uart_sink_valid;
wire main_basesoc_uart_uart_sink_ready;
wire main_basesoc_uart_uart_sink_first;
wire main_basesoc_uart_uart_sink_last;
wire [7:0] main_basesoc_uart_uart_sink_payload_data;
wire main_basesoc_uart_uart_source_valid;
wire main_basesoc_uart_uart_source_ready;
wire main_basesoc_uart_uart_source_first;
wire main_basesoc_uart_uart_source_last;
wire [7:0] main_basesoc_uart_uart_source_payload_data;
wire main_basesoc_uart_tx_fifo_sink_valid;
wire main_basesoc_uart_tx_fifo_sink_ready;
reg main_basesoc_uart_tx_fifo_sink_first = 1'd0;
reg main_basesoc_uart_tx_fifo_sink_last = 1'd0;
wire [7:0] main_basesoc_uart_tx_fifo_sink_payload_data;
wire main_basesoc_uart_tx_fifo_source_valid;
wire main_basesoc_uart_tx_fifo_source_ready;
wire main_basesoc_uart_tx_fifo_source_first;
wire main_basesoc_uart_tx_fifo_source_last;
wire [7:0] main_basesoc_uart_tx_fifo_source_payload_data;
wire main_basesoc_uart_tx_fifo_re;
reg main_basesoc_uart_tx_fifo_readable = 1'd0;
wire main_basesoc_uart_tx_fifo_syncfifo_we;
wire main_basesoc_uart_tx_fifo_syncfifo_writable;
wire main_basesoc_uart_tx_fifo_syncfifo_re;
wire main_basesoc_uart_tx_fifo_syncfifo_readable;
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_din;
wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_dout;
reg [4:0] main_basesoc_uart_tx_fifo_level0 = 5'd0;
reg main_basesoc_uart_tx_fifo_replace = 1'd0;
reg [3:0] main_basesoc_uart_tx_fifo_produce = 4'd0;
reg [3:0] main_basesoc_uart_tx_fifo_consume = 4'd0;
reg [3:0] main_basesoc_uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_r;
wire main_basesoc_uart_tx_fifo_wrport_we;
wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_w;
wire main_basesoc_uart_tx_fifo_do_read;
wire [3:0] main_basesoc_uart_tx_fifo_rdport_adr;
wire [9:0] main_basesoc_uart_tx_fifo_rdport_dat_r;
wire main_basesoc_uart_tx_fifo_rdport_re;
wire [4:0] main_basesoc_uart_tx_fifo_level1;
wire [7:0] main_basesoc_uart_tx_fifo_fifo_in_payload_data;
wire main_basesoc_uart_tx_fifo_fifo_in_first;
wire main_basesoc_uart_tx_fifo_fifo_in_last;
wire [7:0] main_basesoc_uart_tx_fifo_fifo_out_payload_data;
wire main_basesoc_uart_tx_fifo_fifo_out_first;
wire main_basesoc_uart_tx_fifo_fifo_out_last;
wire main_basesoc_uart_rx_fifo_sink_valid;
wire main_basesoc_uart_rx_fifo_sink_ready;
wire main_basesoc_uart_rx_fifo_sink_first;
wire main_basesoc_uart_rx_fifo_sink_last;
wire [7:0] main_basesoc_uart_rx_fifo_sink_payload_data;
wire main_basesoc_uart_rx_fifo_source_valid;
wire main_basesoc_uart_rx_fifo_source_ready;
wire main_basesoc_uart_rx_fifo_source_first;
wire main_basesoc_uart_rx_fifo_source_last;
wire [7:0] main_basesoc_uart_rx_fifo_source_payload_data;
wire main_basesoc_uart_rx_fifo_re;
reg main_basesoc_uart_rx_fifo_readable = 1'd0;
wire main_basesoc_uart_rx_fifo_syncfifo_we;
wire main_basesoc_uart_rx_fifo_syncfifo_writable;
wire main_basesoc_uart_rx_fifo_syncfifo_re;
wire main_basesoc_uart_rx_fifo_syncfifo_readable;
wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_din;
wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_dout;
reg [4:0] main_basesoc_uart_rx_fifo_level0 = 5'd0;
reg main_basesoc_uart_rx_fifo_replace = 1'd0;
reg [3:0] main_basesoc_uart_rx_fifo_produce = 4'd0;
reg [3:0] main_basesoc_uart_rx_fifo_consume = 4'd0;
reg [3:0] main_basesoc_uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_r;
wire main_basesoc_uart_rx_fifo_wrport_we;
wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_w;
wire main_basesoc_uart_rx_fifo_do_read;
wire [3:0] main_basesoc_uart_rx_fifo_rdport_adr;
wire [9:0] main_basesoc_uart_rx_fifo_rdport_dat_r;
wire main_basesoc_uart_rx_fifo_rdport_re;
wire [4:0] main_basesoc_uart_rx_fifo_level1;
wire [7:0] main_basesoc_uart_rx_fifo_fifo_in_payload_data;
wire main_basesoc_uart_rx_fifo_fifo_in_first;
wire main_basesoc_uart_rx_fifo_fifo_in_last;
wire [7:0] main_basesoc_uart_rx_fifo_fifo_out_payload_data;
wire main_basesoc_uart_rx_fifo_fifo_out_first;
wire main_basesoc_uart_rx_fifo_fifo_out_last;
reg [31:0] main_basesoc_timer_load_storage = 32'd0;
reg main_basesoc_timer_load_re = 1'd0;
reg [31:0] main_basesoc_timer_reload_storage = 32'd0;
reg main_basesoc_timer_reload_re = 1'd0;
reg main_basesoc_timer_en_storage = 1'd0;
reg main_basesoc_timer_en_re = 1'd0;
reg main_basesoc_timer_update_value_storage = 1'd0;
reg main_basesoc_timer_update_value_re = 1'd0;
reg [31:0] main_basesoc_timer_value_status = 32'd0;
wire main_basesoc_timer_value_we;
reg main_basesoc_timer_value_re = 1'd0;
wire main_basesoc_timer_irq;
wire main_basesoc_timer_zero_status;
reg main_basesoc_timer_zero_pending = 1'd0;
wire main_basesoc_timer_zero_trigger;
reg main_basesoc_timer_zero_clear = 1'd0;
reg main_basesoc_timer_zero_trigger_d = 1'd0;
wire main_basesoc_timer_zero0;
wire main_basesoc_timer_status_status;
wire main_basesoc_timer_status_we;
reg main_basesoc_timer_status_re = 1'd0;
wire main_basesoc_timer_zero1;
wire main_basesoc_timer_pending_status;
wire main_basesoc_timer_pending_we;
reg main_basesoc_timer_pending_re = 1'd0;
reg main_basesoc_timer_pending_r = 1'd0;
wire main_basesoc_timer_zero2;
reg main_basesoc_timer_enable_storage = 1'd0;
reg main_basesoc_timer_enable_re = 1'd0;
reg [31:0] main_basesoc_timer_value = 32'd0;
wire main_crg_rst;
wire sys_clk;
wire sys_rst;
wire hdmi_clk;
wire hdmi_rst;
wire main_crg_reset;
wire main_crg_locked;
wire main_crg_clkin;
wire main_crg_clkout0;
wire main_crg_clkout1;
reg [3:0] builder_max10jtag_state = 4'd0;
reg [3:0] builder_max10jtag_next_state = 4'd0;
reg [1:0] builder_resetinserter_state = 2'd0;
reg [1:0] builder_resetinserter_next_state = 2'd0;
reg main_basesoc_valid_next_value0 = 1'd0;
reg main_basesoc_valid_next_value_ce0 = 1'd0;
reg [7:0] main_basesoc_data_next_value1 = 8'd0;
reg main_basesoc_data_next_value_ce1 = 1'd0;
reg [2:0] main_basesoc_count_next_value2 = 3'd0;
reg main_basesoc_count_next_value_ce2 = 1'd0;
wire [1:0] builder_clks;
reg [13:0] builder_basesoc_adr = 14'd0;
reg builder_basesoc_we = 1'd0;
reg [31:0] builder_basesoc_dat_w = 32'd0;
wire [31:0] builder_basesoc_dat_r;
reg [29:0] builder_basesoc_wishbone_adr = 30'd0;
reg [31:0] builder_basesoc_wishbone_dat_w = 32'd0;
reg [31:0] builder_basesoc_wishbone_dat_r = 32'd0;
reg [3:0] builder_basesoc_wishbone_sel = 4'd0;
reg builder_basesoc_wishbone_cyc = 1'd0;
reg builder_basesoc_wishbone_stb = 1'd0;
reg builder_basesoc_wishbone_ack = 1'd0;
reg builder_basesoc_wishbone_we = 1'd0;
wire [13:0] builder_csr_bankarray_interface0_bank_bus_adr;
wire builder_csr_bankarray_interface0_bank_bus_we;
wire [31:0] builder_csr_bankarray_interface0_bank_bus_dat_w;
reg [31:0] builder_csr_bankarray_interface0_bank_bus_dat_r = 32'd0;
reg builder_csr_bankarray_csrbank0_reset0_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank0_reset0_r;
reg builder_csr_bankarray_csrbank0_reset0_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank0_reset0_w;
reg builder_csr_bankarray_csrbank0_scratch0_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_scratch0_r;
reg builder_csr_bankarray_csrbank0_scratch0_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_scratch0_w;
reg builder_csr_bankarray_csrbank0_bus_errors_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_r;
reg builder_csr_bankarray_csrbank0_bus_errors_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank0_bus_errors_w;
wire builder_csr_bankarray_csrbank0_sel;
wire [13:0] builder_csr_bankarray_sram_bus_adr;
wire builder_csr_bankarray_sram_bus_we;
wire [31:0] builder_csr_bankarray_sram_bus_dat_w;
reg [31:0] builder_csr_bankarray_sram_bus_dat_r = 32'd0;
wire [5:0] builder_csr_bankarray_adr;
wire [7:0] builder_csr_bankarray_dat_r;
wire builder_csr_bankarray_sel;
reg builder_csr_bankarray_sel_r = 1'd0;
wire [13:0] builder_csr_bankarray_interface1_bank_bus_adr;
wire builder_csr_bankarray_interface1_bank_bus_we;
wire [31:0] builder_csr_bankarray_interface1_bank_bus_dat_w;
reg [31:0] builder_csr_bankarray_interface1_bank_bus_dat_r = 32'd0;
reg builder_csr_bankarray_csrbank1_load0_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_load0_r;
reg builder_csr_bankarray_csrbank1_load0_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_load0_w;
reg builder_csr_bankarray_csrbank1_reload0_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_reload0_r;
reg builder_csr_bankarray_csrbank1_reload0_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_reload0_w;
reg builder_csr_bankarray_csrbank1_en0_re = 1'd0;
wire builder_csr_bankarray_csrbank1_en0_r;
reg builder_csr_bankarray_csrbank1_en0_we = 1'd0;
wire builder_csr_bankarray_csrbank1_en0_w;
reg builder_csr_bankarray_csrbank1_update_value0_re = 1'd0;
wire builder_csr_bankarray_csrbank1_update_value0_r;
reg builder_csr_bankarray_csrbank1_update_value0_we = 1'd0;
wire builder_csr_bankarray_csrbank1_update_value0_w;
reg builder_csr_bankarray_csrbank1_value_re = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_value_r;
reg builder_csr_bankarray_csrbank1_value_we = 1'd0;
wire [31:0] builder_csr_bankarray_csrbank1_value_w;
reg builder_csr_bankarray_csrbank1_ev_status_re = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_status_r;
reg builder_csr_bankarray_csrbank1_ev_status_we = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_status_w;
reg builder_csr_bankarray_csrbank1_ev_pending_re = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_pending_r;
reg builder_csr_bankarray_csrbank1_ev_pending_we = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_pending_w;
reg builder_csr_bankarray_csrbank1_ev_enable0_re = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_enable0_r;
reg builder_csr_bankarray_csrbank1_ev_enable0_we = 1'd0;
wire builder_csr_bankarray_csrbank1_ev_enable0_w;
wire builder_csr_bankarray_csrbank1_sel;
wire [13:0] builder_csr_bankarray_interface2_bank_bus_adr;
wire builder_csr_bankarray_interface2_bank_bus_we;
wire [31:0] builder_csr_bankarray_interface2_bank_bus_dat_w;
reg [31:0] builder_csr_bankarray_interface2_bank_bus_dat_r = 32'd0;
reg builder_csr_bankarray_csrbank2_txfull_re = 1'd0;
wire builder_csr_bankarray_csrbank2_txfull_r;
reg builder_csr_bankarray_csrbank2_txfull_we = 1'd0;
wire builder_csr_bankarray_csrbank2_txfull_w;
reg builder_csr_bankarray_csrbank2_rxempty_re = 1'd0;
wire builder_csr_bankarray_csrbank2_rxempty_r;
reg builder_csr_bankarray_csrbank2_rxempty_we = 1'd0;
wire builder_csr_bankarray_csrbank2_rxempty_w;
reg builder_csr_bankarray_csrbank2_ev_status_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_r;
reg builder_csr_bankarray_csrbank2_ev_status_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_status_w;
reg builder_csr_bankarray_csrbank2_ev_pending_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_pending_r;
reg builder_csr_bankarray_csrbank2_ev_pending_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_pending_w;
reg builder_csr_bankarray_csrbank2_ev_enable0_re = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_enable0_r;
reg builder_csr_bankarray_csrbank2_ev_enable0_we = 1'd0;
wire [1:0] builder_csr_bankarray_csrbank2_ev_enable0_w;
reg builder_csr_bankarray_csrbank2_txempty_re = 1'd0;
wire builder_csr_bankarray_csrbank2_txempty_r;
reg builder_csr_bankarray_csrbank2_txempty_we = 1'd0;
wire builder_csr_bankarray_csrbank2_txempty_w;
reg builder_csr_bankarray_csrbank2_rxfull_re = 1'd0;
wire builder_csr_bankarray_csrbank2_rxfull_r;
reg builder_csr_bankarray_csrbank2_rxfull_we = 1'd0;
wire builder_csr_bankarray_csrbank2_rxfull_w;
wire builder_csr_bankarray_csrbank2_sel;
wire [13:0] builder_csr_interconnect_adr;
wire builder_csr_interconnect_we;
wire [31:0] builder_csr_interconnect_dat_w;
wire [31:0] builder_csr_interconnect_dat_r;
reg builder_state = 1'd0;
reg builder_next_state = 1'd0;
wire builder_rst_meta0;
reg [2:0] builder_multiregimpl0_regs0 = 3'd0;
reg [2:0] builder_multiregimpl0_regs1 = 3'd0;
reg [2:0] builder_multiregimpl1_regs0 = 3'd0;
reg [2:0] builder_multiregimpl1_regs1 = 3'd0;
reg [2:0] builder_multiregimpl2_regs0 = 3'd0;
reg [2:0] builder_multiregimpl2_regs1 = 3'd0;
reg [2:0] builder_multiregimpl3_regs0 = 3'd0;
reg [2:0] builder_multiregimpl3_regs1 = 3'd0;
wire builder_rst_meta1;
wire builder_rst_meta2;
//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------
assign sys_jtag_clk = sys_clk;
assign user_led = gpio[0];
assign user_led_1 = gpio[1];
assign user_led_2 = gpio[2];
assign user_led_3 = gpio[3];
assign user_led_4 = gpio[4];
assign user_led_5 = gpio[5];
assign user_led_6 = gpio[6];
assign user_led_7 = gpio[7];
assign main_crg_rst = main_basesoc_soc_rst;
assign main_basesoc_bus_errors_status = main_basesoc_bus_errors;
always @(*) begin
main_basesoc_we <= 4'd0;
main_basesoc_we[0] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[0]);
main_basesoc_we[1] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[1]);
main_basesoc_we[2] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[2]);
main_basesoc_we[3] <= (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & main_basesoc_ram_bus_we) & main_basesoc_ram_bus_sel[3]);
end
assign main_basesoc_adr = main_basesoc_ram_bus_adr[10:0];
assign main_basesoc_ram_bus_dat_r = main_basesoc_dat_r;
assign main_basesoc_dat_w = main_basesoc_ram_bus_dat_w;
assign jtag_clk = main_basesoc_jtag_tck;
assign main_basesoc_tx_cdc_sink_valid = main_basesoc_sink_sink_valid;
assign main_basesoc_sink_sink_ready = main_basesoc_tx_cdc_sink_ready;
assign main_basesoc_tx_cdc_sink_first = main_basesoc_sink_sink_first;
assign main_basesoc_tx_cdc_sink_last = main_basesoc_sink_sink_last;
assign main_basesoc_tx_cdc_sink_payload_data = main_basesoc_sink_sink_payload_data;
assign main_basesoc_source_source_valid = main_basesoc_rx_cdc_source_valid;
assign main_basesoc_rx_cdc_source_ready = main_basesoc_source_source_ready;
assign main_basesoc_source_source_first = main_basesoc_rx_cdc_source_first;
assign main_basesoc_source_source_last = main_basesoc_rx_cdc_source_last;
assign main_basesoc_source_source_payload_data = main_basesoc_rx_cdc_source_payload_data;
assign main_basesoc_fsm_reset = (main_basesoc_jtag_reset | main_basesoc_jtag_capture);
assign main_basesoc_rx_cdc_sink_payload_data = main_basesoc_data;
assign jtag_inv_clk = (~jtag_clk);
assign jtag_inv_rst = jtag_rst;
assign main_basesoc_jtag_altera_reserved_tms = altera_reserved_tms;
assign main_basesoc_jtag_altera_reserved_tck = altera_reserved_tck;
assign main_basesoc_jtag_altera_reserved_tdi = altera_reserved_tdi;
assign altera_reserved_tdo = main_basesoc_jtag_altera_reserved_tdo;
assign main_basesoc_jtag_tck = main_basesoc_jtag_tckutap;
assign main_basesoc_jtag_tms = main_basesoc_jtag_tmsutap;
assign main_basesoc_jtag_tdi = main_basesoc_jtag_tdiutap;
assign main_basesoc_jtag_TEST_LOGIC_RESET = main_basesoc_jtag_is_ongoing0;
assign main_basesoc_jtag_RUN_TEST_IDLE = main_basesoc_jtag_is_ongoing1;
assign main_basesoc_jtag_SELECT_DR_SCAN = main_basesoc_jtag_is_ongoing2;
assign main_basesoc_jtag_CAPTURE_DR = main_basesoc_jtag_is_ongoing3;
assign main_basesoc_jtag_SHIFT_DR = main_basesoc_jtag_is_ongoing4;
assign main_basesoc_jtag_EXIT1_DR = main_basesoc_jtag_is_ongoing5;
assign main_basesoc_jtag_PAUSE_DR = main_basesoc_jtag_is_ongoing6;
assign main_basesoc_jtag_EXIT2_DR = main_basesoc_jtag_is_ongoing7;
assign main_basesoc_jtag_UPDATE_DR = main_basesoc_jtag_is_ongoing8;
assign main_basesoc_jtag_SELECT_IR_SCAN = main_basesoc_jtag_is_ongoing9;
assign main_basesoc_jtag_CAPTURE_IR = main_basesoc_jtag_is_ongoing10;
assign main_basesoc_jtag_SHIFT_IR = main_basesoc_jtag_is_ongoing11;
assign main_basesoc_jtag_EXIT1_IR = main_basesoc_jtag_is_ongoing12;
assign main_basesoc_jtag_PAUSE_IR = main_basesoc_jtag_is_ongoing13;
assign main_basesoc_jtag_EXIT2_IR = main_basesoc_jtag_is_ongoing14;
assign main_basesoc_jtag_UPDATE_IR = main_basesoc_jtag_is_ongoing15;
always @(*) begin
main_basesoc_jtag_is_ongoing12 <= 1'd0;
builder_max10jtag_next_state <= 4'd0;
main_basesoc_jtag_is_ongoing0 <= 1'd1;
main_basesoc_jtag_is_ongoing13 <= 1'd0;
main_basesoc_jtag_is_ongoing1 <= 1'd0;
main_basesoc_jtag_is_ongoing14 <= 1'd0;
main_basesoc_jtag_is_ongoing2 <= 1'd0;
main_basesoc_jtag_is_ongoing15 <= 1'd0;
main_basesoc_jtag_is_ongoing3 <= 1'd0;
main_basesoc_jtag_is_ongoing4 <= 1'd0;
main_basesoc_jtag_is_ongoing5 <= 1'd0;
main_basesoc_jtag_is_ongoing6 <= 1'd0;
main_basesoc_jtag_is_ongoing7 <= 1'd0;
main_basesoc_jtag_is_ongoing8 <= 1'd0;
main_basesoc_jtag_is_ongoing9 <= 1'd0;
main_basesoc_jtag_is_ongoing10 <= 1'd0;
main_basesoc_jtag_is_ongoing11 <= 1'd0;
builder_max10jtag_next_state <= builder_max10jtag_state;
case (builder_max10jtag_state)
1'd1: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 2'd2;
end
main_basesoc_jtag_is_ongoing1 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
2'd2: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 2'd3;
end else begin
builder_max10jtag_next_state <= 4'd9;
end
main_basesoc_jtag_is_ongoing2 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
2'd3: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 3'd4;
end else begin
builder_max10jtag_next_state <= 3'd5;
end
main_basesoc_jtag_is_ongoing3 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd4: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 3'd5;
end
main_basesoc_jtag_is_ongoing4 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd5: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 3'd6;
end else begin
builder_max10jtag_next_state <= 4'd8;
end
main_basesoc_jtag_is_ongoing5 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd6: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 3'd7;
end
main_basesoc_jtag_is_ongoing6 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
3'd7: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd8;
end else begin
builder_max10jtag_next_state <= 3'd4;
end
main_basesoc_jtag_is_ongoing7 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd8: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 2'd2;
end else begin
builder_max10jtag_next_state <= 1'd1;
end
main_basesoc_jtag_is_ongoing8 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd9: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 4'd10;
end else begin
builder_max10jtag_next_state <= 1'd0;
end
main_basesoc_jtag_is_ongoing9 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd10: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 4'd11;
end else begin
builder_max10jtag_next_state <= 4'd12;
end
main_basesoc_jtag_is_ongoing10 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd11: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd12;
end
main_basesoc_jtag_is_ongoing11 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd12: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 4'd13;
end else begin
builder_max10jtag_next_state <= 4'd15;
end
main_basesoc_jtag_is_ongoing12 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd13: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd14;
end
main_basesoc_jtag_is_ongoing13 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd14: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 4'd15;
end else begin
builder_max10jtag_next_state <= 4'd11;
end
main_basesoc_jtag_is_ongoing14 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
4'd15: begin
if (main_basesoc_jtag_tms) begin
builder_max10jtag_next_state <= 2'd2;
end else begin
builder_max10jtag_next_state <= 1'd1;
end
main_basesoc_jtag_is_ongoing15 <= 1'd1;
main_basesoc_jtag_is_ongoing0 <= 1'd0;
end
default: begin
if ((~main_basesoc_jtag_tms)) begin
builder_max10jtag_next_state <= 1'd1;
end
main_basesoc_jtag_is_ongoing0 <= 1'd1;
end
endcase
end
assign main_basesoc_tx_cdc_asyncfifo_din = {main_basesoc_tx_cdc_fifo_in_last, main_basesoc_tx_cdc_fifo_in_first, main_basesoc_tx_cdc_fifo_in_payload_data};
assign {main_basesoc_tx_cdc_fifo_out_last, main_basesoc_tx_cdc_fifo_out_first, main_basesoc_tx_cdc_fifo_out_payload_data} = main_basesoc_tx_cdc_asyncfifo_dout;
assign main_basesoc_tx_cdc_sink_ready = main_basesoc_tx_cdc_asyncfifo_writable;
assign main_basesoc_tx_cdc_asyncfifo_we = main_basesoc_tx_cdc_sink_valid;
assign main_basesoc_tx_cdc_fifo_in_first = main_basesoc_tx_cdc_sink_first;
assign main_basesoc_tx_cdc_fifo_in_last = main_basesoc_tx_cdc_sink_last;
assign main_basesoc_tx_cdc_fifo_in_payload_data = main_basesoc_tx_cdc_sink_payload_data;
assign main_basesoc_tx_cdc_source_valid = main_basesoc_tx_cdc_asyncfifo_readable;
assign main_basesoc_tx_cdc_source_first = main_basesoc_tx_cdc_fifo_out_first;
assign main_basesoc_tx_cdc_source_last = main_basesoc_tx_cdc_fifo_out_last;
assign main_basesoc_tx_cdc_source_payload_data = main_basesoc_tx_cdc_fifo_out_payload_data;
assign main_basesoc_tx_cdc_asyncfifo_re = main_basesoc_tx_cdc_source_ready;
assign main_basesoc_tx_cdc_graycounter0_ce = (main_basesoc_tx_cdc_asyncfifo_writable & main_basesoc_tx_cdc_asyncfifo_we);
assign main_basesoc_tx_cdc_graycounter1_ce = (main_basesoc_tx_cdc_asyncfifo_readable & main_basesoc_tx_cdc_asyncfifo_re);
assign main_basesoc_tx_cdc_asyncfifo_writable = (((main_basesoc_tx_cdc_graycounter0_q[2] == main_basesoc_tx_cdc_consume_wdomain[2]) | (main_basesoc_tx_cdc_graycounter0_q[1] == main_basesoc_tx_cdc_consume_wdomain[1])) | (main_basesoc_tx_cdc_graycounter0_q[0] != main_basesoc_tx_cdc_consume_wdomain[0]));
assign main_basesoc_tx_cdc_asyncfifo_readable = (main_basesoc_tx_cdc_graycounter1_q != main_basesoc_tx_cdc_produce_rdomain);
assign main_basesoc_tx_cdc_wrport_adr = main_basesoc_tx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_tx_cdc_wrport_dat_w = main_basesoc_tx_cdc_asyncfifo_din;
assign main_basesoc_tx_cdc_wrport_we = main_basesoc_tx_cdc_graycounter0_ce;
assign main_basesoc_tx_cdc_rdport_adr = main_basesoc_tx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_tx_cdc_asyncfifo_dout = main_basesoc_tx_cdc_rdport_dat_r;
always @(*) begin
main_basesoc_tx_cdc_graycounter0_q_next_binary <= 3'd0;
if (main_basesoc_tx_cdc_graycounter0_ce) begin
main_basesoc_tx_cdc_graycounter0_q_next_binary <= (main_basesoc_tx_cdc_graycounter0_q_binary + 1'd1);
end else begin
main_basesoc_tx_cdc_graycounter0_q_next_binary <= main_basesoc_tx_cdc_graycounter0_q_binary;
end
end
assign main_basesoc_tx_cdc_graycounter0_q_next = (main_basesoc_tx_cdc_graycounter0_q_next_binary ^ main_basesoc_tx_cdc_graycounter0_q_next_binary[2:1]);
always @(*) begin
main_basesoc_tx_cdc_graycounter1_q_next_binary <= 3'd0;
if (main_basesoc_tx_cdc_graycounter1_ce) begin
main_basesoc_tx_cdc_graycounter1_q_next_binary <= (main_basesoc_tx_cdc_graycounter1_q_binary + 1'd1);
end else begin
main_basesoc_tx_cdc_graycounter1_q_next_binary <= main_basesoc_tx_cdc_graycounter1_q_binary;
end
end
assign main_basesoc_tx_cdc_graycounter1_q_next = (main_basesoc_tx_cdc_graycounter1_q_next_binary ^ main_basesoc_tx_cdc_graycounter1_q_next_binary[2:1]);
assign main_basesoc_rx_cdc_asyncfifo_din = {main_basesoc_rx_cdc_fifo_in_last, main_basesoc_rx_cdc_fifo_in_first, main_basesoc_rx_cdc_fifo_in_payload_data};
assign {main_basesoc_rx_cdc_fifo_out_last, main_basesoc_rx_cdc_fifo_out_first, main_basesoc_rx_cdc_fifo_out_payload_data} = main_basesoc_rx_cdc_asyncfifo_dout;
assign main_basesoc_rx_cdc_sink_ready = main_basesoc_rx_cdc_asyncfifo_writable;
assign main_basesoc_rx_cdc_asyncfifo_we = main_basesoc_rx_cdc_sink_valid;
assign main_basesoc_rx_cdc_fifo_in_first = main_basesoc_rx_cdc_sink_first;
assign main_basesoc_rx_cdc_fifo_in_last = main_basesoc_rx_cdc_sink_last;
assign main_basesoc_rx_cdc_fifo_in_payload_data = main_basesoc_rx_cdc_sink_payload_data;
assign main_basesoc_rx_cdc_source_valid = main_basesoc_rx_cdc_asyncfifo_readable;
assign main_basesoc_rx_cdc_source_first = main_basesoc_rx_cdc_fifo_out_first;
assign main_basesoc_rx_cdc_source_last = main_basesoc_rx_cdc_fifo_out_last;
assign main_basesoc_rx_cdc_source_payload_data = main_basesoc_rx_cdc_fifo_out_payload_data;
assign main_basesoc_rx_cdc_asyncfifo_re = main_basesoc_rx_cdc_source_ready;
assign main_basesoc_rx_cdc_graycounter0_ce = (main_basesoc_rx_cdc_asyncfifo_writable & main_basesoc_rx_cdc_asyncfifo_we);
assign main_basesoc_rx_cdc_graycounter1_ce = (main_basesoc_rx_cdc_asyncfifo_readable & main_basesoc_rx_cdc_asyncfifo_re);
assign main_basesoc_rx_cdc_asyncfifo_writable = (((main_basesoc_rx_cdc_graycounter0_q[2] == main_basesoc_rx_cdc_consume_wdomain[2]) | (main_basesoc_rx_cdc_graycounter0_q[1] == main_basesoc_rx_cdc_consume_wdomain[1])) | (main_basesoc_rx_cdc_graycounter0_q[0] != main_basesoc_rx_cdc_consume_wdomain[0]));
assign main_basesoc_rx_cdc_asyncfifo_readable = (main_basesoc_rx_cdc_graycounter1_q != main_basesoc_rx_cdc_produce_rdomain);
assign main_basesoc_rx_cdc_wrport_adr = main_basesoc_rx_cdc_graycounter0_q_binary[1:0];
assign main_basesoc_rx_cdc_wrport_dat_w = main_basesoc_rx_cdc_asyncfifo_din;
assign main_basesoc_rx_cdc_wrport_we = main_basesoc_rx_cdc_graycounter0_ce;
assign main_basesoc_rx_cdc_rdport_adr = main_basesoc_rx_cdc_graycounter1_q_next_binary[1:0];
assign main_basesoc_rx_cdc_asyncfifo_dout = main_basesoc_rx_cdc_rdport_dat_r;
always @(*) begin
main_basesoc_rx_cdc_graycounter0_q_next_binary <= 3'd0;
if (main_basesoc_rx_cdc_graycounter0_ce) begin
main_basesoc_rx_cdc_graycounter0_q_next_binary <= (main_basesoc_rx_cdc_graycounter0_q_binary + 1'd1);
end else begin
main_basesoc_rx_cdc_graycounter0_q_next_binary <= main_basesoc_rx_cdc_graycounter0_q_binary;
end
end
assign main_basesoc_rx_cdc_graycounter0_q_next = (main_basesoc_rx_cdc_graycounter0_q_next_binary ^ main_basesoc_rx_cdc_graycounter0_q_next_binary[2:1]);
always @(*) begin
main_basesoc_rx_cdc_graycounter1_q_next_binary <= 3'd0;
if (main_basesoc_rx_cdc_graycounter1_ce) begin
main_basesoc_rx_cdc_graycounter1_q_next_binary <= (main_basesoc_rx_cdc_graycounter1_q_binary + 1'd1);
end else begin
main_basesoc_rx_cdc_graycounter1_q_next_binary <= main_basesoc_rx_cdc_graycounter1_q_binary;
end
end
assign main_basesoc_rx_cdc_graycounter1_q_next = (main_basesoc_rx_cdc_graycounter1_q_next_binary ^ main_basesoc_rx_cdc_graycounter1_q_next_binary[2:1]);
always @(*) begin
main_basesoc_data_next_value1 <= 8'd0;
main_basesoc_jtag_tdo <= 1'd0;
main_basesoc_data_next_value_ce1 <= 1'd0;
main_basesoc_count_next_value2 <= 3'd0;
main_basesoc_tx_cdc_source_ready <= 1'd0;
main_basesoc_count_next_value_ce2 <= 1'd0;
main_basesoc_rx_cdc_sink_valid <= 1'd0;
builder_resetinserter_next_state <= 2'd0;
main_basesoc_valid_next_value0 <= 1'd0;
main_basesoc_valid_next_value_ce0 <= 1'd0;
builder_resetinserter_next_state <= builder_resetinserter_state;
case (builder_resetinserter_state)
1'd1: begin
main_basesoc_jtag_tdo <= main_basesoc_data;
if (main_basesoc_jtag_shift) begin
main_basesoc_count_next_value2 <= (main_basesoc_count + 1'd1);
main_basesoc_count_next_value_ce2 <= 1'd1;
main_basesoc_data_next_value1 <= {main_basesoc_jtag_tdi, main_basesoc_data[7:1]};
main_basesoc_data_next_value_ce1 <= 1'd1;
if ((main_basesoc_count == 3'd7)) begin
builder_resetinserter_next_state <= 2'd2;
end
end
end
2'd2: begin
main_basesoc_jtag_tdo <= main_basesoc_valid;
if (main_basesoc_jtag_shift) begin
main_basesoc_rx_cdc_sink_valid <= main_basesoc_jtag_tdi;
builder_resetinserter_next_state <= 1'd0;
end
end
default: begin
main_basesoc_jtag_tdo <= main_basesoc_rx_cdc_sink_ready;
if (main_basesoc_jtag_shift) begin
main_basesoc_tx_cdc_source_ready <= main_basesoc_jtag_tdi;
main_basesoc_valid_next_value0 <= main_basesoc_tx_cdc_source_valid;
main_basesoc_valid_next_value_ce0 <= 1'd1;
main_basesoc_data_next_value1 <= main_basesoc_tx_cdc_source_payload_data;
main_basesoc_data_next_value_ce1 <= 1'd1;
main_basesoc_count_next_value2 <= 1'd0;
main_basesoc_count_next_value_ce2 <= 1'd1;
builder_resetinserter_next_state <= 1'd1;
end
end
endcase
end
assign main_basesoc_uart_uart_sink_valid = main_basesoc_source_source_valid;
assign main_basesoc_source_source_ready = main_basesoc_uart_uart_sink_ready;
assign main_basesoc_uart_uart_sink_first = main_basesoc_source_source_first;
assign main_basesoc_uart_uart_sink_last = main_basesoc_source_source_last;
assign main_basesoc_uart_uart_sink_payload_data = main_basesoc_source_source_payload_data;
assign main_basesoc_sink_sink_valid = main_basesoc_uart_uart_source_valid;
assign main_basesoc_uart_uart_source_ready = main_basesoc_sink_sink_ready;
assign main_basesoc_sink_sink_first = main_basesoc_uart_uart_source_first;
assign main_basesoc_sink_sink_last = main_basesoc_uart_uart_source_last;
assign main_basesoc_sink_sink_payload_data = main_basesoc_uart_uart_source_payload_data;
assign main_basesoc_uart_tx_fifo_sink_valid = main_basesoc_uart_rxtx_re;
assign main_basesoc_uart_tx_fifo_sink_payload_data = main_basesoc_uart_rxtx_r;
assign main_basesoc_uart_uart_source_valid = main_basesoc_uart_tx_fifo_source_valid;
assign main_basesoc_uart_tx_fifo_source_ready = main_basesoc_uart_uart_source_ready;
assign main_basesoc_uart_uart_source_first = main_basesoc_uart_tx_fifo_source_first;
assign main_basesoc_uart_uart_source_last = main_basesoc_uart_tx_fifo_source_last;
assign main_basesoc_uart_uart_source_payload_data = main_basesoc_uart_tx_fifo_source_payload_data;
assign main_basesoc_uart_txfull_status = (~main_basesoc_uart_tx_fifo_sink_ready);
assign main_basesoc_uart_txempty_status = (~main_basesoc_uart_tx_fifo_source_valid);
assign main_basesoc_uart_tx_trigger = main_basesoc_uart_tx_fifo_sink_ready;
assign main_basesoc_uart_rx_fifo_sink_valid = main_basesoc_uart_uart_sink_valid;
assign main_basesoc_uart_uart_sink_ready = main_basesoc_uart_rx_fifo_sink_ready;
assign main_basesoc_uart_rx_fifo_sink_first = main_basesoc_uart_uart_sink_first;
assign main_basesoc_uart_rx_fifo_sink_last = main_basesoc_uart_uart_sink_last;
assign main_basesoc_uart_rx_fifo_sink_payload_data = main_basesoc_uart_uart_sink_payload_data;
assign main_basesoc_uart_rxtx_w = main_basesoc_uart_rx_fifo_source_payload_data;
assign main_basesoc_uart_rx_fifo_source_ready = (main_basesoc_uart_rx_clear | (1'd0 & main_basesoc_uart_rxtx_we));
assign main_basesoc_uart_rxempty_status = (~main_basesoc_uart_rx_fifo_source_valid);
assign main_basesoc_uart_rxfull_status = (~main_basesoc_uart_rx_fifo_sink_ready);
assign main_basesoc_uart_rx_trigger = main_basesoc_uart_rx_fifo_source_valid;
assign main_basesoc_uart_tx0 = main_basesoc_uart_tx_status;
assign main_basesoc_uart_tx1 = main_basesoc_uart_tx_pending;
always @(*) begin
main_basesoc_uart_tx_clear <= 1'd0;
if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[0])) begin
main_basesoc_uart_tx_clear <= 1'd1;
end
end
assign main_basesoc_uart_rx0 = main_basesoc_uart_rx_status;
assign main_basesoc_uart_rx1 = main_basesoc_uart_rx_pending;
always @(*) begin
main_basesoc_uart_rx_clear <= 1'd0;
if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[1])) begin
main_basesoc_uart_rx_clear <= 1'd1;
end
end
assign main_basesoc_uart_irq = ((main_basesoc_uart_pending_status[0] & main_basesoc_uart_enable_storage[0]) | (main_basesoc_uart_pending_status[1] & main_basesoc_uart_enable_storage[1]));
assign main_basesoc_uart_tx_status = main_basesoc_uart_tx_trigger;
assign main_basesoc_uart_rx_status = main_basesoc_uart_rx_trigger;
assign main_basesoc_uart_tx_fifo_syncfifo_din = {main_basesoc_uart_tx_fifo_fifo_in_last, main_basesoc_uart_tx_fifo_fifo_in_first, main_basesoc_uart_tx_fifo_fifo_in_payload_data};
assign {main_basesoc_uart_tx_fifo_fifo_out_last, main_basesoc_uart_tx_fifo_fifo_out_first, main_basesoc_uart_tx_fifo_fifo_out_payload_data} = main_basesoc_uart_tx_fifo_syncfifo_dout;
assign main_basesoc_uart_tx_fifo_sink_ready = main_basesoc_uart_tx_fifo_syncfifo_writable;
assign main_basesoc_uart_tx_fifo_syncfifo_we = main_basesoc_uart_tx_fifo_sink_valid;
assign main_basesoc_uart_tx_fifo_fifo_in_first = main_basesoc_uart_tx_fifo_sink_first;
assign main_basesoc_uart_tx_fifo_fifo_in_last = main_basesoc_uart_tx_fifo_sink_last;
assign main_basesoc_uart_tx_fifo_fifo_in_payload_data = main_basesoc_uart_tx_fifo_sink_payload_data;
assign main_basesoc_uart_tx_fifo_source_valid = main_basesoc_uart_tx_fifo_readable;
assign main_basesoc_uart_tx_fifo_source_first = main_basesoc_uart_tx_fifo_fifo_out_first;
assign main_basesoc_uart_tx_fifo_source_last = main_basesoc_uart_tx_fifo_fifo_out_last;
assign main_basesoc_uart_tx_fifo_source_payload_data = main_basesoc_uart_tx_fifo_fifo_out_payload_data;
assign main_basesoc_uart_tx_fifo_re = main_basesoc_uart_tx_fifo_source_ready;
assign main_basesoc_uart_tx_fifo_syncfifo_re = (main_basesoc_uart_tx_fifo_syncfifo_readable & ((~main_basesoc_uart_tx_fifo_readable) | main_basesoc_uart_tx_fifo_re));
assign main_basesoc_uart_tx_fifo_level1 = (main_basesoc_uart_tx_fifo_level0 + main_basesoc_uart_tx_fifo_readable);
always @(*) begin
main_basesoc_uart_tx_fifo_wrport_adr <= 4'd0;
if (main_basesoc_uart_tx_fifo_replace) begin
main_basesoc_uart_tx_fifo_wrport_adr <= (main_basesoc_uart_tx_fifo_produce - 1'd1);
end else begin
main_basesoc_uart_tx_fifo_wrport_adr <= main_basesoc_uart_tx_fifo_produce;
end
end
assign main_basesoc_uart_tx_fifo_wrport_dat_w = main_basesoc_uart_tx_fifo_syncfifo_din;
assign main_basesoc_uart_tx_fifo_wrport_we = (main_basesoc_uart_tx_fifo_syncfifo_we & (main_basesoc_uart_tx_fifo_syncfifo_writable | main_basesoc_uart_tx_fifo_replace));
assign main_basesoc_uart_tx_fifo_do_read = (main_basesoc_uart_tx_fifo_syncfifo_readable & main_basesoc_uart_tx_fifo_syncfifo_re);
assign main_basesoc_uart_tx_fifo_rdport_adr = main_basesoc_uart_tx_fifo_consume;
assign main_basesoc_uart_tx_fifo_syncfifo_dout = main_basesoc_uart_tx_fifo_rdport_dat_r;
assign main_basesoc_uart_tx_fifo_rdport_re = main_basesoc_uart_tx_fifo_do_read;
assign main_basesoc_uart_tx_fifo_syncfifo_writable = (main_basesoc_uart_tx_fifo_level0 != 5'h10);
assign main_basesoc_uart_tx_fifo_syncfifo_readable = (main_basesoc_uart_tx_fifo_level0 != 1'd0);
assign main_basesoc_uart_rx_fifo_syncfifo_din = {main_basesoc_uart_rx_fifo_fifo_in_last, main_basesoc_uart_rx_fifo_fifo_in_first, main_basesoc_uart_rx_fifo_fifo_in_payload_data};
assign {main_basesoc_uart_rx_fifo_fifo_out_last, main_basesoc_uart_rx_fifo_fifo_out_first, main_basesoc_uart_rx_fifo_fifo_out_payload_data} = main_basesoc_uart_rx_fifo_syncfifo_dout;
assign main_basesoc_uart_rx_fifo_sink_ready = main_basesoc_uart_rx_fifo_syncfifo_writable;
assign main_basesoc_uart_rx_fifo_syncfifo_we = main_basesoc_uart_rx_fifo_sink_valid;
assign main_basesoc_uart_rx_fifo_fifo_in_first = main_basesoc_uart_rx_fifo_sink_first;
assign main_basesoc_uart_rx_fifo_fifo_in_last = main_basesoc_uart_rx_fifo_sink_last;
assign main_basesoc_uart_rx_fifo_fifo_in_payload_data = main_basesoc_uart_rx_fifo_sink_payload_data;
assign main_basesoc_uart_rx_fifo_source_valid = main_basesoc_uart_rx_fifo_readable;
assign main_basesoc_uart_rx_fifo_source_first = main_basesoc_uart_rx_fifo_fifo_out_first;
assign main_basesoc_uart_rx_fifo_source_last = main_basesoc_uart_rx_fifo_fifo_out_last;
assign main_basesoc_uart_rx_fifo_source_payload_data = main_basesoc_uart_rx_fifo_fifo_out_payload_data;
assign main_basesoc_uart_rx_fifo_re = main_basesoc_uart_rx_fifo_source_ready;
assign main_basesoc_uart_rx_fifo_syncfifo_re = (main_basesoc_uart_rx_fifo_syncfifo_readable & ((~main_basesoc_uart_rx_fifo_readable) | main_basesoc_uart_rx_fifo_re));
assign main_basesoc_uart_rx_fifo_level1 = (main_basesoc_uart_rx_fifo_level0 + main_basesoc_uart_rx_fifo_readable);
always @(*) begin
main_basesoc_uart_rx_fifo_wrport_adr <= 4'd0;
if (main_basesoc_uart_rx_fifo_replace) begin
main_basesoc_uart_rx_fifo_wrport_adr <= (main_basesoc_uart_rx_fifo_produce - 1'd1);
end else begin
main_basesoc_uart_rx_fifo_wrport_adr <= main_basesoc_uart_rx_fifo_produce;
end
end
assign main_basesoc_uart_rx_fifo_wrport_dat_w = main_basesoc_uart_rx_fifo_syncfifo_din;
assign main_basesoc_uart_rx_fifo_wrport_we = (main_basesoc_uart_rx_fifo_syncfifo_we & (main_basesoc_uart_rx_fifo_syncfifo_writable | main_basesoc_uart_rx_fifo_replace));
assign main_basesoc_uart_rx_fifo_do_read = (main_basesoc_uart_rx_fifo_syncfifo_readable & main_basesoc_uart_rx_fifo_syncfifo_re);
assign main_basesoc_uart_rx_fifo_rdport_adr = main_basesoc_uart_rx_fifo_consume;
assign main_basesoc_uart_rx_fifo_syncfifo_dout = main_basesoc_uart_rx_fifo_rdport_dat_r;
assign main_basesoc_uart_rx_fifo_rdport_re = main_basesoc_uart_rx_fifo_do_read;
assign main_basesoc_uart_rx_fifo_syncfifo_writable = (main_basesoc_uart_rx_fifo_level0 != 5'h10);
assign main_basesoc_uart_rx_fifo_syncfifo_readable = (main_basesoc_uart_rx_fifo_level0 != 1'd0);
assign main_basesoc_timer_zero_trigger = (main_basesoc_timer_value == 1'd0);
assign main_basesoc_timer_zero0 = main_basesoc_timer_zero_status;
assign main_basesoc_timer_zero1 = main_basesoc_timer_zero_pending;
always @(*) begin
main_basesoc_timer_zero_clear <= 1'd0;
if ((main_basesoc_timer_pending_re & main_basesoc_timer_pending_r)) begin
main_basesoc_timer_zero_clear <= 1'd1;
end
end
assign main_basesoc_timer_irq = (main_basesoc_timer_pending_status & main_basesoc_timer_enable_storage);
assign main_basesoc_timer_zero_status = main_basesoc_timer_zero_trigger;
assign main_crg_reset = main_crg_rst;
assign main_crg_clkin = clk50;
assign sys_clk = main_crg_clkout0;
assign hdmi_clk = main_crg_clkout1;
assign main_crg_clkout0 = builder_clks[0];
assign main_crg_clkout1 = builder_clks[1];
always @(*) begin
builder_basesoc_wishbone_ack <= 1'd0;
builder_basesoc_dat_w <= 32'd0;
builder_next_state <= 1'd0;
builder_basesoc_wishbone_dat_r <= 32'd0;
builder_basesoc_adr <= 14'd0;
builder_basesoc_we <= 1'd0;
builder_next_state <= builder_state;
case (builder_state)
1'd1: begin
builder_basesoc_wishbone_ack <= 1'd1;
builder_basesoc_wishbone_dat_r <= builder_basesoc_dat_r;
builder_next_state <= 1'd0;
end
default: begin
builder_basesoc_dat_w <= builder_basesoc_wishbone_dat_w;
if ((builder_basesoc_wishbone_cyc & builder_basesoc_wishbone_stb)) begin
builder_basesoc_adr <= builder_basesoc_wishbone_adr;
builder_basesoc_we <= (builder_basesoc_wishbone_we & (builder_basesoc_wishbone_sel != 1'd0));
builder_next_state <= 1'd1;
end
end
endcase
end
assign builder_csr_bankarray_csrbank0_sel = (builder_csr_bankarray_interface0_bank_bus_adr[13:9] == 1'd0);
assign builder_csr_bankarray_csrbank0_reset0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank0_reset0_re <= 1'd0;
builder_csr_bankarray_csrbank0_reset0_we <= 1'd0;
if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin
builder_csr_bankarray_csrbank0_reset0_re <= builder_csr_bankarray_interface0_bank_bus_we;
builder_csr_bankarray_csrbank0_reset0_we <= (~builder_csr_bankarray_interface0_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank0_scratch0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank0_scratch0_we <= 1'd0;
builder_csr_bankarray_csrbank0_scratch0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd1))) begin
builder_csr_bankarray_csrbank0_scratch0_re <= builder_csr_bankarray_interface0_bank_bus_we;
builder_csr_bankarray_csrbank0_scratch0_we <= (~builder_csr_bankarray_interface0_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank0_bus_errors_r = builder_csr_bankarray_interface0_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank0_bus_errors_we <= 1'd0;
builder_csr_bankarray_csrbank0_bus_errors_re <= 1'd0;
if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 2'd2))) begin
builder_csr_bankarray_csrbank0_bus_errors_re <= builder_csr_bankarray_interface0_bank_bus_we;
builder_csr_bankarray_csrbank0_bus_errors_we <= (~builder_csr_bankarray_interface0_bank_bus_we);
end
end
always @(*) begin
main_basesoc_soc_rst <= 1'd0;
if (main_basesoc_reset_re) begin
main_basesoc_soc_rst <= main_basesoc_reset_storage[0];
end
end
assign main_basesoc_cpu_rst = main_basesoc_reset_storage[1];
assign builder_csr_bankarray_csrbank0_reset0_w = main_basesoc_reset_storage[1:0];
assign builder_csr_bankarray_csrbank0_scratch0_w = main_basesoc_scratch_storage[31:0];
assign builder_csr_bankarray_csrbank0_bus_errors_w = main_basesoc_bus_errors_status[31:0];
assign main_basesoc_bus_errors_we = builder_csr_bankarray_csrbank0_bus_errors_we;
assign builder_csr_bankarray_sel = (builder_csr_bankarray_sram_bus_adr[13:9] == 1'd1);
always @(*) begin
builder_csr_bankarray_sram_bus_dat_r <= 32'd0;
if (builder_csr_bankarray_sel_r) begin
builder_csr_bankarray_sram_bus_dat_r <= builder_csr_bankarray_dat_r;
end
end
assign builder_csr_bankarray_adr = builder_csr_bankarray_sram_bus_adr[5:0];
assign builder_csr_bankarray_csrbank1_sel = (builder_csr_bankarray_interface1_bank_bus_adr[13:9] == 2'd2);
assign builder_csr_bankarray_csrbank1_load0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank1_load0_re <= 1'd0;
builder_csr_bankarray_csrbank1_load0_we <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin
builder_csr_bankarray_csrbank1_load0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_load0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_reload0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank1_reload0_we <= 1'd0;
builder_csr_bankarray_csrbank1_reload0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin
builder_csr_bankarray_csrbank1_reload0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_reload0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_en0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_en0_re <= 1'd0;
builder_csr_bankarray_csrbank1_en0_we <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin
builder_csr_bankarray_csrbank1_en0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_en0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_update_value0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_update_value0_we <= 1'd0;
builder_csr_bankarray_csrbank1_update_value0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd3))) begin
builder_csr_bankarray_csrbank1_update_value0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_update_value0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_value_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
builder_csr_bankarray_csrbank1_value_we <= 1'd0;
builder_csr_bankarray_csrbank1_value_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd4))) begin
builder_csr_bankarray_csrbank1_value_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_value_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_ev_status_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_ev_status_re <= 1'd0;
builder_csr_bankarray_csrbank1_ev_status_we <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd5))) begin
builder_csr_bankarray_csrbank1_ev_status_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_ev_status_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_ev_pending_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_ev_pending_re <= 1'd0;
builder_csr_bankarray_csrbank1_ev_pending_we <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd6))) begin
builder_csr_bankarray_csrbank1_ev_pending_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_ev_pending_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_ev_enable0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank1_ev_enable0_we <= 1'd0;
builder_csr_bankarray_csrbank1_ev_enable0_re <= 1'd0;
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 3'd7))) begin
builder_csr_bankarray_csrbank1_ev_enable0_re <= builder_csr_bankarray_interface1_bank_bus_we;
builder_csr_bankarray_csrbank1_ev_enable0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank1_load0_w = main_basesoc_timer_load_storage[31:0];
assign builder_csr_bankarray_csrbank1_reload0_w = main_basesoc_timer_reload_storage[31:0];
assign builder_csr_bankarray_csrbank1_en0_w = main_basesoc_timer_en_storage;
assign builder_csr_bankarray_csrbank1_update_value0_w = main_basesoc_timer_update_value_storage;
assign builder_csr_bankarray_csrbank1_value_w = main_basesoc_timer_value_status[31:0];
assign main_basesoc_timer_value_we = builder_csr_bankarray_csrbank1_value_we;
assign main_basesoc_timer_status_status = main_basesoc_timer_zero0;
assign builder_csr_bankarray_csrbank1_ev_status_w = main_basesoc_timer_status_status;
assign main_basesoc_timer_status_we = builder_csr_bankarray_csrbank1_ev_status_we;
assign main_basesoc_timer_pending_status = main_basesoc_timer_zero1;
assign builder_csr_bankarray_csrbank1_ev_pending_w = main_basesoc_timer_pending_status;
assign main_basesoc_timer_pending_we = builder_csr_bankarray_csrbank1_ev_pending_we;
assign main_basesoc_timer_zero2 = main_basesoc_timer_enable_storage;
assign builder_csr_bankarray_csrbank1_ev_enable0_w = main_basesoc_timer_enable_storage;
assign builder_csr_bankarray_csrbank2_sel = (builder_csr_bankarray_interface2_bank_bus_adr[13:9] == 2'd3);
assign main_basesoc_uart_rxtx_r = builder_csr_bankarray_interface2_bank_bus_dat_w[7:0];
always @(*) begin
main_basesoc_uart_rxtx_re <= 1'd0;
main_basesoc_uart_rxtx_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin
main_basesoc_uart_rxtx_re <= builder_csr_bankarray_interface2_bank_bus_we;
main_basesoc_uart_rxtx_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_txfull_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_txfull_re <= 1'd0;
builder_csr_bankarray_csrbank2_txfull_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd1))) begin
builder_csr_bankarray_csrbank2_txfull_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_txfull_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_rxempty_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_rxempty_re <= 1'd0;
builder_csr_bankarray_csrbank2_rxempty_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 2'd2))) begin
builder_csr_bankarray_csrbank2_rxempty_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_rxempty_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_ev_status_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank2_ev_status_we <= 1'd0;
builder_csr_bankarray_csrbank2_ev_status_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 2'd3))) begin
builder_csr_bankarray_csrbank2_ev_status_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_ev_status_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_ev_pending_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank2_ev_pending_we <= 1'd0;
builder_csr_bankarray_csrbank2_ev_pending_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd4))) begin
builder_csr_bankarray_csrbank2_ev_pending_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_ev_pending_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_ev_enable0_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0];
always @(*) begin
builder_csr_bankarray_csrbank2_ev_enable0_re <= 1'd0;
builder_csr_bankarray_csrbank2_ev_enable0_we <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd5))) begin
builder_csr_bankarray_csrbank2_ev_enable0_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_ev_enable0_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_txempty_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_txempty_we <= 1'd0;
builder_csr_bankarray_csrbank2_txempty_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd6))) begin
builder_csr_bankarray_csrbank2_txempty_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_txempty_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_rxfull_r = builder_csr_bankarray_interface2_bank_bus_dat_w[0];
always @(*) begin
builder_csr_bankarray_csrbank2_rxfull_we <= 1'd0;
builder_csr_bankarray_csrbank2_rxfull_re <= 1'd0;
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd7))) begin
builder_csr_bankarray_csrbank2_rxfull_re <= builder_csr_bankarray_interface2_bank_bus_we;
builder_csr_bankarray_csrbank2_rxfull_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
end
end
assign builder_csr_bankarray_csrbank2_txfull_w = main_basesoc_uart_txfull_status;
assign main_basesoc_uart_txfull_we = builder_csr_bankarray_csrbank2_txfull_we;
assign builder_csr_bankarray_csrbank2_rxempty_w = main_basesoc_uart_rxempty_status;
assign main_basesoc_uart_rxempty_we = builder_csr_bankarray_csrbank2_rxempty_we;
always @(*) begin
main_basesoc_uart_status_status <= 2'd0;
main_basesoc_uart_status_status[0] <= main_basesoc_uart_tx0;
main_basesoc_uart_status_status[1] <= main_basesoc_uart_rx0;
end
assign builder_csr_bankarray_csrbank2_ev_status_w = main_basesoc_uart_status_status[1:0];
assign main_basesoc_uart_status_we = builder_csr_bankarray_csrbank2_ev_status_we;
always @(*) begin
main_basesoc_uart_pending_status <= 2'd0;
main_basesoc_uart_pending_status[0] <= main_basesoc_uart_tx1;
main_basesoc_uart_pending_status[1] <= main_basesoc_uart_rx1;
end
assign builder_csr_bankarray_csrbank2_ev_pending_w = main_basesoc_uart_pending_status[1:0];
assign main_basesoc_uart_pending_we = builder_csr_bankarray_csrbank2_ev_pending_we;
assign main_basesoc_uart_tx2 = main_basesoc_uart_enable_storage[0];
assign main_basesoc_uart_rx2 = main_basesoc_uart_enable_storage[1];
assign builder_csr_bankarray_csrbank2_ev_enable0_w = main_basesoc_uart_enable_storage[1:0];
assign builder_csr_bankarray_csrbank2_txempty_w = main_basesoc_uart_txempty_status;
assign main_basesoc_uart_txempty_we = builder_csr_bankarray_csrbank2_txempty_we;
assign builder_csr_bankarray_csrbank2_rxfull_w = main_basesoc_uart_rxfull_status;
assign main_basesoc_uart_rxfull_we = builder_csr_bankarray_csrbank2_rxfull_we;
assign builder_csr_interconnect_adr = builder_basesoc_adr;
assign builder_csr_interconnect_we = builder_basesoc_we;
assign builder_csr_interconnect_dat_w = builder_basesoc_dat_w;
assign builder_basesoc_dat_r = builder_csr_interconnect_dat_r;
assign builder_csr_bankarray_interface0_bank_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_interface1_bank_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_interface2_bank_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_sram_bus_adr = builder_csr_interconnect_adr;
assign builder_csr_bankarray_interface0_bank_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_interface1_bank_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_interface2_bank_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_sram_bus_we = builder_csr_interconnect_we;
assign builder_csr_bankarray_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_bankarray_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_bankarray_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_bankarray_sram_bus_dat_w = builder_csr_interconnect_dat_w;
assign builder_csr_interconnect_dat_r = (((builder_csr_bankarray_interface0_bank_bus_dat_r | builder_csr_bankarray_interface1_bank_bus_dat_r) | builder_csr_bankarray_interface2_bank_bus_dat_r) | builder_csr_bankarray_sram_bus_dat_r);
assign main_basesoc_tx_cdc_produce_rdomain = builder_multiregimpl0_regs1;
assign main_basesoc_tx_cdc_consume_wdomain = builder_multiregimpl1_regs1;
assign main_basesoc_rx_cdc_produce_rdomain = builder_multiregimpl2_regs1;
assign main_basesoc_rx_cdc_consume_wdomain = builder_multiregimpl3_regs1;
//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------
always @(posedge jtag_clk) begin
builder_max10jtag_state <= builder_max10jtag_next_state;
main_basesoc_tx_cdc_graycounter1_q_binary <= main_basesoc_tx_cdc_graycounter1_q_next_binary;
main_basesoc_tx_cdc_graycounter1_q <= main_basesoc_tx_cdc_graycounter1_q_next;
main_basesoc_rx_cdc_graycounter0_q_binary <= main_basesoc_rx_cdc_graycounter0_q_next_binary;
main_basesoc_rx_cdc_graycounter0_q <= main_basesoc_rx_cdc_graycounter0_q_next;
builder_resetinserter_state <= builder_resetinserter_next_state;
if (main_basesoc_valid_next_value_ce0) begin
main_basesoc_valid <= main_basesoc_valid_next_value0;
end
if (main_basesoc_data_next_value_ce1) begin
main_basesoc_data <= main_basesoc_data_next_value1;
end
if (main_basesoc_count_next_value_ce2) begin
main_basesoc_count <= main_basesoc_count_next_value2;
end
if (main_basesoc_fsm_reset) begin
main_basesoc_valid <= 1'd0;
main_basesoc_data <= 8'd0;
main_basesoc_count <= 3'd0;
builder_resetinserter_state <= 2'd0;
end
if (jtag_rst) begin
main_basesoc_valid <= 1'd0;
main_basesoc_data <= 8'd0;
main_basesoc_count <= 3'd0;
main_basesoc_tx_cdc_graycounter1_q <= 3'd0;
main_basesoc_tx_cdc_graycounter1_q_binary <= 3'd0;
main_basesoc_rx_cdc_graycounter0_q <= 3'd0;
main_basesoc_rx_cdc_graycounter0_q_binary <= 3'd0;
builder_max10jtag_state <= 4'd0;
builder_resetinserter_state <= 2'd0;
end
builder_multiregimpl0_regs0 <= main_basesoc_tx_cdc_graycounter0_q;
builder_multiregimpl0_regs1 <= builder_multiregimpl0_regs0;
builder_multiregimpl3_regs0 <= main_basesoc_rx_cdc_graycounter1_q;
builder_multiregimpl3_regs1 <= builder_multiregimpl3_regs0;
end
always @(posedge jtag_inv_clk) begin
main_basesoc_jtag_reset <= main_basesoc_jtag_TEST_LOGIC_RESET;
main_basesoc_jtag_capture <= main_basesoc_jtag_CAPTURE_DR;
main_basesoc_jtag_tdouser <= main_basesoc_jtag_tdo;
if (jtag_inv_rst) begin
main_basesoc_jtag_reset <= 1'd0;
main_basesoc_jtag_capture <= 1'd0;
main_basesoc_jtag_tdouser <= 1'd0;
end
end
always @(posedge sys_clk) begin
if ((main_basesoc_bus_errors != 32'hffffffff)) begin
if (main_basesoc_bus_error) begin
main_basesoc_bus_errors <= (main_basesoc_bus_errors + 1'd1);
end
end
main_basesoc_ram_bus_ack <= 1'd0;
if (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & (~main_basesoc_ram_bus_ack))) begin
main_basesoc_ram_bus_ack <= 1'd1;
end
if (main_basesoc_uart_tx_clear) begin
main_basesoc_uart_tx_pending <= 1'd0;
end
main_basesoc_uart_tx_trigger_d <= main_basesoc_uart_tx_trigger;
if ((main_basesoc_uart_tx_trigger & (~main_basesoc_uart_tx_trigger_d))) begin
main_basesoc_uart_tx_pending <= 1'd1;
end
if (main_basesoc_uart_rx_clear) begin
main_basesoc_uart_rx_pending <= 1'd0;
end
main_basesoc_uart_rx_trigger_d <= main_basesoc_uart_rx_trigger;
if ((main_basesoc_uart_rx_trigger & (~main_basesoc_uart_rx_trigger_d))) begin
main_basesoc_uart_rx_pending <= 1'd1;
end
if (main_basesoc_uart_tx_fifo_syncfifo_re) begin
main_basesoc_uart_tx_fifo_readable <= 1'd1;
end else begin
if (main_basesoc_uart_tx_fifo_re) begin
main_basesoc_uart_tx_fifo_readable <= 1'd0;
end
end
if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin
main_basesoc_uart_tx_fifo_produce <= (main_basesoc_uart_tx_fifo_produce + 1'd1);
end
if (main_basesoc_uart_tx_fifo_do_read) begin
main_basesoc_uart_tx_fifo_consume <= (main_basesoc_uart_tx_fifo_consume + 1'd1);
end
if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin
if ((~main_basesoc_uart_tx_fifo_do_read)) begin
main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (main_basesoc_uart_tx_fifo_do_read) begin
main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 - 1'd1);
end
end
if (main_basesoc_uart_rx_fifo_syncfifo_re) begin
main_basesoc_uart_rx_fifo_readable <= 1'd1;
end else begin
if (main_basesoc_uart_rx_fifo_re) begin
main_basesoc_uart_rx_fifo_readable <= 1'd0;
end
end
if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin
main_basesoc_uart_rx_fifo_produce <= (main_basesoc_uart_rx_fifo_produce + 1'd1);
end
if (main_basesoc_uart_rx_fifo_do_read) begin
main_basesoc_uart_rx_fifo_consume <= (main_basesoc_uart_rx_fifo_consume + 1'd1);
end
if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin
if ((~main_basesoc_uart_rx_fifo_do_read)) begin
main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (main_basesoc_uart_rx_fifo_do_read) begin
main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 - 1'd1);
end
end
if (main_basesoc_timer_en_storage) begin
if ((main_basesoc_timer_value == 1'd0)) begin
main_basesoc_timer_value <= main_basesoc_timer_reload_storage;
end else begin
main_basesoc_timer_value <= (main_basesoc_timer_value - 1'd1);
end
end else begin
main_basesoc_timer_value <= main_basesoc_timer_load_storage;
end
if (main_basesoc_timer_update_value_re) begin
main_basesoc_timer_value_status <= main_basesoc_timer_value;
end
if (main_basesoc_timer_zero_clear) begin
main_basesoc_timer_zero_pending <= 1'd0;
end
main_basesoc_timer_zero_trigger_d <= main_basesoc_timer_zero_trigger;
if ((main_basesoc_timer_zero_trigger & (~main_basesoc_timer_zero_trigger_d))) begin
main_basesoc_timer_zero_pending <= 1'd1;
end
builder_state <= builder_next_state;
builder_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0;
if (builder_csr_bankarray_csrbank0_sel) begin
case (builder_csr_bankarray_interface0_bank_bus_adr[8:0])
1'd0: begin
builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_reset0_w;
end
1'd1: begin
builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_scratch0_w;
end
2'd2: begin
builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_bus_errors_w;
end
endcase
end
if (builder_csr_bankarray_csrbank0_reset0_re) begin
main_basesoc_reset_storage[1:0] <= builder_csr_bankarray_csrbank0_reset0_r;
end
main_basesoc_reset_re <= builder_csr_bankarray_csrbank0_reset0_re;
if (builder_csr_bankarray_csrbank0_scratch0_re) begin
main_basesoc_scratch_storage[31:0] <= builder_csr_bankarray_csrbank0_scratch0_r;
end
main_basesoc_scratch_re <= builder_csr_bankarray_csrbank0_scratch0_re;
main_basesoc_bus_errors_re <= builder_csr_bankarray_csrbank0_bus_errors_re;
builder_csr_bankarray_sel_r <= builder_csr_bankarray_sel;
builder_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0;
if (builder_csr_bankarray_csrbank1_sel) begin
case (builder_csr_bankarray_interface1_bank_bus_adr[8:0])
1'd0: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_load0_w;
end
1'd1: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_reload0_w;
end
2'd2: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_en0_w;
end
2'd3: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_update_value0_w;
end
3'd4: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_value_w;
end
3'd5: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_ev_status_w;
end
3'd6: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_ev_pending_w;
end
3'd7: begin
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_ev_enable0_w;
end
endcase
end
if (builder_csr_bankarray_csrbank1_load0_re) begin
main_basesoc_timer_load_storage[31:0] <= builder_csr_bankarray_csrbank1_load0_r;
end
main_basesoc_timer_load_re <= builder_csr_bankarray_csrbank1_load0_re;
if (builder_csr_bankarray_csrbank1_reload0_re) begin
main_basesoc_timer_reload_storage[31:0] <= builder_csr_bankarray_csrbank1_reload0_r;
end
main_basesoc_timer_reload_re <= builder_csr_bankarray_csrbank1_reload0_re;
if (builder_csr_bankarray_csrbank1_en0_re) begin
main_basesoc_timer_en_storage <= builder_csr_bankarray_csrbank1_en0_r;
end
main_basesoc_timer_en_re <= builder_csr_bankarray_csrbank1_en0_re;
if (builder_csr_bankarray_csrbank1_update_value0_re) begin
main_basesoc_timer_update_value_storage <= builder_csr_bankarray_csrbank1_update_value0_r;
end
main_basesoc_timer_update_value_re <= builder_csr_bankarray_csrbank1_update_value0_re;
main_basesoc_timer_value_re <= builder_csr_bankarray_csrbank1_value_re;
main_basesoc_timer_status_re <= builder_csr_bankarray_csrbank1_ev_status_re;
if (builder_csr_bankarray_csrbank1_ev_pending_re) begin
main_basesoc_timer_pending_r <= builder_csr_bankarray_csrbank1_ev_pending_r;
end
main_basesoc_timer_pending_re <= builder_csr_bankarray_csrbank1_ev_pending_re;
if (builder_csr_bankarray_csrbank1_ev_enable0_re) begin
main_basesoc_timer_enable_storage <= builder_csr_bankarray_csrbank1_ev_enable0_r;
end
main_basesoc_timer_enable_re <= builder_csr_bankarray_csrbank1_ev_enable0_re;
builder_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0;
if (builder_csr_bankarray_csrbank2_sel) begin
case (builder_csr_bankarray_interface2_bank_bus_adr[8:0])
1'd0: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= main_basesoc_uart_rxtx_w;
end
1'd1: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_txfull_w;
end
2'd2: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_rxempty_w;
end
2'd3: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_ev_status_w;
end
3'd4: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_ev_pending_w;
end
3'd5: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_ev_enable0_w;
end
3'd6: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_txempty_w;
end
3'd7: begin
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_rxfull_w;
end
endcase
end
main_basesoc_uart_txfull_re <= builder_csr_bankarray_csrbank2_txfull_re;
main_basesoc_uart_rxempty_re <= builder_csr_bankarray_csrbank2_rxempty_re;
main_basesoc_uart_status_re <= builder_csr_bankarray_csrbank2_ev_status_re;
if (builder_csr_bankarray_csrbank2_ev_pending_re) begin
main_basesoc_uart_pending_r[1:0] <= builder_csr_bankarray_csrbank2_ev_pending_r;
end
main_basesoc_uart_pending_re <= builder_csr_bankarray_csrbank2_ev_pending_re;
if (builder_csr_bankarray_csrbank2_ev_enable0_re) begin
main_basesoc_uart_enable_storage[1:0] <= builder_csr_bankarray_csrbank2_ev_enable0_r;
end
main_basesoc_uart_enable_re <= builder_csr_bankarray_csrbank2_ev_enable0_re;
main_basesoc_uart_txempty_re <= builder_csr_bankarray_csrbank2_txempty_re;
main_basesoc_uart_rxfull_re <= builder_csr_bankarray_csrbank2_rxfull_re;
if (sys_rst) begin
main_basesoc_reset_storage <= 2'd0;
main_basesoc_reset_re <= 1'd0;
main_basesoc_scratch_storage <= 32'd305419896;
main_basesoc_scratch_re <= 1'd0;
main_basesoc_bus_errors_re <= 1'd0;
main_basesoc_bus_errors <= 32'd0;
main_basesoc_ram_bus_ack <= 1'd0;
main_basesoc_uart_txfull_re <= 1'd0;
main_basesoc_uart_rxempty_re <= 1'd0;
main_basesoc_uart_tx_pending <= 1'd0;
main_basesoc_uart_tx_trigger_d <= 1'd0;
main_basesoc_uart_rx_pending <= 1'd0;
main_basesoc_uart_rx_trigger_d <= 1'd0;
main_basesoc_uart_status_re <= 1'd0;
main_basesoc_uart_pending_re <= 1'd0;
main_basesoc_uart_pending_r <= 2'd0;
main_basesoc_uart_enable_storage <= 2'd0;
main_basesoc_uart_enable_re <= 1'd0;
main_basesoc_uart_txempty_re <= 1'd0;
main_basesoc_uart_rxfull_re <= 1'd0;
main_basesoc_uart_tx_fifo_readable <= 1'd0;
main_basesoc_uart_tx_fifo_level0 <= 5'd0;
main_basesoc_uart_tx_fifo_produce <= 4'd0;
main_basesoc_uart_tx_fifo_consume <= 4'd0;
main_basesoc_uart_rx_fifo_readable <= 1'd0;
main_basesoc_uart_rx_fifo_level0 <= 5'd0;
main_basesoc_uart_rx_fifo_produce <= 4'd0;
main_basesoc_uart_rx_fifo_consume <= 4'd0;
main_basesoc_timer_load_storage <= 32'd0;
main_basesoc_timer_load_re <= 1'd0;
main_basesoc_timer_reload_storage <= 32'd0;
main_basesoc_timer_reload_re <= 1'd0;
main_basesoc_timer_en_storage <= 1'd0;
main_basesoc_timer_en_re <= 1'd0;
main_basesoc_timer_update_value_storage <= 1'd0;
main_basesoc_timer_update_value_re <= 1'd0;
main_basesoc_timer_value_status <= 32'd0;
main_basesoc_timer_value_re <= 1'd0;
main_basesoc_timer_zero_pending <= 1'd0;
main_basesoc_timer_zero_trigger_d <= 1'd0;
main_basesoc_timer_status_re <= 1'd0;
main_basesoc_timer_pending_re <= 1'd0;
main_basesoc_timer_pending_r <= 1'd0;
main_basesoc_timer_enable_storage <= 1'd0;
main_basesoc_timer_enable_re <= 1'd0;
main_basesoc_timer_value <= 32'd0;
builder_csr_bankarray_sel_r <= 1'd0;
builder_state <= 1'd0;
end
end
always @(posedge sys_jtag_clk) begin
main_basesoc_tx_cdc_graycounter0_q_binary <= main_basesoc_tx_cdc_graycounter0_q_next_binary;
main_basesoc_tx_cdc_graycounter0_q <= main_basesoc_tx_cdc_graycounter0_q_next;
main_basesoc_rx_cdc_graycounter1_q_binary <= main_basesoc_rx_cdc_graycounter1_q_next_binary;
main_basesoc_rx_cdc_graycounter1_q <= main_basesoc_rx_cdc_graycounter1_q_next;
if (sys_jtag_rst) begin
main_basesoc_tx_cdc_graycounter0_q <= 3'd0;
main_basesoc_tx_cdc_graycounter0_q_binary <= 3'd0;
main_basesoc_rx_cdc_graycounter1_q <= 3'd0;
main_basesoc_rx_cdc_graycounter1_q_binary <= 3'd0;
end
builder_multiregimpl1_regs0 <= main_basesoc_tx_cdc_graycounter1_q;
builder_multiregimpl1_regs1 <= builder_multiregimpl1_regs0;
builder_multiregimpl2_regs0 <= main_basesoc_rx_cdc_graycounter0_q;
builder_multiregimpl2_regs1 <= builder_multiregimpl2_regs0;
end
//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Memory mem: 2048-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
reg [31:0] mem[0:2047];
initial begin
$readmemh("mem.init", mem);
end
reg [10:0] mem_adr0;
always @(posedge sys_clk) begin
if (main_basesoc_we[0])
mem[main_basesoc_adr][7:0] <= main_basesoc_dat_w[7:0];
if (main_basesoc_we[1])
mem[main_basesoc_adr][15:8] <= main_basesoc_dat_w[15:8];
if (main_basesoc_we[2])
mem[main_basesoc_adr][23:16] <= main_basesoc_dat_w[23:16];
if (main_basesoc_we[3])
mem[main_basesoc_adr][31:24] <= main_basesoc_dat_w[31:24];
mem_adr0 <= main_basesoc_adr;
end
assign main_basesoc_dat_r = mem[mem_adr0];
//------------------------------------------------------------------------------
// Memory mem_1: 46-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: ---- |
reg [7:0] mem_1[0:45];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [5:0] mem_1_adr0;
always @(posedge sys_clk) begin
mem_1_adr0 <= builder_csr_bankarray_adr;
end
assign builder_csr_bankarray_dat_r = mem_1[mem_1_adr0];
fiftyfivenm_jtag fiftyfivenm_jtag(
.tck(main_basesoc_jtag_altera_reserved_tck),
.tdi(main_basesoc_jtag_altera_reserved_tdi),
.tdouser(main_basesoc_jtag_tdouser),
.tms(main_basesoc_jtag_altera_reserved_tms),
.clkdruser(main_basesoc_jtag_drck),
.runidleuser(main_basesoc_jtag_runtest),
.shiftuser(main_basesoc_jtag_shift),
.tckutap(main_basesoc_jtag_tckutap),
.tdiutap(main_basesoc_jtag_tdiutap),
.tdo(main_basesoc_jtag_altera_reserved_tdo),
.tmsutap(main_basesoc_jtag_tmsutap),
.updateuser(main_basesoc_jtag_update),
.usr1user(main_basesoc_jtag_sel)
);
//------------------------------------------------------------------------------
// Memory storage: 4-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage[0:3];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
always @(posedge sys_jtag_clk) begin
if (main_basesoc_tx_cdc_wrport_we)
storage[main_basesoc_tx_cdc_wrport_adr] <= main_basesoc_tx_cdc_wrport_dat_w;
storage_dat0 <= storage[main_basesoc_tx_cdc_wrport_adr];
end
always @(posedge jtag_clk) begin
storage_dat1 <= storage[main_basesoc_tx_cdc_rdport_adr];
end
assign main_basesoc_tx_cdc_wrport_dat_r = storage_dat0;
assign main_basesoc_tx_cdc_rdport_dat_r = storage_dat1;
//------------------------------------------------------------------------------
// Memory storage_1: 4-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_1[0:3];
reg [9:0] storage_1_dat0;
reg [9:0] storage_1_dat1;
always @(posedge jtag_clk) begin
if (main_basesoc_rx_cdc_wrport_we)
storage_1[main_basesoc_rx_cdc_wrport_adr] <= main_basesoc_rx_cdc_wrport_dat_w;
storage_1_dat0 <= storage_1[main_basesoc_rx_cdc_wrport_adr];
end
always @(posedge sys_jtag_clk) begin
storage_1_dat1 <= storage_1[main_basesoc_rx_cdc_rdport_adr];
end
assign main_basesoc_rx_cdc_wrport_dat_r = storage_1_dat0;
assign main_basesoc_rx_cdc_rdport_dat_r = storage_1_dat1;
//------------------------------------------------------------------------------
// Memory storage_2: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_2[0:15];
reg [9:0] storage_2_dat0;
reg [9:0] storage_2_dat1;
always @(posedge sys_clk) begin
if (main_basesoc_uart_tx_fifo_wrport_we)
storage_2[main_basesoc_uart_tx_fifo_wrport_adr] <= main_basesoc_uart_tx_fifo_wrport_dat_w;
storage_2_dat0 <= storage_2[main_basesoc_uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_basesoc_uart_tx_fifo_rdport_re)
storage_2_dat1 <= storage_2[main_basesoc_uart_tx_fifo_rdport_adr];
end
assign main_basesoc_uart_tx_fifo_wrport_dat_r = storage_2_dat0;
assign main_basesoc_uart_tx_fifo_rdport_dat_r = storage_2_dat1;
//------------------------------------------------------------------------------
// Memory storage_3: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_3[0:15];
reg [9:0] storage_3_dat0;
reg [9:0] storage_3_dat1;
always @(posedge sys_clk) begin
if (main_basesoc_uart_rx_fifo_wrport_we)
storage_3[main_basesoc_uart_rx_fifo_wrport_adr] <= main_basesoc_uart_rx_fifo_wrport_dat_w;
storage_3_dat0 <= storage_3[main_basesoc_uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_basesoc_uart_rx_fifo_rdport_re)
storage_3_dat1 <= storage_3[main_basesoc_uart_rx_fifo_rdport_adr];
end
assign main_basesoc_uart_rx_fifo_wrport_dat_r = storage_3_dat0;
assign main_basesoc_uart_rx_fifo_rdport_dat_r = storage_3_dat1;
ALTPLL #(
.BANDWIDTH_TYPE("AUTO"),
.CLK0_DIVIDE_BY(5'd25),
.CLK0_DUTY_CYCLE(6'd50),
.CLK0_MULTIPLY_BY(5'd25),
.CLK0_PHASE_SHIFT(1'd0),
.CLK1_DIVIDE_BY(5'd31),
.CLK1_DUTY_CYCLE(6'd50),
.CLK1_MULTIPLY_BY(5'd25),
.CLK1_PHASE_SHIFT(1'd0),
.COMPENSATE_CLOCK("CLK0"),
.INCLK0_INPUT_FREQUENCY(15'd20000),
.OPERATION_MODE("NORMAL")
) ALTPLL (
.ARESET(1'd0),
.CLKENA(5'd31),
.EXTCLKENA(4'd15),
.FBIN(1'd1),
.INCLK(main_crg_clkin),
.PFDENA(1'd1),
.PLLENA(1'd1),
.CLK(builder_clks),
.LOCKED(main_crg_locked)
);
DFF DFF(
.clk(jtag_clk),
.clrn(1'd1),
.d(1'd0),
.prn((~sys_jtag_rst)),
.q(builder_rst_meta0)
);
DFF DFF_1(
.clk(jtag_clk),
.clrn(1'd1),
.d(builder_rst_meta0),
.prn((~sys_jtag_rst)),
.q(jtag_rst)
);
DFF DFF_2(
.clk(sys_clk),
.clrn(1'd1),
.d(1'd0),
.prn((~(~main_crg_locked))),
.q(builder_rst_meta1)
);
DFF DFF_3(
.clk(sys_clk),
.clrn(1'd1),
.d(builder_rst_meta1),
.prn((~(~main_crg_locked))),
.q(sys_rst)
);
DFF DFF_4(
.clk(hdmi_clk),
.clrn(1'd1),
.d(1'd0),
.prn((~(~main_crg_locked))),
.q(builder_rst_meta2)
);
DFF DFF_5(
.clk(hdmi_clk),
.clrn(1'd1),
.d(builder_rst_meta2),
.prn((~(~main_crg_locked))),
.q(hdmi_rst)
);
endmodule
// -----------------------------------------------------------------------------
// Auto-Generated by LiteX on 2022-02-08 16:31:25.
//------------------------------------------------------------------------------
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