LiteX IO PinRefs

pinref.py

# Implementation:
# https://github.com/jevinskie/litex/blob/52ade48db1d23c59e96ab0955174998af01faf41/litex/build/generic_platform.py#L44
# https://github.com/jevinskie/litex/blob/52ade48db1d23c59e96ab0955174998af01faf41/litex/build/altera/quartus.py#L36

_io = [
    # DDR3 SDRAM.
    ("ddram", 0,
        Subsignal("dm", Pins("N19 J15"),
            IOStandard("SSTL-15"),
            Misc("DM_PIN ON")
        ),
        Subsignal("dq", Pins(
            "L20 L19 L18 M15 M18 M14 M20 N20",
            "K19 K18 J18 K20 H18 J20 H20 H19"),
        ),
        Subsignal("dqs_p", Pins("L14 K14"),
            IOStandard("DIFFERENTIAL 1.5-V SSTL"),
            Misc('OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION"'),
            # set_instance_assignment -comment "ddram:0.dqs_p" -name DQ_GROUP 9 -from ddram_dqs_p[0] -to ddram_dq[0..7]
            Misc(["DQ_GROUP 9", PinRef(identity=True, subidx=0), PinRef(subsignal="dq", subidx=slice(8), relative=True)]),
            Misc(["DQ_GROUP 9", PinRef(identity=True, subidx=1), PinRef(subsignal="dq", subidx=slice(8, 16), relative=True)]),
            Misc(["DQ_GROUP 9", PinRef(identity=True, subidx=0), PinRef(subsignal="dm", subidx=0, relative=True)]),
            Misc(["DQ_GROUP 9", PinRef(identity=True, subidx=1), PinRef(subsignal="dm", subidx=1, relative=True)])
        ),
        Subsignal("clk_p", Pins("D18"),
            IOStandard("DIFFERENTIAL 1.5-V SSTL"),
            Misc('OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION"'),
        ),
        Subsignal("clk_n", Pins("E18"),
            IOStandard("DIFFERENTIAL 1.5-V SSTL"),
            Misc('OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION"'),
            # set_instance_assignment -comment "ddram:0.clk_n" -name CKN_CK_PAIR ON -from ddram_clk_n -to ddram_clk_p
            Misc(["CKN_CK_PAIR ON", PinRef(subsignal="clk_p", relative=True)])
        ),
    ),
]