# Python 2.7 and 2.6 install script for CentOS 7
# Instructions mainly taken from tutorial by Daniel Eriksson
# Functions to calculate APPROXIMATE range, bearing, and XY offset between two lat/long positions
# Uses the Haversine Formula
# See for more details
# Math library needed for cos, sine, atan2, sqrt, degrees, and radians
import math
# This is the mean radius of the earth in metres
EARTH_RADIUS = 6371000.0
View config.cpp
#include <iostream>
#include <fstream>
#include <string>
#include <algorithm>
#include <sstream>
using namespace std;
struct ad9361Config{
int rxFrequency;
View enigma.c
//Emulates the output of a WWII German Enigma encryption machine
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//#define DEBUG
//Strut Prototypes
View FPGA_VGA.vhd
--An FPGA version of the classic pong game
--Score counts up to 9
--Right player uses buttons 0 and 1
--Left player uses Switch 0 (Much harder!)
--Button 2 resets the game and score
library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;
entity FPGA_VGA is
View hello_world.c
* "Hello World" example.
* This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
* the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
* designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
* device in your system's hardware.
* The memory footprint of this hosted application is ~69 kbytes by default
* using the standard reference design.
View pll_test.vhd
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all;
--This example shows how different speed signals can be created using both a counter method and a PLL
--PLL are very powerful and can be used to generate both fast or slower clk speeds as well as changing the phase of the signal.
--There are a limited amount of PLLs on an FPGA however a single PLL block in the FPGA can often be used to generate several different frequencies.
entity pll_test is port (
CLOCK_50 : in std_logic;
SW : in std_logic_vector(9 downto 0);
LEDG : OUT std_logic_vector(9 downto 0)
View frisbee.bgproj
<?xml version="1.0" encoding="UTF-8" ?>
<gatt in="gatt.xml" />
<hardware in="hardware.xml" />
<script in="frisbee.bgs" />
<image out="BLE112.hex" />
<device type="ble112" />
<boot fw="bootuart" />
View LCD_LIB.c
* File: LCD_LIB.c
* Author: James Gibbard
* Description: Display library for operating 16x2 Hitachi HD44780 type displays
* Created on 24 April 2013, 15:23
#include <xc.h>
#include "LCD_LIB.h"
#include <stdio.h>