jgibbard

--VHDL VGA PONG demo
--An FPGA version of the classic pong game
--Score counts up to 9
--Right player uses buttons 0 and 1
--Left player uses Switch 0 (Much harder!)
--Button 2 resets the game and score

library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

entity FPGA_VGA is 

jgibbard

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all;

--This example shows how different speed signals can be created using both a counter method and a PLL
--PLL are very powerful and can be used to generate both fast or slower clk speeds as well as changing the phase of the signal.
--There are a limited amount of PLLs on an FPGA however a single PLL block in the FPGA can often be used to generate several different frequencies.

entity pll_test is port (
	CLOCK_50 : in std_logic;
	SW			: in std_logic_vector(9 downto 0);
	LEDG		: OUT std_logic_vector(9 downto 0)

jgibbard

<?xml version="1.0" encoding="UTF-8" ?>
<project>
    <gatt in="gatt.xml" />
    <hardware in="hardware.xml" />    
    <script in="frisbee.bgs" />
    <image out="BLE112.hex" />  
    <device type="ble112" />
	<boot fw="bootuart" />
</project>

jgibbard

/* 
 * File:   LCD_LIB.c
 * Author: James Gibbard
 * Description: Display library for operating 16x2 Hitachi HD44780 type displays
 * Created on 24 April 2013, 15:23
 */

#include <xc.h>
#include "LCD_LIB.h"
#include <stdio.h>