jijingg

  /**
    * Take lowerst n bits
    * @example {{{ val res = data10bits.take(4) }}}
    * @return data10bits(3 downto 0)
    */
  def take(n: Int): Bits = {
    val hsbpos = n - 1
    val lsbpos = 0
    this(hsbpos downto lsbpos)
  }

jijingg

// Generator : SpinalHDL v1.3.8    git head : 8e3601528eafdc014e27c2cfb3caa69454d6ff27
// Date      : 01/02/2020, 14:03:47
// Component : T2


module T2 (
      input  [15:0] a);
  wire [10:0] _zz_15_;
  wire [9:0] _zz_16_;
  wire [16:0] _zz_17_;

jijingg

// Generator : SpinalHDL v1.3.9    git head : 1e13681878fae2d43f3bac35289fbb97baa321d1
// Date      : 01/02/2020, 15:06:47
// Component : T2


module SInt16fixTo5_0_ROUNDTOINF (
      input  [15:0] din,
      output [5:0] dout);
  wire [10:0] _zz_2_;
  wire [9:0] _zz_3_;