ex_amend.eqy

[gold]
read_rtlil <<EOF
  module \top
    wire $gate_0
    wire width 2 $gate_1
    wire width 2 $gate_2
    wire input 1 \A
    wire width 2 output 4 \X
    wire width 2 output 5 \Y
    cell $not \13
      parameter \A_SIGNED 0
      parameter \A_WIDTH 2
      parameter \Y_WIDTH 2
      connect \A $gate_1
      connect \Y $gate_2
    end
    cell $not \2
      parameter \A_SIGNED 0
      parameter \A_WIDTH 1
      parameter \Y_WIDTH 1
      connect \A \A
      connect \Y $gate_0
    end
    cell $not \8
      parameter \A_SIGNED 0
      parameter \A_WIDTH 2
      parameter \Y_WIDTH 2
      connect \A { 1'0 $gate_0 }
      connect \Y $gate_1
    end
    connect \X $gate_1
    connect \Y $gate_2
  end
EOF

show -format png -prefix gold top

[gate]
read_rtlil <<EOF
  module \top
    wire $gold_0
    wire $gold_1
    wire $gold_2
    wire width 2 $gold_3
    wire width 2 $gold_4
    wire input 1 \A
    wire width 2 output 4 \X
    wire width 2 output 5 \Y
    cell $not \11
      parameter \A_SIGNED 0
      parameter \A_WIDTH 2
      parameter \Y_WIDTH 2
      connect \A { 1'0 $gold_2 }
      connect \Y $gold_3
    end
    cell $xor \13
      parameter \A_SIGNED 0
      parameter \A_WIDTH 2
      parameter \B_SIGNED 0
      parameter \B_WIDTH 2
      parameter \Y_WIDTH 2
      connect \A 2'01
      connect \B $gold_3
      connect \Y $gold_4
    end
    cell $not \2
      parameter \A_SIGNED 0
      parameter \A_WIDTH 1
      parameter \Y_WIDTH 1
      connect \A \A
      connect \Y $gold_0
    end
    cell $not \7
      parameter \A_SIGNED 0
      parameter \A_WIDTH 1
      parameter \Y_WIDTH 1
      connect \A \A
      connect \Y $gold_2
    end
    connect \X { $gold_0 $gold_0 }
    connect \Y $gold_4
  end
EOF

show -format png -prefix gate top

[script]
prep -top top
check -assert

[collect top]
join X
join Y

[partition top]
amend X

[strategy simple]
use sat
depth 10