Skip to content

Instantly share code, notes, and snippets.

View joaocarlos's full-sized avatar

João Carlos N. Bittencourt joaocarlos

View GitHub Profile
@joaocarlos
joaocarlos / de2_115_default.sdc
Created September 6, 2022 01:58
Arquivo de restrições para a placa DE2-115 utilizado no projeto do somador Lookahead.
#**************************************************************
# This .sdc file is created by Terasic Tool.
# Users are recommended to modify this file to match users logic.
#**************************************************************
#**************************************************************
# Create Clock
#**************************************************************
create_clock -add -name sys_clk_pin -period 20 -waveform {0 10} [get_ports clk]
# create_clock -add -name sys_clk_pin -period 20 -waveform {0 10} [get_ports CLOCK_50]
@joaocarlos
joaocarlos / full_adder.v
Last active September 6, 2022 01:26
Somador completo.
/////////////////////////////////////////////////////////////////////////////
// GCET231 - Circuitos Digitais II
///////////////////////////////////////////////////////////////////////////////
// File Downloaded from http://www.nandland.com
///////////////////////////////////////////////////////////////////////////////
module full_adder
(
i_bit1,
i_bit2,
i_carry,
@joaocarlos
joaocarlos / carry_lookahead_adder_4_bit.v
Last active September 6, 2022 01:25
Somador Carry Lookahead de 4 bits, construído a partir de 4 somadores completos.
/////////////////////////////////////////////////////////////////////////////
// GCET231 - Circuitos Digitais II
/////////////////////////////////////////////////////////////////////////////
// File Downloaded from http://www.nandland.com
/////////////////////////////////////////////////////////////////////////////
module carry_lookahead_adder_4_bit
(
input clk, rst,
input [3:0] add1,
input [3:0] add2,
@joaocarlos
joaocarlos / adder_tb.sv
Created May 4, 2022 00:18
Test bench for an adder circuito in SystemVerilog
`timescale 1ns/1ps
module adder_tb();
reg [31:0] a, b;
wire [31:0] c;
adder dut (.a(a), .b(b), .c(c)); // device under test
initial begin
$dumpfile("adder.vcd");
@joaocarlos
joaocarlos / modelsim_installation.md
Created October 22, 2020 19:03 — forked from robodhruv/modelsim_installation.md
Sorting ModelSim installation issues

ModelSim Installation issues

Ubuntu 14.xx and above

Ignore this if you have not encountered any issue with the installation and running of ModelSim and Quartus on your system. You are very lucky. (Just Kidding! You have surely had this issue, only sorted.)

Hence assuming you have been following the procedure given in this guide. Most certainly, Quartus will install jsut fine, and so will ModelSim. The issue is in launching due to inappropriate linking etc.

Stage 1

This is the simplest error you would encounter. Navigate to the modelsim_ase folder and run:

@joaocarlos
joaocarlos / install_quartus17.sh
Created August 26, 2020 02:29 — forked from arthurbeggs/install_quartus17.sh
Install Quartus Prime Lite 17.0 in Ubuntu
#!/bin/bash
################################################################################
### Install Quartus and ModelSim ###
################################################################################
# Source code at https://github.com/arthurbeggs/scripts #
################################################################################
# #
# Based on https://github.com/jessebarreto/ConfigureWorkspace script. #
# #