joelagnel

joelagnel

joelagnel

joelagnel

joelagnel

joelagnel

commit 0472f75681d9d9e5ee12b063c4cfa96bbe295519
Author: Joel Fernandes <joelaf@google.com>
Date:   Mon Aug 21 23:20:14 2017 -0700

    wake partner count: first cut
    
    Signed-off-by: Joel Fernandes <joelaf@google.com>

diff --git a/include/linux/sched.h b/include/linux/sched.h
index 8d3bee6221ea..45180f834b81 100644

joelagnel

[  199.387105] [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
[  199.387210] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
[  199.387308] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
[  199.387547] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
[  199.446402] [drm:drm_mode_addfb2 [drm]] [FB:133]
[  200.046399] [drm:drm_mode_addfb2 [drm]] [FB:95]
[  200.649363] [drm:drm_mode_addfb2 [drm]] [FB:133]
[  201.232812] [UFW BLOCK] IN=wlp4s0 OUT= MAC=ff:ff:ff:ff:ff:ff:14:cc:20:3d:2f:4a:08:00 SRC=192.168.0.1 DST=255.255.255.255 LEN=201 TOS=0x00 PREC=0x00 TTL=64 ID=0 DF PROTO=UDP SPT=42387 DPT=7437 LEN=181 
[  201.249606] [drm:drm_mode_addfb2 [drm]] [FB:95]
[  201.851507] [drm:drm_mode_addfb2 [drm]] [FB:133]

joelagnel

#!/bin/bash

rm /tmp/make-out* /tmp/make-error* >/dev/null 2>&1
make $@ 2>&1 | tee /tmp/make-out-all-tmp
grep error: /tmp/make-out-all-tmp > /tmp/make-out-tmp
if [ $? -ne 0 ]; then exit; fi

MAKE_NCURSES_SCRIPT=/tmp/make-ncurses-errors-script.py
cat > $MAKE_NCURSES_SCRIPT <<END
#!/usr/bin/python

joelagnel

/* This version is borrowed from perfbook's QRCU
 * However: The intention here is not to have a performant
 * QRCU if written this way in the real world, but to have
 * a functionally correct and model-friendly RCU.
 * with least complexity in Promela/Spin.
 *
 * Main changes from QRCU are:
 * 1. Removed fast/slow paths in synchronize_rcu.
 * 2. Made ctr and idx updates as atomic.
 * 3. Removed sum_unordered.

joelagnel

The Message Passing pattern (MP pattern) is shown below in the snippet below. P0 and P1 are 2 CPUs executing some code. The pattern has P0 store a message to `buf` and then signal to consumers like P1 that the message is available -- by doing a store to `flag`. Without memory barriers between P0's stores, the stores can appear to be out of order to P1, thus breaking the pattern. The condition "r1 == 0 and r2 == 1" is a failure and show never occur. Only after flag is updated, should we read the buf ("message").

```
        int buf = 0, flag = 0;

        P0()
        {
                WRITE_ONCE(buf, 1);
                WRITE_ONCE(flag, 1);
        }