Propuesta del puerto de I/O para JPU16

JPU16_GPIO.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.JPU16_Pack.all;

package JPU16_GPIO_Pack is
   component JPU16_GPIO is
   generic (nDataBits: integer := 16;
            Data_Addr: JPU16_IO_ADDR_BUS := X"4000";
            Data_Mask: JPU16_IO_ADDR_BUS := X"4000";
            DDR_Addr: JPU16_IO_ADDR_BUS := X"8000";
            DDR_Mask: JPU16_IO_ADDR_BUS := X"8000");
   port (SysClk:   in  STD_LOGIC;
         Reset:    in  STD_LOGIC;
         SysHold:  in  STD_LOGIC;
         IO_Din:   out JPU16_INPUT_BUS;
         IO_Dout:  in JPU16_OUTPUT_BUS;
         IO_Addr:  in JPU16_IO_ADDR_BUS;
         IO_RD:    in STD_LOGIC;
         IO_WR:    in STD_LOGIC;
         DataPort: inout STD_LOGIC_VECTOR (nDataBits-1 downto 0));
   end component;
end package;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.JPU16_Pack.all;

entity JPU16_GPIO is
   generic (nDataBits: integer := 16;
            Data_Addr: JPU16_IO_ADDR_BUS := X"4000";
            Data_Mask: JPU16_IO_ADDR_BUS := X"4000";
            DDR_Addr: JPU16_IO_ADDR_BUS := X"8000";
            DDR_Mask: JPU16_IO_ADDR_BUS := X"8000");
   port (SysClk:   in  STD_LOGIC;
         Reset:    in  STD_LOGIC;
         SysHold:  in  STD_LOGIC;
         IO_Din:   out JPU16_INPUT_BUS;
         IO_Dout:  in JPU16_OUTPUT_BUS;
         IO_Addr:  in JPU16_IO_ADDR_BUS;
         IO_RD:    in STD_LOGIC;
         IO_WR:    in STD_LOGIC;
         DataPort: inout STD_LOGIC_VECTOR (nDataBits-1 downto 0));
end JPU16_GPIO;

architecture Funcionamiento of JPU16_GPIO is
   signal DataOutReg: STD_LOGIC_VECTOR (nDataBits-1 downto 0) := (others => '0');
   signal DDR: STD_LOGIC_VECTOR (nDataBits-1 downto 0) := (others => '0');

   signal DDR_Sel: STD_LOGIC;
   signal Data_Sel: STD_LOGIC;
begin
   DDR_Sel <= '1' when SysHold = '0' and (IO_Addr and DDR_Mask) = DDR_Addr else '0';
   Data_Sel <= '1' when SysHold = '0' and (IO_Addr and Data_Mask) = Data_Addr else '0';

   --Proceso de escritura del registro DDR
   process (SysClk) begin
      if rising_edge(SysClk) then
         if Reset = '1' then
            DDR <= (others => '0');
         elsif DDR_Sel = '1' and IO_WR = '1' then
            DDR <= IO_Dout;
         end if;
      end if;
   end process;

   --Proceso de escritura en el registro de datos de salida
   process (SysClk) begin
      if rising_edge(SysClk) then
         if Reset = '0' and Data_Sel = '1' and IO_WR = '1' then
            DataOutReg <= IO_Dout;
         end if;
      end if;
   end process;

   --Control del puerto externo
   External_Port:
   for i in 0 to nDataBits-1 generate
      DataPort(i) <= DataOutReg(i) when DDR(i) = '1' else 'Z';
   end generate;

   --Lectura de los registros
   process (Reset, DDR_Sel, Data_Sel, IO_RD, DDR, DataPort) begin
      if Reset = '0' and DDR_Sel = '1' and IO_RD = '1' then
         IO_Din <= DDR;
      elsif Reset = '0' and Data_Sel = '1' and IO_RD = '1' then
         IO_Din <= DataPort;
      else
         IO_Din <= (others => '0');
      end if;
   end process;
end Funcionamiento;