DAC Delta Sigma

Banca_Prueba.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
  
ENTITY Banca_Prueba IS
END Banca_Prueba;
 
ARCHITECTURE behavior OF Banca_Prueba IS 
    COMPONENT Principal
    PORT(
         clk : IN  std_logic;
         EntPCM : IN  std_logic_vector(7 downto 0);
         SalDAC : OUT  std_logic;
         SalFeedBack : OUT STD_LOGIC_VECTOR (7 downto 0);
         SalDelta : OUT  std_logic_vector(8 downto 0);
         SalSigma : OUT  std_logic_vector(8 downto 0)
        );
    END COMPONENT;    

   --Inputs
   signal clk : std_logic := '1';
   signal EntPCM : std_logic_vector(7 downto 0) := X"00";

 	--Outputs
   signal SalDAC : std_logic;
   signal SalFeedBack : std_logic_vector(7 downto 0);
   signal SalDelta : std_logic_vector(8 downto 0);
   signal SalSigma : std_logic_vector(8 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Principal PORT MAP (
          clk => clk,
          EntPCM => EntPCM,
          SalDAC => SalDAC,
          SalFeedBack => SalFeedBack,
          SalDelta => SalDelta,
          SalSigma => SalSigma
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '1';
		wait for clk_period/2;
		clk <= '0';
		wait for clk_period/2;
   end process;
 
   prueba: process
   begin
      while EntPCM < 255 loop
         EntPCM <= EntPCM + 1;
         wait until rising_edge(clk);
         wait until rising_edge(clk);
         wait until rising_edge(clk);
         wait until rising_edge(clk);
      end loop;
      while EntPCM > 0 loop
         EntPCM <= EntPCM - 1;
         wait until rising_edge(clk);
         wait until rising_edge(clk);
         wait until rising_edge(clk);
         wait until rising_edge(clk);
      end loop;
   end process;

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

Delta_Sigma.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Principal is
   generic (n_bits: integer := 8);
   port (clk:      in  STD_LOGIC;
         EntPCM:   in  STD_LOGIC_VECTOR (n_bits-1 downto 0);
         SalDAC:   out STD_LOGIC;
         --Puertos de prueba (pueden ser eliminados)
         SalFeedBack: out STD_LOGIC_VECTOR (n_bits-1 downto 0);
         SalDelta: out STD_LOGIC_VECTOR (n_bits downto 0);
         SalSigma: out STD_LOGIC_VECTOR (n_bits downto 0));
end Principal;

architecture Funcionamiento of Principal is
   --Señal de realimentacion que viene de la salida del DAC (resolucion de n_bits)
   signal feedback: STD_LOGIC_VECTOR (n_bits-1 downto 0);

   --Señal de diferencia/error/derivacion (resolucion de n_bits + 1)
   signal delta: STD_LOGIC_VECTOR (n_bits downto 0);

   --Señal de integracion (resolucion de n_bits + 1)
   signal sigma: STD_LOGIC_VECTOR (n_bits downto 0) := (others => '0');
begin
   --Puertos de prueba (pueden ser eliminados)
   SalFeedBack <= feedback;
   SalDelta <= delta;
   SalSigma <= sigma;

   --La señal de realimentacion es 0xFF cuando la salida (MSB de la señal de integracion) es alta,
   --y 0x00 cuando es baja
   feedback <= (others => '1') when sigma(n_bits) = '1' else
               (others => '0');

   --La señal de diferencia/error se obtiene a partir de la entrada y la realimentacion (notese
   --que la diferencia se calcula en 9 bits para incluir el acarreo)
   delta <= ('0' & EntPCM) - ('0' & feedback);

   --La señal de integracion se calcula sumando discretamente el valor acumulado con la diferencia
   --en cada periodo de la señal de reloj
   sigma <= sigma + delta when rising_edge(clk) else sigma;

   --La salida del DAC es lo mismo que el bit mas significativo de la señal de integracion
   SalDAC <= sigma(n_bits);
end Funcionamiento;