X86InitialState.swift

import Hypervisor

class X86InitialState {
  let registers: Dictionary<hv_x86_reg_t, UInt64> = [
    HV_X86_RIP: 0xfff0,
    HV_X86_RFLAGS: 0x2,
    HV_X86_RAX: 0,
    HV_X86_RCX: 0,
    HV_X86_RDX: 0xf00,
    HV_X86_RBX: 0,
    HV_X86_RSI: 0,
    HV_X86_RDI: 0,
    HV_X86_RSP: 0,
    HV_X86_RBP: 0,
    HV_X86_R8: 0,
    HV_X86_R9: 0,
    HV_X86_R10: 0,
    HV_X86_R11: 0,
    HV_X86_R12: 0,
    HV_X86_R13: 0,
    HV_X86_R14: 0,
    HV_X86_R15: 0,
    HV_X86_CS: 0xf000,
    HV_X86_SS: 0,
    HV_X86_DS: 0,
    HV_X86_ES: 0,
    HV_X86_FS: 0,
    HV_X86_GS: 0,
    HV_X86_IDT_BASE: 0,
    HV_X86_IDT_LIMIT: 0xffff,
    HV_X86_GDT_BASE: 0,
    HV_X86_GDT_LIMIT: 0xffff,
    HV_X86_LDTR: 0,
    HV_X86_LDT_BASE: 0,
    HV_X86_LDT_LIMIT: 0xffff,
    HV_X86_LDT_AR: 0x82,
    HV_X86_TR: 0,
    HV_X86_TSS_BASE: 0,
    HV_X86_TSS_LIMIT: 0xffff,
    HV_X86_TSS_AR: 0x83,

    HV_X86_CR0: 0x60000010,
    HV_X86_CR1: 0,
    HV_X86_CR2: 0,
    HV_X86_CR3: 0,
    HV_X86_CR4: 0,

    HV_X86_DR0: 0,
    HV_X86_DR1: 0,
    HV_X86_DR2: 0,
    HV_X86_DR3: 0,
    HV_X86_DR6: 0xffff0ff0,
    HV_X86_DR7: 0x400,

    HV_X86_TPR: 0,
    HV_X86_XCR0: 0,
  ]
  
  let vmcs: Dictionary<Int, UInt64> = [
    VMCS_CTRL_EXC_BITMAP: 0xffffffff,

    VMCS_CTRL_CR0_MASK: 0,
    VMCS_CTRL_CR0_SHADOW: 0,
    VMCS_CTRL_CR4_MASK: 0,
    VMCS_CTRL_CR4_SHADOW: 0,

    VMCS_GUEST_CS: 0xf000,
    VMCS_GUEST_CS_LIMIT: 0xffff,
    VMCS_GUEST_CS_AR: 0x9b,
    VMCS_GUEST_CS_BASE: 0xffff0000,

    VMCS_GUEST_DS: 0,
    VMCS_GUEST_DS_LIMIT: 0xffff,
    VMCS_GUEST_DS_AR: 0x83,
    VMCS_GUEST_DS_BASE: 0,

    VMCS_GUEST_ES: 0,
    VMCS_GUEST_ES_LIMIT: 0xffff,
    VMCS_GUEST_ES_AR: 0x83,
    VMCS_GUEST_ES_BASE: 0,

    VMCS_GUEST_FS: 0,
    VMCS_GUEST_FS_LIMIT: 0xffff,
    VMCS_GUEST_FS_AR: 0x83,
    VMCS_GUEST_FS_BASE: 0,

    VMCS_GUEST_GS: 0,
    VMCS_GUEST_GS_LIMIT: 0xffff,
    VMCS_GUEST_GS_AR: 0x93,
    VMCS_GUEST_GS_BASE: 0,

    VMCS_GUEST_SS: 0,
    VMCS_GUEST_SS_LIMIT: 0xffff,
    VMCS_GUEST_SS_AR: 0x83,
    VMCS_GUEST_SS_BASE: 0,

    VMCS_GUEST_LDTR: 0,
    VMCS_GUEST_LDTR_LIMIT: 0xffff,
    VMCS_GUEST_LDTR_AR: 0x10000,
    VMCS_GUEST_LDTR_BASE: 0,

    VMCS_GUEST_TR: 0,
    VMCS_GUEST_TR_LIMIT: 0,
    VMCS_GUEST_TR_AR: 0x83,
    VMCS_GUEST_TR_BASE: 0,

    VMCS_GUEST_GDTR_LIMIT: 0xffff,
    VMCS_GUEST_GDTR_BASE: 0,

    VMCS_GUEST_IDTR_LIMIT: 0xffff,
    VMCS_GUEST_IDTR_BASE: 0,

    VMCS_GUEST_CR0: 0x60000010,
    VMCS_GUEST_CR3: 0,
    VMCS_GUEST_CR4: 0,
  ]
}