VHDL function that returns even or odd bits from a vector

test_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use std.env.finish;
use std.textio.all;

entity test_tb is
end test_tb; 

architecture sim of test_tb is

  signal a: std_logic_vector(31 downto 0);
  signal b: std_logic_vector(15 downto 0);
  signal c: std_logic_vector(15 downto 0);

  -- Return the even bits when even_not_odd = true
  function even_or_odd(
    vec : std_logic_vector;
    even_not_odd : boolean)
    return std_logic_vector is
    variable ret : std_logic_vector(vec'length / 2  - 1 downto 0);
    variable mod_value : integer := 0;
  begin

    mod_value := 1 when even_not_odd;

    for i in vec'range loop
      if i mod 2 = mod_value then
        ret(i / 2) := vec(i);
      end if;
    end loop;

    return ret;
  end function;

begin

-- Testbench process
process
  variable l : line;
begin

  a <= "01010101010101010101010101010101";
  --a <= "11110000111100001111000011110000";
  wait for 10 ns;

  b <= even_or_odd(a, true);
  c <= even_or_odd(a, false);
  wait for 10 ns;

  swrite(l, "a: ");
  bwrite(l, a);
  writeline(output, l);

  swrite(l, "b: ");
  bwrite(l, b);
  writeline(output, l);

  swrite(l, "c: ");
  bwrite(l, c);
  writeline(output, l);

  finish;

end process;

end architecture;