stm32h7 itm

gistfile1.patch

 Cargo.lock     |  1 -
 Cargo.toml     |  5 +++--
 openocd.gdb    | 26 ++++++++++++++++++++------
 src/main.rs    | 15 ++++++++++-----
 stabilizer.cfg |  5 +++--
 5 files changed, 36 insertions(+), 16 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 6133b9e..cc91d7c 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -60,7 +60,6 @@ version = "0.4.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 dependencies = [
  "cortex-m 0.5.8 (registry+https://github.com/rust-lang/crates.io-index)",
- "cortex-m-semihosting 0.3.2 (registry+https://github.com/rust-lang/crates.io-index)",
  "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)",
 ]

diff --git a/Cargo.toml b/Cargo.toml
index 1e12749..6e5da97 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -29,7 +29,7 @@ default-target = "thumbv7em-none-eabihf"
 [dependencies]
 cortex-m = { version = "0.5", features = ["inline-asm", "const-fn"] }
 cortex-m-rt = { version = "0.6", features = ["device"] }
-cortex-m-log = { version = "0.4", features = ["log-integration"] }
+cortex-m-log = { version = "0.4", features = ["log-integration", "itm" ] }
 stm32h7 = { version = "0.6", features = ["stm32h7x3", "rt"] }
 # stm32h7 = { path = "../stm32-rs/stm32h7", features = ["stm32h7x3", "rt"] }
 log = "0.4"
@@ -38,7 +38,8 @@ panic-semihosting = { version = "0.5", optional = true }
 smoltcp = { version = "0.5", default-features = false, features = ["proto-ipv4", "socket-tcp", "log"] }

 [features]
-semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
+semihosting = ["panic-semihosting"]
+itm = [ ]
 bkpt = [ ]

 [build-dependencies]
diff --git a/openocd.gdb b/openocd.gdb
index a8602e2..25043fe 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -4,10 +4,10 @@ set print asm-demangle on
 set backtrace limit 32
 monitor arm semihosting enable
 # if using ITM with itmdump
-# monitor tpiu config internal itm.fifo uart off 168000000
+monitor tpiu config internal itm.fifo uart off 400000000
 # or uart
 # monitor tpiu config external uart off 168000000 2000000
-# monitor itm port 0 on
+monitor itm port 0 on

 # detect unhandled exceptions, hard faults and panics
 break DefaultHandler
@@ -16,14 +16,28 @@ break rust_begin_unwind

 load
 # tbreak cortex_m_rt::reset_handler
-# monitor reset halt
+monitor reset halt
+
+# D1DBG/D3DBG/TRACE CLKEN
+set *0x5C001004 = 0x00700000
+# SWO_LAR
+set *0x5C004FB0 = 0xC5ACCE55
+# SWTF_LAR
+set *0x5C003FB0 = 0xC5ACCE55
+# 400 MHz -> 2 MHz
+set *0x5C003010 = 0x000000c7
+# NRZ
+set *0x5C0030F0 = 0x00000002
+# enable SWO
+set *0x5C004000 = (*0x5C004000) | 0x1

 # cycle counter delta tool, place two bkpts around the section
-set var $cc=0xe0001004
+set $cc=0xe0001004
 define qq
 print *$cc-$t0
-set var $t0=*$cc
+set $t0=*$cc
 continue
 end
-set var $t0=*$cc
+
+set $t0=*$cc
 continue
diff --git a/src/main.rs b/src/main.rs
index 91ff3be..cd74057 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -21,17 +21,19 @@ use cortex_m::interrupt::Mutex;
 mod iir;
 use iir::*;

-#[cfg(not(feature = "semihosting"))]
+#[cfg(not(feature = "itm"))]
 fn init_log() {}

-#[cfg(feature = "semihosting")]
+#[cfg(feature = "itm")]
 fn init_log() {
     use log::LevelFilter;
     use cortex_m_log::log::{Logger, init};
-    use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout};
-    static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
+    use cortex_m_log::printer::itm::InterruptSync;
+    use cortex_m_log::destination::Itm;
+    let itm = unsafe { CorePeripherals::steal().ITM };
+    static mut LOGGER: Option<Logger<InterruptSync>> = None;
     let logger = Logger {
-        inner: InterruptOk::<_>::stdout().unwrap(),
+        inner: InterruptSync::new(Itm::new(itm)),
         level: LevelFilter::Info,
     };
     let logger = unsafe {
@@ -115,6 +117,7 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
          .pll1rge().bits(0b11)  // 8-16 MHz PFD
          .pll1fracen().clear_bit()
          .divp1en().set_bit()
+         .divr1en().set_bit()  // TPIU
          .pll2vcosel().set_bit()  // 150-420 MHz VCO
          .pll2rge().bits(0b11)  // 8-16 MHz PFD
          .pll2fracen().clear_bit()
@@ -124,6 +127,7 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
     rcc.pll1divr.write(|w| unsafe {
         w.divn1().bits(100 - 1)  // feebdack divider
          .divp1().bits(2 - 1)  // p output divider
+         .divr1().bits(2 - 1)  // r output divider
     });
     rcc.cr.modify(|_, w| w.pll1on().set_bit());
     while rcc.cr.read().pll1rdy().bit_is_clear() {}
@@ -530,6 +534,7 @@ fn main() -> ! {
     cp.SCB.enable_icache();
     cp.SCB.enable_dcache(&mut cp.CPUID);
     cp.DWT.enable_cycle_counter();
+    cp.DCB.enable_trace();

     rcc.ahb4enr.modify(|_, w|
         w.gpioaen().set_bit()
diff --git a/stabilizer.cfg b/stabilizer.cfg
index 51d7c6c..b896faf 100644
--- a/stabilizer.cfg
+++ b/stabilizer.cfg
@@ -2,5 +2,6 @@ source [find interface/stlink.cfg]
 transport select hla_swd
 source [find target/stm32h7x_dual_bank.cfg]

-# reset_config srst_only
-reset_config none
+reset_config srst_only
+# connect_assert_srst
+# reset_config none