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josyb / 1-StateMachines_and_Resets.md
Last active Sep 1, 2020
State Machines and Resets
View 1-StateMachines_and_Resets.md

One-Process, Two-Process and Three-Process State Machines

"a state machine is worth a thousand equations" - Josy Boelen (yes ...)

and their Resets

About State Machines

On the internet for a dealing with FPGA programming, I often read the advice to write One-Process state machines only.
And I usually beg to differ. (You shouldn't be surprised ...)
The principal arguments given are that a One-Process state machine description is 'free from latches' and at the same time requires less typing. Now being lazy is a hallmark of a good engineer, but ...
In a lot of cases a One-Process description fits exactly. However in my line of work this is rarely so.
To understand the deeper differences between the One- and Two-Process description we have to go back to Moore and Mealy.

@josyb
josyb / 1 - toplevelinterfaces.py
Last active Aug 24, 2018
Conversion of nested top-level interfaces
View 1 - toplevelinterfaces.py
'''
Created on 23 aug. 2018
@author: josy
'''
from __future__ import print_function
from myhdl import Signal, intbv, block, always_comb, always_seq, ResetSignal
@josyb
josyb / ringcounter.py
Created Aug 13, 2018
A simple ringcounter
View ringcounter.py
class RingCounter():
''' a simple 'Overbeck' ring counter.
See https://en.wikipedia.org/wiki/Ring_counter
It has zero overhead cost as no logic is needed to start.
The following picture is worth a thousand words?
A B C D
---- | ---- | ---- | ---- |
-| 0 | |--| 1 |-----| 2 |-----| 3 |-----
| | | o- | | | | | |o-
| ---- ---- ---- ---- |
@josyb
josyb / 1-structuraldesigninmyhdl.md
Last active Mar 14, 2018
Structural Design in MyHDL - to @block or not to @block?
View 1-structuraldesigninmyhdl.md

Following a discussion on Gitter[https://gitter.im/myhdl/myhdl] (November 24th, 14:40 about) I decided to make a small example to test it all. I have two versions of the MyHDL source:

  • structuraldesign_block.py: using the @block
  • structuraldesign_noblock.py: as in 0.9 using the old toVHDL() function call

You can see the two resulting VHDL files.

The one generated with the @block is a mess as it duplicates a lot of names. Of course the one generated by my local no-block MyHDL packages is ... well ... beautiful

@josyb
josyb / oo.md
Last active Oct 9, 2018
Object Oriented Design in MyHDL
View oo.md

There is a web-page where Adam Taylor lists 10 alternative FPGA development languages: http://www.eetimes.com/document.asp?doc_id=1329857 On some languages the OO-word was used ... I commented that the only thing I have seen so far from these languages is that they are (truly) class based but that I haven't seen any real example. Yet, as I did not study them to their deepest extent, having not enough time and too much other work ...

I already use class-based design for my MyHDL work, see my gist https://gist.github.com/josyb/afd84c9a06fdec77f2fd, but this is not OO as none of these classes have been subclassed.

In stead of doing some real work today (Sat Oct 22nd 2016), I decided to give OO in MyHDL a try. You can see the results in the two next files.

@josyb
josyb / zigzag.py
Last active Jul 2, 2016
Doing zigzag 'My Way' ...
View zigzag.py
'''
Created on 2 Jul 2016
@author: Josy
a question by Merkourios Katsimpris on gitter:myhdl triggered me to look at
http://paddy3118.blogspot.nl/2008/08/zig-zag.html
while the solution presented there is (very probably) very pythonic
you need to read the explanation to understand what or why it is doing
@josyb
josyb / dynconn.py
Last active Oct 9, 2018
Exploring improved structural design - Part 1
View dynconn.py
'''
Created on 29 Dec 2015
@author: Josy
'''
from __future__ import print_function
import random
import myhdl
@josyb
josyb / another_test.py
Last active Sep 19, 2015
another small test to demonstrate the 'delta' issue
View another_test.py
def delta(Clk, Reset, D, Wr, Sel, Q):
r = [Signal( intbv(0)[len(D):]) for _ in range(9)]
@always_seq(Clk.posedge, reset = Reset)
def rtl():
if Wr:
r[0].next = D
r[1].next = r[0]
r[2].next = r[1]
r[3].next = r[2]
View test_array_part2.py
def array_2(clk, reset, D, Q):
''' testing a 2-dimensional Array
just making a simple pipeline
'''
mt = myhdl.Array( (4, 3,), myhdl.Signal( myhdl.intbv(0)[len(D):]))
@myhdl.always_comb
def rtlcomb():
Q.next = mt[3][2]
@josyb
josyb / test_array_part_3.py
Last active Sep 14, 2015
Issue with having to ad a 'delta'after clk,posedge
View test_array_part_3.py
def array_3(clk, reset, Sel1, Sel2, Q):
''' testing a 2-dimensional Constant Array
'''
aoc = myhdl.Array( [[1,2,3], [4,5,6], [7,8,9]], myhdl.intbv(0)[len(Q):])
@myhdl.always_seq( clk.posedge, reset = reset)
def rtlreg():
Q.next = aoc[Sel2][Sel1]
return rtlreg