OSAL RTEMS timer test log

rtems-timer-test-ic-20191030.log

*** RTEMS Info ***
COPYRIGHT (c) 1989-2008.
On-Line Applications Research Corporation (OAR).
rtems-4.11.1.99(Intel i386/i386 with i387/pc686)

 Stack size=8
 Workspace size=1048576
 Bootloader Command Line: build/exe/cpu1/timer-test.exe 

*** End RTEMS info ***

Creating mount point directory: /ram0
Creating mount point directory: /ram1



RTEMS Shell on /dev/console. Use 'help' to list commands.
[/] # 
[BEGIN] PC-RTEMS UNIT TEST
OS_ConsoleCreate_Impl(): Starting Async Console Handler

[BEGIN] 01 TimerTest
[ PASS] 01.001 timer-test.c:74 - Timer Test Task Created RC=0
[ PASS] 01.002 timer-test.c:105 - Timer 0 Created RC=0 ID=589825
[ INFO] timer-test.c:107:Timer 0 Accuracy = 10000 microseconds 

[ PASS] 01.003 timer-test.c:105 - Timer 1 Created RC=0 ID=589826
[ INFO] timer-test.c:107:Timer 1 Accuracy = 10000 microseconds 

[ PASS] 01.004 timer-test.c:105 - Timer 2 Created RC=0 ID=589827
[ INFO] timer-test.c:107:Timer 2 Accuracy = 10000 microseconds 

[ PASS] 01.005 timer-test.c:105 - Timer 3 Created RC=0 ID=589828
[ INFO] timer-test.c:107:Timer 3 Accuracy = 10000 microseconds 

WARNING: timer 1 start_time requested=1000us, configured=10000us
[ PASS] 01.006 timer-test.c:129 - Timer 0 programmed RC=0
[ PASS] 01.007 timer-test.c:129 - Timer 1 programmed RC=0
[ PASS] 01.008 timer-test.c:129 - Timer 2 programmed RC=0
[ PASS] 01.009 timer-test.c:129 - Timer 3 programmed RC=0
[ INFO] timer-test.c:135:Starting Delay loop.

[ PASS] 01.010 timer-test.c:156 - Timer 0 delete RC=0. Count total = 61
[ PASS] 01.011 timer-test.c:156 - Timer 1 delete RC=0. Count total = 71
[ PASS] 01.012 timer-test.c:156 - Timer 2 delete RC=0. Count total = 34
[ PASS] 01.013 timer-test.c:156 - Timer 3 delete RC=0. Count total = 44
[ PASS] 01.014 timer-test.c:190 - Expected ticks = 61
[ PASS] 01.015 timer-test.c:196 - Timer 0 count >= 58
[ PASS] 01.016 timer-test.c:197 - Timer 0 count <= 64
[ PASS] 01.017 timer-test.c:190 - Expected ticks = 71
[ PASS] 01.018 timer-test.c:196 - Timer 1 count >= 68
[ PASS] 01.019 timer-test.c:197 - Timer 1 count <= 74
[ PASS] 01.020 timer-test.c:190 - Expected ticks = 34
[ PASS] 01.021 timer-test.c:196 - Timer 2 count >= 31
[ PASS] 01.022 timer-test.c:197 - Timer 2 count <= 37
[ PASS] 01.023 timer-test.c:190 - Expected ticks = 44
[ PASS] 01.024 timer-test.c:196 - Timer 3 count >= 41
[ PASS] 01.025 timer-test.c:197 - Timer 3 count <= 47
[  END] 01 TimerTest            TOTAL::25    PASS::25    FAIL::0      MIR::0      TSF::0      N/A::0   

COMPLETE: 1 test segment(s) executed
RESULT: SUCCESS