Created
November 12, 2022 03:42
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Icestudio example of using Lattice ICE40 internal oscillator as a reference clock working on UPduino v3.1
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{ | |
"version": "1.2", | |
"package": { | |
"name": "", | |
"version": "", | |
"description": "", | |
"author": "", | |
"image": "" | |
}, | |
"design": { | |
"board": "upduino31", | |
"graph": { | |
"blocks": [ | |
{ | |
"id": "bba5bacd-2bbe-48a6-afda-3639d94f801a", | |
"type": "basic.output", | |
"data": { | |
"name": "LED", | |
"pins": [ | |
{ | |
"index": "0", | |
"name": "led_blue", | |
"value": "40" | |
} | |
], | |
"virtual": false | |
}, | |
"position": { | |
"x": 360, | |
"y": -64 | |
} | |
}, | |
{ | |
"id": "5701b50c-904b-4776-ab4c-addc641b71ff", | |
"type": "basic.output", | |
"data": { | |
"name": "LED", | |
"pins": [ | |
{ | |
"index": "0", | |
"name": "led_red", | |
"value": "41" | |
} | |
], | |
"virtual": false | |
}, | |
"position": { | |
"x": 360, | |
"y": 16 | |
} | |
}, | |
{ | |
"id": "279c2e74-69b0-489f-af8a-1a3b26a8d20e", | |
"type": "32200dc0915d45d6ec035bcec61c8472f0cc7b88", | |
"position": { | |
"x": 208, | |
"y": 16 | |
}, | |
"size": { | |
"width": 96, | |
"height": 64 | |
} | |
}, | |
{ | |
"id": "c4334cde-6d7f-4932-bd44-7978a59c0b75", | |
"type": "basic.info", | |
"data": { | |
"info": "LEDs blue and red are blinking alternatively", | |
"readonly": false | |
}, | |
"position": { | |
"x": -176, | |
"y": -120 | |
}, | |
"size": { | |
"width": 416, | |
"height": 32 | |
} | |
}, | |
{ | |
"id": "9f445916-9f64-46fe-921d-06ef2a3a4fff", | |
"type": "basic.code", | |
"data": { | |
"ports": { | |
"in": [], | |
"out": [ | |
{ | |
"name": "clk" | |
} | |
] | |
}, | |
"params": [], | |
"code": "wire clk_pre;\nSB_HFOSC inthosc(.CLKHFPU(1'b1), .CLKHFEN(1'b1), .CLKHF(clk_pre));\n\nparameter N = 27;\n\n//-- divisor register\nreg [N-1:0] divcounter;\n\n//-- N bit counter\nalways @(posedge clk_pre)\n divcounter <= divcounter + 1;\n\n//-- Use the most significant bit as output\nassign clk = divcounter[N-1];" | |
}, | |
"position": { | |
"x": -416, | |
"y": -384 | |
}, | |
"size": { | |
"width": 760, | |
"height": 216 | |
} | |
} | |
], | |
"wires": [ | |
{ | |
"source": { | |
"block": "279c2e74-69b0-489f-af8a-1a3b26a8d20e", | |
"port": "664caf9e-5f40-4df4-800a-b626af702e62" | |
}, | |
"target": { | |
"block": "5701b50c-904b-4776-ab4c-addc641b71ff", | |
"port": "in" | |
} | |
}, | |
{ | |
"source": { | |
"block": "9f445916-9f64-46fe-921d-06ef2a3a4fff", | |
"port": "clk" | |
}, | |
"target": { | |
"block": "bba5bacd-2bbe-48a6-afda-3639d94f801a", | |
"port": "in" | |
} | |
}, | |
{ | |
"source": { | |
"block": "9f445916-9f64-46fe-921d-06ef2a3a4fff", | |
"port": "clk" | |
}, | |
"target": { | |
"block": "279c2e74-69b0-489f-af8a-1a3b26a8d20e", | |
"port": "18c2ebc7-5152-439c-9b3f-851c59bac834" | |
} | |
} | |
] | |
} | |
}, | |
"dependencies": { | |
"32200dc0915d45d6ec035bcec61c8472f0cc7b88": { | |
"package": { | |
"name": "NOT", | |
"version": "1.0.0", | |
"description": "NOT logic gate", | |
"author": "Jesús Arroyo", | |
"image": "%3Csvg%20xmlns=%22http://www.w3.org/2000/svg%22%20width=%2291.33%22%20height=%2245.752%22%20version=%221%22%3E%3Cpath%20d=%22M0%2020.446h27v2H0zM70.322%2020.447h15.3v2h-15.3z%22/%3E%3Cpath%20d=%22M66.05%2026.746c-2.9%200-5.3-2.4-5.3-5.3s2.4-5.3%205.3-5.3%205.3%202.4%205.3%205.3-2.4%205.3-5.3%205.3zm0-8.6c-1.8%200-3.3%201.5-3.3%203.3%200%201.8%201.5%203.3%203.3%203.3%201.8%200%203.3-1.5%203.3-3.3%200-1.8-1.5-3.3-3.3-3.3z%22/%3E%3Cpath%20d=%22M25.962%202.563l33.624%2018.883L25.962%2040.33V2.563z%22%20fill=%22none%22%20stroke=%22#000%22%20stroke-width=%223%22/%3E%3C/svg%3E" | |
}, | |
"design": { | |
"graph": { | |
"blocks": [ | |
{ | |
"id": "5365ed8c-e5db-4445-938f-8d689830ea5c", | |
"type": "basic.code", | |
"data": { | |
"code": "// NOT logic gate\n\nassign c = ~ a;", | |
"params": [], | |
"ports": { | |
"in": [ | |
{ | |
"name": "a" | |
} | |
], | |
"out": [ | |
{ | |
"name": "c" | |
} | |
] | |
} | |
}, | |
"position": { | |
"x": 256, | |
"y": 48 | |
} | |
}, | |
{ | |
"id": "18c2ebc7-5152-439c-9b3f-851c59bac834", | |
"type": "basic.input", | |
"data": { | |
"name": "" | |
}, | |
"position": { | |
"x": 64, | |
"y": 144 | |
} | |
}, | |
{ | |
"id": "664caf9e-5f40-4df4-800a-b626af702e62", | |
"type": "basic.output", | |
"data": { | |
"name": "" | |
}, | |
"position": { | |
"x": 752, | |
"y": 144 | |
} | |
} | |
], | |
"wires": [ | |
{ | |
"source": { | |
"block": "18c2ebc7-5152-439c-9b3f-851c59bac834", | |
"port": "out" | |
}, | |
"target": { | |
"block": "5365ed8c-e5db-4445-938f-8d689830ea5c", | |
"port": "a" | |
} | |
}, | |
{ | |
"source": { | |
"block": "5365ed8c-e5db-4445-938f-8d689830ea5c", | |
"port": "c" | |
}, | |
"target": { | |
"block": "664caf9e-5f40-4df4-800a-b626af702e62", | |
"port": "in" | |
} | |
} | |
] | |
} | |
} | |
} | |
} | |
} |
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See FPGAwars/icestudio#408 (comment) for context