minimal example solution to the initialization problem

test_gen_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

library work;
package wb_init is
    
    constant NbitW : natural := 18;
    
    type ramd_type0 is array (1 downto 0) of std_logic_vector(NbitW-1 downto 0);
    type ramd_type1 is array (2  downto 0) of std_logic_vector(NbitW-1 downto 0);

    type layer_ram0 is array (3 downto 0) of ramd_type0;
    type layer_ram1 is array (4 downto 0) of ramd_type1;
  
    constant w0 : layer_ram0 := (others => (others =>(others =>'0')));
    constant w1 : layer_ram1 := (others => (others =>(others =>'0')));

end wb_init ;

--- test_gen:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

library work;
use work.wb_init.all;
   
entity test_gen is

   generic
   (
      LNum    : natural ;  
      NumN    : natural ; 
      NumIn   : natural    
   );

   port
   (
      inputs  : in std_logic_vector(17 downto 0);
      outputs : out std_logic_vector(17 downto 0) 
   );

end test_gen;

architecture beh of test_gen is


  type ramd_type is array (NumN-1 downto 0) of std_logic_vector(17 downto 0); 
  type layer_ram is array (NumIn-1 downto 0) of ramd_type;
    

  function w_init(LNum : natural) return layer_ram is
    variable tmp_arr : layer_ram ;
  begin
    if LNum = 0 then
      for i in 0 to NumIn-1 loop
        for j in 0 to NumN-1 loop
           tmp_arr(i)(j) := w0(i)(j);
        end loop;
     end loop;
    elsif LNum = 1 then
      for i in 0 to NumIn-1 loop
        for j in 0 to NumN-1 loop
           tmp_arr(i)(j) := w1(i)(j);
        end loop;
      end loop;
    else
      for i in 0 to NumIn-1 loop
        for j in 0 to NumN-1 loop
           tmp_arr(i)(j) := (others => '0');
        end loop;
      end loop;
    end if;

    return tmp_arr ;
  end w_init;

  signal lram  : layer_ram := w_init(LNum); 

begin
  outputs<= inputs;
end beh;

--- test_gen_tb:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

--library work;
--use work.wb_init.all;
   
entity test_gen_tb is
end test_gen_tb;

architecture beh of test_gen_tb is

component test_gen is
  generic
  (
     LNum    : natural ; 
     NumN    : natural ;
     NumIn   : natural   
  );

  port
  (
     inputs  : in std_logic_vector(17 downto 0);
     outputs : out std_logic_vector(17 downto 0) 
  );

  end component;
  type gen_ar is array (1 downto 0) of natural;
  signal NumN_ar : gen_ar := (3,2);
  signal NumIn_ar : gen_ar := (5,4);
  signal inputs,outputs : std_logic_vector(17 downto 0);

begin

  test_gen_inst:
  for i in 0 to 1 generate
  tg:test_gen
  generic map (
    LNum  => i,
    NumN  => NumN_ar(i),
    NumIn => NumIn_ar(i)
  )
  port map (
    inputs  => inputs,
    outputs => outputs
  );  
  end generate;

end beh;