How to use Gowin's DCS (Dynamic Clock Select) and rPLL module instances and properly configure timing analysis

gowin_verilog_dcs_and_rpll.v

module top(
  input clk_27mhz, // The built-in 27 MHz oscillator clock. Using timing constraint: create_clock -name clk_27mhz -period 37.037 [get_ports {clk_27mhz}]
  input external_clk, // And external clock signal at 12.5 - 32 MHz frequency. Using timing constraint: create_clock -name external_clk -period 31.25 [get_ports {external_clk}]
  input which_clock_to_use,
  output reg o_a,
  output reg o_b,
  output o_clk
);

  always @(posedge clk_27mhz) begin
    o_a <= ~o_a;
  end

  always @(posedge external_clk) begin
    o_b <= ~o_b;
  end

  DCS dcs (
    .CLK0(clk_27mhz),
    .CLK1(external_clk),
    .CLK2(1'b0),
    .CLK3(1'b0),
    .CLKSEL(which_clock_to_use ? 4'b0001 : 4'b0010),
    .SELFORCE(1'b1),
    .CLKOUT(sel_clk)
  );

  rPLL #(
    // N.b. without proper timing constraints (see below), the following line will issue warnings
    // WARN  (CK3000) : The clock "DEFAULT_CLK"'s frequency does not match hdmi_pll's param "FCLKIN = "32""
    // WARN  (TA1118) : the clock "clk_27mhz"'s frequency does not match hdmi_pll's param "FCLKIN = "32""
    .FCLKIN("32"),
    .DYN_FBDIV_SEL("true"),
    .DYN_IDIV_SEL("true"),
    .DYN_ODIV_SEL("true")
  ) hdmi_pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0),
    .CLKIN(sel_clk),
    // N.b. without proper timing constraints, four copies of the following warning will be issued:
    // WARN  (TA1121) : hdmi_pll's "CLKIN" pin has more than one clock on it,use clock "clk_27mhz" as master clock of "hdmi_pll/CLKOUT" pin
    .CLKOUT(o_clk),
    .FBDSEL(which_clock_to_use ? 6'd59 : 6'd63),
    .IDSEL(6'd63),
    .ODSEL(6'h3f),
    .LOCK()
  );
endmodule

/* Specify the following timing constraints:

// Annotate two original input clocks
create_clock -name clk_27mhz -period 37.037 [get_ports {clk_27mhz}]
create_clock -name external_clk -period 31.25 [get_ports {external_clk}]
// Annotate DCS output/PLL input
create_clock -name pll_input -period 31.25 [get_nets {sel_clk}] 
// Annotate PLL output
create_clock -name pll_output -period 6.25 [get_ports {o_clk}]
*/