some SysRegs may be missing, but this should be the majority

everest-core-sysregs

S0_0_c4_c0_3 at min EL1: UAOIMM
S0_0_c4_c0_4 at min EL1: PANIMM
S0_0_c4_c0_5 at min EL1: SPSELIMM
S0_3_c4_c0_1 at min EL1: SSBSIMM
S0_3_c4_c0_2 at min EL1: DITIMM
S0_3_c4_c0_6 at min EL1: DAIFSET
S0_3_c4_c0_7 at min EL1: DAIFCLR
S1_0_c7_c10_2 at min EL1: DCCSW
S1_0_c7_c14_2 at min EL1: DCCISW
S1_0_c7_c1_0 at min EL1: ICIALLUIS
S1_0_c7_c5_0 at min EL1: ICIALLU
S1_0_c7_c6_1 at min EL1: DCIVAC
S1_0_c7_c6_2 at min EL1: DCISW
S1_0_c7_c8_0 at min EL1: ATS1E1R
S1_0_c7_c8_1 at min EL1: ATS1E1W
S1_0_c7_c8_2 at min EL1: ATS1E0R
S1_0_c7_c8_3 at min EL1: ATS1E0W
S1_0_c8_c3_0 at min EL1: TLBIVMALLE1IS
S1_0_c8_c3_1 at min EL1: TLBIVAE1IS
S1_0_c8_c3_2 at min EL1: TLBIASIDE1IS
S1_0_c8_c3_3 at min EL1: TLBIVAAE1IS
S1_0_c8_c3_5 at min EL1: TLBIVALE1IS
S1_0_c8_c3_7 at min EL1: TLBIVAALE1IS
S1_0_c8_c7_0 at min EL1: TLBIVMALLE1
S1_0_c8_c7_1 at min EL1: TLBIVAE1
S1_0_c8_c7_2 at min EL1: TLBIASIDE1
S1_0_c8_c7_3 at min EL1: TLBIVAAE1
S1_0_c8_c7_5 at min EL1: TLBIVALE1
S1_0_c8_c7_7 at min EL1: TLBIVAALE1
S1_3_c7_c10_1 at min EL1: DCCVAC
S1_3_c7_c11_1 at min EL1: DCCVAU
S1_3_c7_c14_1 at min EL1: DCCIVAC
S1_3_c7_c4_1 at min EL1: DCZVA
S1_3_c7_c5_1 at min EL1: ICIVAU
S1_4_c7_c8_0 at min EL1: ATS1E2R
S1_4_c7_c8_1 at min EL1: ATS1E2W
S1_4_c7_c8_4 at min EL1: ATS12E1R
S1_4_c7_c8_5 at min EL1: ATS12E1W
S1_4_c7_c8_6 at min EL1: ATS12E0R
S1_4_c7_c8_7 at min EL1: ATS12E0W
S1_4_c8_c0_1 at min EL1: TLBIIPAS2E1IS
S1_4_c8_c0_5 at min EL1: TLBIIPAS2LE1IS
S1_4_c8_c3_0 at min EL1: TLBIALLE2IS
S1_4_c8_c3_1 at min EL1: TLBIVAE2IS
S1_4_c8_c3_4 at min EL1: TLBIALLE1IS
S1_4_c8_c3_5 at min EL1: TLBIVALE2IS
S1_4_c8_c3_6 at min EL1: TLBIVMALLS12E1IS
S1_4_c8_c4_1 at min EL1: TLBIIPAS2E1
S1_4_c8_c4_5 at min EL1: TLBIIPAS2LE1
S1_4_c8_c7_0 at min EL1: TLBIALLE2
S1_4_c8_c7_1 at min EL1: TLBIVAE2
S1_4_c8_c7_4 at min EL1: TLBIALLE1
S1_4_c8_c7_5 at min EL1: TLBIVALE2
S1_4_c8_c7_6 at min EL1: TLBIVMALLS12E1
S1_6_c7_c8_0 at min EL1: ATS1E3R
S1_6_c7_c8_1 at min EL1: ATS1E3W
S1_6_c8_c3_0 at min EL1: TLBIALLE3IS
S1_6_c8_c3_1 at min EL1: TLBIVAE3IS
S1_6_c8_c3_5 at min EL1: TLBIVALE3IS
S1_6_c8_c7_0 at min EL1: TLBIALLE3
S1_6_c8_c7_1 at min EL1: TLBIVAE3
S1_6_c8_c7_5 at min EL1: TLBIVALE3
S2_0_c0_c0_2 at min EL1: OSDTRRX_EL1
S2_0_c0_c0_4 at min EL1: DBGBVR0_EL1
S2_0_c0_c0_5 at min EL1: DBGBCR0_EL1
S2_0_c0_c0_6 at min EL1: DBGWVR0_EL1
S2_0_c0_c0_7 at min EL1: DBGWCR0_EL1
S2_0_c0_c10_4 at min EL1: DBGBVR10_EL1
S2_0_c0_c10_5 at min EL1: DBGBCR10_EL1
S2_0_c0_c10_6 at min EL1: DBGWVR10_EL1
S2_0_c0_c10_7 at min EL1: DBGWCR10_EL1
S2_0_c0_c11_4 at min EL1: DBGBVR11_EL1
S2_0_c0_c11_5 at min EL1: DBGBCR11_EL1
S2_0_c0_c11_6 at min EL1: DBGWVR11_EL1
S2_0_c0_c11_7 at min EL1: DBGWCR11_EL1
S2_0_c0_c12_4 at min EL1: DBGBVR12_EL1
S2_0_c0_c12_5 at min EL1: DBGBCR12_EL1
S2_0_c0_c12_6 at min EL1: DBGWVR12_EL1
S2_0_c0_c12_7 at min EL1: DBGWCR12_EL1
S2_0_c0_c13_4 at min EL1: DBGBVR13_EL1
S2_0_c0_c13_5 at min EL1: DBGBCR13_EL1
S2_0_c0_c13_6 at min EL1: DBGWVR13_EL1
S2_0_c0_c13_7 at min EL1: DBGWCR13_EL1
S2_0_c0_c14_4 at min EL1: DBGBVR14_EL1
S2_0_c0_c14_5 at min EL1: DBGBCR14_EL1
S2_0_c0_c14_6 at min EL1: DBGWVR14_EL1
S2_0_c0_c14_7 at min EL1: DBGWCR14_EL1
S2_0_c0_c15_4 at min EL1: DBGBVR15_EL1
S2_0_c0_c15_5 at min EL1: DBGBCR15_EL1
S2_0_c0_c15_6 at min EL1: DBGWVR15_EL1
S2_0_c0_c15_7 at min EL1: DBGWCR15_EL1
S2_0_c0_c1_4 at min EL1: DBGBVR1_EL1
S2_0_c0_c1_5 at min EL1: DBGBCR1_EL1
S2_0_c0_c1_6 at min EL1: DBGWVR1_EL1
S2_0_c0_c1_7 at min EL1: DBGWCR1_EL1
S2_0_c0_c2_0 at min EL1: MDCCINT_EL1
S2_0_c0_c2_2 at min EL1: MDSCR_EL1
S2_0_c0_c2_4 at min EL1: DBGBVR2_EL1
S2_0_c0_c2_5 at min EL1: DBGBCR2_EL1
S2_0_c0_c2_6 at min EL1: DBGWVR2_EL1
S2_0_c0_c2_7 at min EL1: DBGWCR2_EL1
S2_0_c0_c3_2 at min EL1: OSDTRTX_EL1
S2_0_c0_c3_4 at min EL1: DBGBVR3_EL1
S2_0_c0_c3_5 at min EL1: DBGBCR3_EL1
S2_0_c0_c3_6 at min EL1: DBGWVR3_EL1
S2_0_c0_c3_7 at min EL1: DBGWCR3_EL1
S2_0_c0_c4_4 at min EL1: DBGBVR4_EL1
S2_0_c0_c4_5 at min EL1: DBGBCR4_EL1
S2_0_c0_c4_6 at min EL1: DBGWVR4_EL1
S2_0_c0_c4_7 at min EL1: DBGWCR4_EL1
S2_0_c0_c5_4 at min EL1: DBGBVR5_EL1
S2_0_c0_c5_5 at min EL1: DBGBCR5_EL1
S2_0_c0_c5_6 at min EL1: DBGWVR5_EL1
S2_0_c0_c5_7 at min EL1: DBGWCR5_EL1
S2_0_c0_c6_0 at min EL1: DBGWFAR
S2_0_c0_c6_2 at min EL1: OSECCR_EL1
S2_0_c0_c6_4 at min EL1: DBGBVR6_EL1
S2_0_c0_c6_5 at min EL1: DBGBCR6_EL1
S2_0_c0_c6_6 at min EL1: DBGWVR6_EL1
S2_0_c0_c6_7 at min EL1: DBGWCR6_EL1
S2_0_c0_c7_4 at min EL1: DBGBVR7_EL1
S2_0_c0_c7_5 at min EL1: DBGBCR7_EL1
S2_0_c0_c7_6 at min EL1: DBGWVR7_EL1
S2_0_c0_c7_7 at min EL1: DBGWCR7_EL1
S2_0_c0_c8_4 at min EL1: DBGBVR8_EL1
S2_0_c0_c8_5 at min EL1: DBGBCR8_EL1
S2_0_c0_c8_6 at min EL1: DBGWVR8_EL1
S2_0_c0_c8_7 at min EL1: DBGWCR8_EL1
S2_0_c0_c9_4 at min EL1: DBGBVR9_EL1
S2_0_c0_c9_5 at min EL1: DBGBCR9_EL1
S2_0_c0_c9_6 at min EL1: DBGWVR9_EL1
S2_0_c0_c9_7 at min EL1: DBGWCR9_EL1
S2_0_c1_c0_0 at min EL1: MDRAR_EL1
S2_0_c1_c0_4 at min EL1: OSLAR_EL1
S2_0_c1_c1_4 at min EL1: OSLSR_EL1
S2_0_c1_c3_4 at min EL1: OSDLR_EL1
S2_0_c1_c4_4 at min EL1: DBGPRCR_EL1
S2_0_c7_c14_6 at min EL1: AUTHSTAT_EL1
S2_0_c7_c14_6 at min EL1: DBGAUTHSTAT_EL1
S2_0_c7_c8_6 at min EL1: CLAIMSET_EL1
S2_0_c7_c8_6 at min EL1: DBGCLAIMSET_EL1
S2_0_c7_c9_6 at min EL1: CLAIMCLR_EL1
S2_0_c7_c9_6 at min EL1: DBGCLAIMCLR_EL1
S2_2_c0_c0_0 at min EL1: TEECR32_EL1
S2_2_c1_c0_0 at min EL1: TEEHBR32_EL1
S2_3_c0_c1_0 at min EL1: MDCCSR_EL0
S2_3_c0_c4_0 at min EL0: DBGDTR_EL0
S2_3_c0_c4_0 at min EL1: MDDTRR_EL0
S2_3_c0_c4_0 at min EL1: MDDTR_EL0
S2_3_c0_c5_0 at min EL0: DBGDTRRX_EL0
S2_3_c0_c5_0 at min EL0: DBGDTRTX_EL0
S2_3_c0_c5_0 at min EL1: MDDTRRX_EL0
S2_3_c0_c5_0 at min EL1: MDDTRTX_EL0
S2_4_c0_c7_0 at min EL2: DBGVCR32_EL2
S3_0_c0_c0_0 at min EL1: MIDR_EL1
S3_0_c0_c0_5 at min EL1: MPIDR_EL1
S3_0_c0_c0_6 at min EL1: REVIDR_EL1
S3_0_c0_c1_0 at min EL1: ID_PFR0_EL1
S3_0_c0_c1_1 at min EL1: ID_PFR1_EL1
S3_0_c0_c1_2 at min EL1: ID_DFR0_EL1
S3_0_c0_c1_3 at min EL1: ID_AFR0_EL1
S3_0_c0_c1_4 at min EL1: ID_MMFR0_EL1
S3_0_c0_c1_5 at min EL1: ID_MMFR1_EL1
S3_0_c0_c1_6 at min EL1: ID_MMFR2_EL1
S3_0_c0_c1_7 at min EL1: ID_MMFR3_EL1
S3_0_c0_c2_0 at min EL1: ID_ISAR0_EL1
S3_0_c0_c2_1 at min EL1: ID_ISAR1_EL1
S3_0_c0_c2_2 at min EL1: ID_ISAR2_EL1
S3_0_c0_c2_3 at min EL1: ID_ISAR3_EL1
S3_0_c0_c2_4 at min EL1: ID_ISAR4_EL1
S3_0_c0_c2_5 at min EL1: ID_ISAR5_EL1
S3_0_c0_c2_6 at min EL1: ID_MMFR4_EL1
S3_0_c0_c2_7 at min EL1: ID_ISAR6_EL1
S3_0_c0_c3_0 at min EL1: MVFR0_EL1
S3_0_c0_c3_1 at min EL1: MVFR1_EL1
S3_0_c0_c3_2 at min EL1: MVFR2_EL1
S3_0_c0_c3_3 at min EL1: ID_AA32RES3_EL1
S3_0_c0_c3_4 at min EL1: ID_PFR2_EL1
S3_0_c0_c3_5 at min EL1: ID_AA32RES5_EL1
S3_0_c0_c3_6 at min EL1: ID_AA32RES6_EL1
S3_0_c0_c3_7 at min EL1: ID_AA32RES7_EL1
S3_0_c0_c4_0 at min EL1: ID_AA64PFR0_EL1
S3_0_c0_c4_1 at min EL1: ID_AA64PFR1_EL1
S3_0_c0_c4_2 at min EL1: ID_AA64PFR2_EL1
S3_0_c0_c4_3 at min EL1: ID_AA64PFR3_EL1
S3_0_c0_c4_4 at min EL1: ID_AA64ZFR0_EL1
S3_0_c0_c4_5 at min EL1: ID_AA64ZFR1_EL1
S3_0_c0_c4_6 at min EL1: ID_AA64ZFR2_EL1
S3_0_c0_c4_7 at min EL1: ID_AA64ZFR3_EL1
S3_0_c0_c5_0 at min EL1: ID_AA64DFR0_EL1
S3_0_c0_c5_1 at min EL1: ID_AA64DFR1_EL1
S3_0_c0_c5_2 at min EL1: ID_AA64DFR2_EL1
S3_0_c0_c5_3 at min EL1: ID_AA64DFR3_EL1
S3_0_c0_c5_4 at min EL1: ID_AA64AFR0_EL1
S3_0_c0_c5_5 at min EL1: ID_AA64AFR1_EL1
S3_0_c0_c5_6 at min EL1: ID_AA64AFR2_EL1
S3_0_c0_c5_7 at min EL1: ID_AA64AFR3_EL1
S3_0_c0_c6_0 at min EL1: ID_AA64ISAR0_EL1
S3_0_c0_c6_1 at min EL1: ID_AA64ISAR1_EL1
S3_0_c0_c6_3 at min EL1: ID_AA64ISAR3_EL1
S3_0_c0_c6_4 at min EL1: ID_AA64ISAR4_EL1
S3_0_c0_c6_5 at min EL1: ID_AA64ISAR5_EL1
S3_0_c0_c6_6 at min EL1: ID_AA64ISAR6_EL1
S3_0_c0_c6_7 at min EL1: ID_AA64ISAR7_EL1
S3_0_c0_c7_0 at min EL1: ID_AA64MMFR0_EL1
S3_0_c0_c7_1 at min EL1: ID_AA64MMFR1_EL1
S3_0_c0_c7_2 at min EL1: ID_AA64MMFR2_EL1
S3_0_c0_c7_3 at min EL1: ID_AA64MMFR3_EL1
S3_0_c0_c7_4 at min EL1: ID_AA64MMFR4_EL1
S3_0_c0_c7_5 at min EL1: ID_AA64MMFR5_EL1
S3_0_c0_c7_6 at min EL1: ID_AA64MMFR6_EL1
S3_0_c0_c7_7 at min EL1: ID_AA64MMFR7_EL1
S3_0_c10_c2_0 at min EL1: MAIR_EL1
S3_0_c10_c2_0 at min EL1: MAIR_EL21
S3_0_c10_c3_0 at min EL1: AMAIR_EL1
S3_0_c10_c3_0 at min EL1: AMAIR_EL21
S3_0_c10_c4_0 at min EL1: LORSA_EL1
S3_0_c10_c4_1 at min EL1: LOREA_EL1
S3_0_c10_c4_2 at min EL1: LORN_EL1
S3_0_c10_c4_3 at min EL1: LORC_EL1
S3_0_c10_c4_7 at min EL1: LORID_EL1
S3_0_c12_c0_0 at min EL1: VBAR_EL1
S3_0_c12_c0_0 at min EL1: VBAR_EL21
S3_0_c12_c0_1 at min EL1: RVBAR_EL1
S3_0_c12_c0_2 at min EL1: RMR_EL1
S3_0_c12_c11_1 at min EL1: ICV_DIR_EL1
S3_0_c12_c11_3 at min EL1: ICV_RPR_EL1
S3_0_c12_c11_5 at min EL1: ICC_SGI1R_EL1
S3_0_c12_c11_6 at min EL1: ICC_ASGI1R_EL1
S3_0_c12_c11_7 at min EL1: ICC_SGI0R_EL1
S3_0_c12_c12_0 at min EL1: ICV_IAR1_EL1
S3_0_c12_c12_1 at min EL1: ICV_EOIR1_EL1
S3_0_c12_c12_2 at min EL1: ICV_HPPIR1_EL1
S3_0_c12_c12_3 at min EL1: ICV_BPR1CBPR_EL1
S3_0_c12_c12_3 at min EL1: ICV_BPR1_EL1
S3_0_c12_c12_4 at min EL1: ICV_CTLR_EL1
S3_0_c12_c12_5 at min EL1: ICC_SRE_EL1
S3_0_c12_c12_6 at min EL1: ICV_IGRPEN0_EL1
S3_0_c12_c12_7 at min EL1: ICV_IGRPEN1_EL1
S3_0_c12_c1_0 at min EL1: ISR_EL1
S3_0_c12_c1_1 at min EL1: DISR_EL1
S3_0_c12_c8_0 at min EL1: ICV_IAR0_EL1
S3_0_c12_c8_1 at min EL1: ICV_EOIR0_EL1
S3_0_c12_c8_2 at min EL1: ICV_HPPIR0_EL1
S3_0_c12_c8_3 at min EL1: ICV_BPR0_EL1
S3_0_c12_c8_4 at min EL1: ICC_AP0R0_EL1
S3_0_c12_c9_0 at min EL1: ICC_AP1R0_EL1
S3_0_c13_c0_1 at min EL1: CONTEXTIDR_EL1
S3_0_c13_c0_1 at min EL1: CONTEXTIDR_EL21
S3_0_c13_c0_4 at min EL1: TPIDR_EL1
S3_0_c14_c1_0 at min EL1: CNTHCTL_EL21
S3_0_c14_c1_0 at min EL1: CNTKCTL_EL1
S3_0_c14_c1_0 at min EL1: REDIR_CNTHCTL_EL21
S3_0_c14_c1_0 at min EL1: REDIR_CNTKCTL_EL1
S3_0_c15_c0_0 at min EL1: HID0
S3_0_c15_c0_2 at min EL1: HID25
S3_0_c15_c0_3 at min EL1: HID26
S3_0_c15_c0_4 at min EL1: HID27
S3_0_c15_c0_5 at min EL1: HID28
S3_0_c15_c0_6 at min EL1: HID29
S3_0_c15_c10_0 at min EL1: HID10
S3_0_c15_c10_2 at min EL1: BLOCK_CMAINT_CFG
S3_0_c15_c11_0 at min EL1: HID11
S3_0_c15_c11_2 at min EL1: HID18
S3_0_c15_c12_0 at min EL1: HID12
S3_0_c15_c12_1 at min EL1: HID15
S3_0_c15_c12_2 at min EL1: HID19
S3_0_c15_c13_0 at min EL1: BIU_TLIMIT
S3_0_c15_c14_0 at min EL1: HID13
S3_0_c15_c15_0 at min EL1: HID14
S3_0_c15_c15_2 at min EL1: HID16
S3_0_c15_c15_3 at min EL1: LLC_WRR2
S3_0_c15_c15_5 at min EL1: HID17
S3_0_c15_c15_6 at min EL1: HID24
S3_0_c15_c1_0 at min EL1: HID1
S3_0_c15_c1_3 at min EL1: HID21
S3_0_c15_c1_4 at min EL1: HID22
S3_0_c15_c1_5 at min EL1: HID23
S3_0_c15_c2_0 at min EL1: HID2
S3_0_c15_c3_0 at min EL1: HID3
S3_0_c15_c4_0 at min EL1: HID4
S3_0_c15_c5_0 at min EL1: HID5
S3_0_c15_c6_0 at min EL1: HID6
S3_0_c15_c7_0 at min EL1: HID7
S3_0_c15_c8_0 at min EL1: HID8
S3_0_c15_c9_0 at min EL1: HID9
S3_0_c1_c0_0 at min EL1: SCTLR_EL1
S3_0_c1_c0_0 at min EL1: SCTLR_EL21
S3_0_c1_c0_1 at min EL1: ACTLR_EL1
S3_0_c1_c0_1 at min EL1: ACTLR_EL21
S3_0_c1_c0_2 at min EL1: CPACR_EL1
S3_0_c1_c0_2 at min EL1: CPTR_EL21
S3_0_c2_c0_0 at min EL1: TTBR0_EL1
S3_0_c2_c0_0 at min EL1: TTBR0_EL21
S3_0_c2_c0_1 at min EL1: TTBR1_EL1
S3_0_c2_c0_1 at min EL1: TTBR1_EL21
S3_0_c2_c0_2 at min EL1: TCR_EL1
S3_0_c2_c0_2 at min EL1: TCR_EL21
S3_0_c2_c1_0 at min EL1: APIAKeyLo_EL1
S3_0_c2_c1_0 at min EL1: APIAKeyLo_EL21
S3_0_c2_c1_1 at min EL1: APIAKeyHi_EL1
S3_0_c2_c1_1 at min EL1: APIAKeyHi_EL21
S3_0_c2_c1_2 at min EL1: APIBKeyLo_EL1
S3_0_c2_c1_2 at min EL1: APIBKeyLo_EL21
S3_0_c2_c1_3 at min EL1: APIBKeyHi_EL1
S3_0_c2_c1_3 at min EL1: APIBKeyHi_EL21
S3_0_c2_c2_0 at min EL1: APDAKeyLo_EL1
S3_0_c2_c2_0 at min EL1: APDAKeyLo_EL21
S3_0_c2_c2_1 at min EL1: APDAKeyHi_EL1
S3_0_c2_c2_1 at min EL1: APDAKeyHi_EL21
S3_0_c2_c2_2 at min EL1: APDBKeyLo_EL1
S3_0_c2_c2_2 at min EL1: APDBKeyLo_EL21
S3_0_c2_c2_3 at min EL1: APDBKeyHi_EL1
S3_0_c2_c2_3 at min EL1: APDBKeyHi_EL21
S3_0_c2_c3_0 at min EL1: APGAKeyLo_EL1
S3_0_c2_c3_0 at min EL1: APGAKeyLo_EL21
S3_0_c2_c3_1 at min EL1: APGAKeyHi_EL1
S3_0_c2_c3_1 at min EL1: APGAKeyHi_EL21
S3_0_c4_c0_0 at min EL1: SPSR_EL1
S3_0_c4_c0_0 at min EL1: SPSR_EL21
S3_0_c4_c0_1 at min EL1: ELR_EL1
S3_0_c4_c0_1 at min EL1: ELR_EL21
S3_0_c4_c1_0 at min EL1: SP_EL0
S3_0_c4_c2_0 at min EL1: SPSEL
S3_0_c4_c2_2 at min EL1: CurrentEL
S3_0_c4_c2_2 at min EL1: NestedCurrentEL
S3_0_c4_c2_3 at min EL1: PAN
S3_0_c4_c2_4 at min EL1: UAO
S3_0_c4_c6_0 at min EL1: ICV_PMR_EL1
S3_0_c5_c1_0 at min EL1: AFSR0_EL1
S3_0_c5_c1_0 at min EL1: AFSR0_EL21
S3_0_c5_c1_1 at min EL1: AFSR1_EL1
S3_0_c5_c1_1 at min EL1: AFSR1_EL21
S3_0_c5_c2_0 at min EL1: ESR_EL1
S3_0_c5_c2_0 at min EL1: ESR_EL21
S3_0_c5_c3_0 at min EL1: ERRIDR_EL1
S3_0_c6_c0_0 at min EL1: FAR_EL1
S3_0_c6_c0_0 at min EL1: FAR_EL21
S3_0_c7_c4_0 at min EL1: PAR_EL1
S3_1_c0_c0_0 at min EL1: CCSIDRLLC_EL1
S3_1_c0_c0_0 at min EL1: CCSIDRPL1_D_EL1
S3_1_c0_c0_0 at min EL1: CCSIDRPL1_I_EL1
S3_1_c0_c0_0 at min EL1: CCSIDR_EL1
S3_1_c0_c0_1 at min EL1: CLIDR_EL1
S3_1_c0_c0_7 at min EL1: AIDR_EL1
S3_1_c15_c0_0 at min EL1: PMCR0_EL1
S3_1_c15_c0_1 at min EL1: APPL_CONTEXTPTR
S3_1_c15_c0_2 at min EL1: LD_LATPROF_CTL_EL1
S3_1_c15_c0_2 at min EL1: LD_LATPROF_CTL_EL21
S3_1_c15_c0_3 at min EL1: AON_CPU_MSTALL_CTL01_EL1
S3_1_c15_c0_4 at min EL1: PM_MEMFLT_CTL23_EL1
S3_1_c15_c0_5 at min EL1: ACNTHV_CTL_EL21
S3_1_c15_c0_5 at min EL1: ACNTV_CTL_EL0
S3_1_c15_c0_5 at min EL1: REDIR_ACNTHV_CTL_EL21
S3_1_c15_c0_5 at min EL1: REDIR_ACNTV_CTL_EL0
S3_1_c15_c0_6 at min EL1: ACNTVCTSS_NOREDIR_EL0
S3_1_c15_c0_6 at min EL1: LCL_ACNTVCTSS_NOREDIR_EL0
S3_1_c15_c10_0 at min EL1: OPMSK1_EL1
S3_1_c15_c10_2 at min EL2: LD_LATPROF_INF_EL2
S3_1_c15_c10_3 at min EL1: AON_CPU_MSTALL_CTR2_EL1
S3_1_c15_c10_4 at min EL1: ACNTHP_CVAL_EL21
S3_1_c15_c10_4 at min EL1: ACNTP_CVAL_EL0
S3_1_c15_c10_4 at min EL1: REDIR_ACNTHP_CVAL_EL21
S3_1_c15_c10_4 at min EL1: REDIR_ACNTP_CVAL_EL0
S3_1_c15_c10_5 at min EL1: CNTHV_CVAL_NOREDIR_EL21
S3_1_c15_c10_5 at min EL1: CNTV_CVAL_NOREDIR_EL0
S3_1_c15_c10_6 at min EL1: ACNTPCT_NOREDIR_EL0
S3_1_c15_c10_6 at min EL1: LCL_ACNTPCT_NOREDIR_EL0
S3_1_c15_c11_0 at min EL1: PMCR_AFFINITY_EL1
S3_1_c15_c11_3 at min EL1: AON_CPU_MSTALL_CTR3_EL1
S3_1_c15_c11_4 at min EL1: ACNTHP_TVAL_EL21
S3_1_c15_c11_4 at min EL1: ACNTP_TVAL_EL0
S3_1_c15_c11_4 at min EL1: REDIR_ACNTHP_TVAL_EL21
S3_1_c15_c11_4 at min EL1: REDIR_ACNTP_TVAL_EL0
S3_1_c15_c11_5 at min EL1: CNTHV_TVAL_NOREDIR_EL21
S3_1_c15_c11_5 at min EL1: CNTV_TVAL_NOREDIR_EL0
S3_1_c15_c11_6 at min EL2: VMSA_HV_LOCK_EL2
S3_1_c15_c12_0 at min EL1: PMSWCTRL_EL1
S3_1_c15_c12_1 at min EL1: PMCR5_EL0
S3_1_c15_c12_3 at min EL1: AON_CPU_MSTALL_CTR4_EL1
S3_1_c15_c12_4 at min EL1: PMCompare0_EL1
S3_1_c15_c12_5 at min EL1: PMCompare1_EL1
S3_1_c15_c12_6 at min EL2: VMSA_NV_LOCK_EL2
S3_1_c15_c13_0 at min EL1: PMSR_EL1
S3_1_c15_c13_3 at min EL1: AON_CPU_MSTALL_CTR5_EL1
S3_1_c15_c13_4 at min EL1: ACNTHP_CTL_EL21
S3_1_c15_c13_4 at min EL1: ACNTP_CTL_EL0
S3_1_c15_c13_4 at min EL1: REDIR_ACNTHP_CTL_EL21
S3_1_c15_c13_4 at min EL1: REDIR_ACNTP_CTL_EL0
S3_1_c15_c13_5 at min EL1: PMCompare5_EL1
S3_1_c15_c13_6 at min EL1: PMCompare6_EL1
S3_1_c15_c13_7 at min EL1: PMCompare7_EL1
S3_1_c15_c14_0 at min EL1: PMCR_BVRNG4_EL1
S3_1_c15_c14_1 at min EL1: PM_PMI_PC
S3_1_c15_c14_3 at min EL1: AON_CPU_MSTALL_CTR6_EL1
S3_1_c15_c14_4 at min EL1: ACNTHV_CVAL_EL21
S3_1_c15_c14_4 at min EL1: ACNTV_CVAL_EL0
S3_1_c15_c14_4 at min EL1: REDIR_ACNTHV_CVAL_EL21
S3_1_c15_c14_4 at min EL1: REDIR_ACNTV_CVAL_EL0
S3_1_c15_c14_5 at min EL1: ACNTVCT_NOREDIR_EL0
S3_1_c15_c14_5 at min EL1: LCL_ACNTVCT_NOREDIR_EL0
S3_1_c15_c15_0 at min EL1: PMCR_BVRNG5_EL1
S3_1_c15_c15_3 at min EL1: AON_CPU_MSTALL_CTR7_EL1
S3_1_c15_c15_4 at min EL1: ACNTHV_TVAL_EL21
S3_1_c15_c15_4 at min EL1: ACNTV_TVAL_EL0
S3_1_c15_c15_4 at min EL1: REDIR_ACNTHV_TVAL_EL21
S3_1_c15_c15_4 at min EL1: REDIR_ACNTV_TVAL_EL0
S3_1_c15_c15_5 at min EL1: ACNTPCTSS_NOREDIR_EL0
S3_1_c15_c15_5 at min EL1: LCL_ACNTPCTSS_NOREDIR_EL0
S3_1_c15_c1_0 at min EL1: PMCR1_EL1
S3_1_c15_c1_0 at min EL1: PMCR1_EL21
S3_1_c15_c1_2 at min EL1: LD_LATPROF_CTR_EL1
S3_1_c15_c1_3 at min EL1: AON_CPU_MSTALL_CTL23_EL1
S3_1_c15_c1_4 at min EL1: PM_MEMFLT_CTL45_EL1
S3_1_c15_c1_5 at min EL1: ACNTRDIR_EL1
S3_1_c15_c1_5 at min EL1: ACNTRDIR_EL21
S3_1_c15_c1_6 at min EL1: ACNTHCTL_NOREDIR_EL21
S3_1_c15_c1_6 at min EL1: ACNTKCTL_NOREDIR_EL1
S3_1_c15_c2_0 at min EL1: PMCR2_EL1
S3_1_c15_c2_2 at min EL1: LD_LATPROF_STS_EL1
S3_1_c15_c2_3 at min EL1: AON_CPU_MSTALL_CTL45_EL1
S3_1_c15_c2_4 at min EL2: ACNTHP_CVAL_EL2
S3_1_c15_c2_4 at min EL2: REDIR_ACNTHP_CVAL_EL2
S3_1_c15_c2_5 at min EL1: CNTVCT_NOREDIR_EL0
S3_1_c15_c2_5 at min EL1: LCL_CNTVCT_NOREDIR_EL0
S3_1_c15_c2_6 at min EL1: ACNTHP_CVAL_NOREDIR_EL21
S3_1_c15_c2_6 at min EL1: ACNTP_CVAL_NOREDIR_EL0
S3_1_c15_c3_0 at min EL1: PMCR3_EL1
S3_1_c15_c3_2 at min EL1: LD_LATPROF_INF_EL1
S3_1_c15_c3_3 at min EL1: AON_CPU_MSTALL_CTL67_EL1
S3_1_c15_c3_4 at min EL2: ACNTHP_TVAL_EL2
S3_1_c15_c3_4 at min EL2: REDIR_ACNTHP_TVAL_EL2
S3_1_c15_c3_5 at min EL1: CNTPCTSS_NOREDIR_EL0
S3_1_c15_c3_5 at min EL1: LCL_CNTPCTSS_NOREDIR_EL0
S3_1_c15_c3_6 at min EL1: ACNTHP_TVAL_NOREDIR_EL21
S3_1_c15_c3_6 at min EL1: ACNTP_TVAL_NOREDIR_EL0
S3_1_c15_c4_0 at min EL1: PMCR4_EL1
S3_1_c15_c4_2 at min EL2: LD_LATPROF_CTL_EL2
S3_1_c15_c4_3 at min EL1: AON_CPU_MEMFLT_CTL01_EL1
S3_1_c15_c4_4 at min EL2: ACNTHP_CTL_EL2
S3_1_c15_c4_4 at min EL2: REDIR_ACNTHP_CTL_EL2
S3_1_c15_c4_5 at min EL1: CNTVCTSS_NOREDIR_EL0
S3_1_c15_c4_5 at min EL1: LCL_CNTVCTSS_NOREDIR_EL0
S3_1_c15_c4_6 at min EL1: ACNTHP_CTL_NOREDIR_EL21
S3_1_c15_c4_6 at min EL1: ACNTP_CTL_NOREDIR_EL0
S3_1_c15_c5_0 at min EL1: PMESR0_EL1
S3_1_c15_c5_2 at min EL1: LD_LATPROF_CMD_EL1
S3_1_c15_c5_3 at min EL1: AON_CPU_MEMFLT_CTL23_EL1
S3_1_c15_c5_4 at min EL2: ACNTHV_CVAL_EL2
S3_1_c15_c5_4 at min EL2: REDIR_ACNTHV_CVAL_EL2
S3_1_c15_c5_6 at min EL1: ACNTHV_CVAL_NOREDIR_EL21
S3_1_c15_c5_6 at min EL1: ACNTV_CVAL_NOREDIR_EL0
S3_1_c15_c6_0 at min EL1: PMESR1_EL1
S3_1_c15_c6_2 at min EL2: PMCR1_EL2
S3_1_c15_c6_3 at min EL1: AON_CPU_MEMFLT_CTL45_EL1
S3_1_c15_c6_4 at min EL2: ACNTHV_TVAL_EL2
S3_1_c15_c6_4 at min EL2: REDIR_ACNTHV_TVAL_EL2
S3_1_c15_c6_5 at min EL1: CNTHCTL_NOREDIR_EL21
S3_1_c15_c6_5 at min EL1: CNTKCTL_NOREDIR_EL1
S3_1_c15_c6_6 at min EL1: ACNTHV_TVAL_NOREDIR_EL21
S3_1_c15_c6_6 at min EL1: ACNTV_TVAL_NOREDIR_EL0
S3_1_c15_c7_0 at min EL1: OPMAT0_EL1
S3_1_c15_c7_2 at min EL2: PMCR1_EL12
S3_1_c15_c7_3 at min EL1: AON_CPU_MEMFLT_CTL67_EL1
S3_1_c15_c7_4 at min EL2: ACNTHV_CTL_EL2
S3_1_c15_c7_4 at min EL2: REDIR_ACNTHV_CTL_EL2
S3_1_c15_c7_5 at min EL1: CNTHP_CVAL_NOREDIR_EL21
S3_1_c15_c7_5 at min EL1: CNTP_CVAL_NOREDIR_EL0
S3_1_c15_c7_6 at min EL1: ACNTHV_CTL_NOREDIR_EL21
S3_1_c15_c7_6 at min EL1: ACNTV_CTL_NOREDIR_EL0
S3_1_c15_c8_0 at min EL1: OPMAT1_EL1
S3_1_c15_c8_2 at min EL2: PMCR1_GL12
S3_1_c15_c8_3 at min EL1: AON_CPU_MSTALL_CTR0_EL1
S3_1_c15_c8_4 at min EL1: ACNTFRQ_EL0
S3_1_c15_c8_4 at min EL1: REDIR_ACNTFRQ_EL0
S3_1_c15_c8_5 at min EL1: CNTHP_TVAL_NOREDIR_EL21
S3_1_c15_c8_5 at min EL1: CNTP_TVAL_NOREDIR_EL0
S3_1_c15_c8_6 at min EL1: CNTPCT_NOREDIR_EL0
S3_1_c15_c8_6 at min EL1: LCL_CNTPCT_NOREDIR_EL0
S3_1_c15_c9_0 at min EL1: OPMSK0_EL1
S3_1_c15_c9_2 at min EL2: LD_LATPROF_CTL_EL12
S3_1_c15_c9_3 at min EL1: AON_CPU_MSTALL_CTR1_EL1
S3_1_c15_c9_4 at min EL2: ACNTVOFF_EL2
S3_1_c15_c9_5 at min EL1: CNTHP_CTL_NOREDIR_EL21
S3_1_c15_c9_5 at min EL1: CNTP_CTL_NOREDIR_EL0
S3_1_c15_c9_6 at min EL1: CNTHV_CTL_NOREDIR_EL21
S3_1_c15_c9_6 at min EL1: CNTV_CTL_NOREDIR_EL0
S3_2_c0_c0_0 at min EL1: CSSELR_EL1
S3_2_c15_c0_0 at min EL1: PMC0
S3_2_c15_c0_1 at min EL1: UPMCFILTER0
S3_2_c15_c0_2 at min EL1: UPMCFILTER1
S3_2_c15_c0_3 at min EL1: UPMCFILTER2
S3_2_c15_c0_4 at min EL1: UPMCFILTER3
S3_2_c15_c0_5 at min EL1: UPMCFILTER4
S3_2_c15_c0_6 at min EL1: UPMCFILTER5
S3_2_c15_c0_7 at min EL1: UPMCFILTER6
S3_2_c15_c10_0 at min EL1: PMC9
S3_2_c15_c12_0 at min EL1: PMTRHLD6_EL1
S3_2_c15_c13_0 at min EL1: PMTRHLD4_EL1
S3_2_c15_c14_0 at min EL1: PMTRHLD2_EL1
S3_2_c15_c15_0 at min EL1: PMMMAP_EL1
S3_2_c15_c1_0 at min EL1: PMC1
S3_2_c15_c1_1 at min EL1: UPMCFILTER7
S3_2_c15_c2_0 at min EL1: PMC2
S3_2_c15_c3_0 at min EL1: PMC3
S3_2_c15_c4_0 at min EL1: PMC4
S3_2_c15_c5_0 at min EL1: PMC5
S3_2_c15_c6_0 at min EL1: PMC6
S3_2_c15_c7_0 at min EL1: PMC7
S3_2_c15_c9_0 at min EL1: PMC8
S3_3_c0_c0_1 at min EL1: CTR_EL0
S3_3_c0_c0_7 at min EL1: DCZID_EL0
S3_3_c13_c0_2 at min EL1: TPIDR_EL0
S3_3_c13_c0_3 at min EL1: TPIDRRO_EL0
S3_3_c14_c0_0 at min EL1: CNTFRQ_EL0
S3_3_c14_c0_0 at min EL1: REDIR_CNTFRQ_EL0
S3_3_c14_c0_1 at min EL1: CNTPCT_EL0
S3_3_c14_c0_1 at min EL1: LCL_CNTPCT_EL0
S3_3_c14_c0_1 at min EL1: REDIR_CNTPCT_EL0
S3_3_c14_c0_1 at min EL1: REDIR_LCL_CNTPCT_EL0
S3_3_c14_c0_2 at min EL1: CNTVCT_EL0
S3_3_c14_c0_2 at min EL1: LCL_CNTVCT_EL0
S3_3_c14_c0_2 at min EL1: REDIR_CNTVCT_EL0
S3_3_c14_c0_2 at min EL1: REDIR_LCL_CNTVCT_EL0
S3_3_c14_c0_5 at min EL1: CNTPCTSS_EL0
S3_3_c14_c0_5 at min EL1: LCL_CNTPCTSS_EL0
S3_3_c14_c0_5 at min EL1: REDIR_CNTPCTSS_EL0
S3_3_c14_c0_5 at min EL1: REDIR_LCL_CNTPCTSS_EL0
S3_3_c14_c0_6 at min EL1: CNTVCTSS_EL0
S3_3_c14_c0_6 at min EL1: LCL_CNTVCTSS_EL0
S3_3_c14_c0_6 at min EL1: REDIR_CNTVCTSS_EL0
S3_3_c14_c0_6 at min EL1: REDIR_LCL_CNTVCTSS_EL0
S3_3_c14_c2_0 at min EL1: CNTHP_TVAL_EL21
S3_3_c14_c2_0 at min EL1: CNTP_TVAL_EL0
S3_3_c14_c2_0 at min EL1: REDIR_CNTHP_TVAL_EL21
S3_3_c14_c2_0 at min EL1: REDIR_CNTP_TVAL_EL0
S3_3_c14_c2_1 at min EL1: CNTHP_CTL_EL21
S3_3_c14_c2_1 at min EL1: CNTP_CTL_EL0
S3_3_c14_c2_1 at min EL1: REDIR_CNTHP_CTL_EL21
S3_3_c14_c2_1 at min EL1: REDIR_CNTP_CTL_EL0
S3_3_c14_c2_2 at min EL1: CNTHP_CVAL_EL21
S3_3_c14_c2_2 at min EL1: CNTP_CVAL_EL0
S3_3_c14_c2_2 at min EL1: REDIR_CNTHP_CVAL_EL21
S3_3_c14_c2_2 at min EL1: REDIR_CNTP_CVAL_EL0
S3_3_c14_c3_0 at min EL1: CNTHV_TVAL_EL21
S3_3_c14_c3_0 at min EL1: CNTV_TVAL_EL0
S3_3_c14_c3_0 at min EL1: REDIR_CNTHV_TVAL_EL21
S3_3_c14_c3_0 at min EL1: REDIR_CNTV_TVAL_EL0
S3_3_c14_c3_1 at min EL1: CNTHV_CTL_EL21
S3_3_c14_c3_1 at min EL1: CNTV_CTL_EL0
S3_3_c14_c3_1 at min EL1: REDIR_CNTHV_CTL_EL21
S3_3_c14_c3_1 at min EL1: REDIR_CNTV_CTL_EL0
S3_3_c14_c3_2 at min EL1: CNTHV_CVAL_EL21
S3_3_c14_c3_2 at min EL1: CNTV_CVAL_EL0
S3_3_c14_c3_2 at min EL1: REDIR_CNTHV_CVAL_EL21
S3_3_c14_c3_2 at min EL1: REDIR_CNTV_CVAL_EL0
S3_3_c15_c0_0 at min EL1: LSU_ERR_STS
S3_3_c15_c0_4 at min EL1: AFLATCTL1_EL1
S3_3_c15_c0_5 at min EL1: AFLATVALBIN0_EL1
S3_3_c15_c0_6 at min EL1: AFLATINFLO_EL1
S3_3_c15_c10_0 at min EL1: LLC_ERR_INF
S3_3_c15_c10_1 at min EL1: USERTAGSEL_EL1
S3_3_c15_c10_2 at min EL1: UUSERTAG_EL0
S3_3_c15_c10_3 at min EL1: KUSERTAG_EL1
S3_3_c15_c10_4 at min EL2: HUSERTAG_EL2
S3_3_c15_c11_0 at min EL1: LLC_TRACE_CTL0
S3_3_c15_c12_0 at min EL1: LLC_TRACE_CTL1
S3_3_c15_c13_0 at min EL1: LLC_UP_REQ_VC
S3_3_c15_c13_1 at min EL1: LLC_UP_REQ_VC_THRESH
S3_3_c15_c13_2 at min EL1: LLC_UP_REQ_VC_2
S3_3_c15_c13_3 at min EL1: LLC_UP_REQ_VC_THRESH_2
S3_3_c15_c13_4 at min EL1: LLC_DRAM_HASH0
S3_3_c15_c13_5 at min EL1: LLC_DRAM_HASH1
S3_3_c15_c13_6 at min EL1: LLC_DRAM_HASH2
S3_3_c15_c13_7 at min EL1: LLC_DRAM_HASH3
S3_3_c15_c14_0 at min EL1: LLC_TRACE_CTL2
S3_3_c15_c15_0 at min EL1: LLC_HASH0
S3_3_c15_c15_1 at min EL1: LLC_HASH1
S3_3_c15_c15_2 at min EL1: LLC_HASH2
S3_3_c15_c15_3 at min EL1: LLC_HASH3
S3_3_c15_c15_4 at min EL1: LLC_WRR
S3_3_c15_c1_0 at min EL1: LSU_ERR_CTL
S3_3_c15_c1_4 at min EL1: AFLATCTL2_EL1
S3_3_c15_c1_5 at min EL1: AFLATVALBIN1_EL1
S3_3_c15_c1_6 at min EL1: AFLATINFHI_EL1
S3_3_c15_c2_4 at min EL1: AFLATCTL3_EL1
S3_3_c15_c2_5 at min EL1: AFLATVALBIN2_EL1
S3_3_c15_c3_4 at min EL1: AFLATCTL4_EL1
S3_3_c15_c3_5 at min EL1: AFLATVALBIN3_EL1
S3_3_c15_c4_0 at min EL1: LLC_FILL_CTL
S3_3_c15_c4_4 at min EL1: AFLATCTL5_LO_EL1
S3_3_c15_c4_5 at min EL1: AFLATVALBIN4_EL1
S3_3_c15_c4_6 at min EL1: AFLATCTL5_HI_EL1
S3_3_c15_c5_0 at min EL1: LLC_FILL_DAT
S3_3_c15_c5_5 at min EL1: AFLATVALBIN5_EL1
S3_3_c15_c6_5 at min EL1: AFLATVALBIN6_EL1
S3_3_c15_c7_0 at min EL1: LLC_RAM_CONFIG
S3_3_c15_c7_5 at min EL1: AFLATVALBIN7_EL1
S3_3_c15_c8_0 at min EL1: LLC_ERR_STS
S3_3_c15_c8_1 at min EL1: CMAINT_BCAST_LIST_0
S3_3_c15_c8_2 at min EL1: CMAINT_BCAST_LIST_1
S3_3_c15_c8_3 at min EL1: CMAINT_BCAST_CTL
S3_3_c15_c9_0 at min EL1: LLC_ERR_ADR
S3_3_c15_c9_1 at min EL1: LLC_ERR_CTL
S3_3_c15_c9_2 at min EL1: LLC_ERR_INJ
S3_3_c4_c2_0 at min EL1: NZCV
S3_3_c4_c2_1 at min EL1: DAIF
S3_3_c4_c2_5 at min EL1: DIT
S3_3_c4_c2_6 at min EL1: SSBS
S3_3_c4_c4_0 at min EL1: FPCR
S3_3_c4_c4_1 at min EL1: FPSR
S3_3_c4_c5_0 at min EL0: DSPSR
S3_3_c4_c5_0 at min EL1: DSPSR_EL0
S3_3_c4_c5_1 at min EL0: DLR
S3_3_c4_c5_1 at min EL1: DLR_EL0
S3_4_c0_c0_0 at min EL2: VPIDR_EL2
S3_4_c0_c0_5 at min EL2: VMPIDR_EL2
S3_4_c10_c2_0 at min EL2: MAIR_EL2
S3_4_c10_c3_0 at min EL2: AMAIR_EL2
S3_4_c12_c0_0 at min EL2: VBAR_EL2
S3_4_c12_c0_1 at min EL2: RVBAR_EL2
S3_4_c12_c0_2 at min EL2: RMR_EL2
S3_4_c12_c11_0 at min EL2: ICH_HCR_EL2
S3_4_c12_c11_1 at min EL2: ICH_VTR_EL2
S3_4_c12_c11_2 at min EL2: ICH_MISR_EL2
S3_4_c12_c11_3 at min EL2: ICH_EISR_EL2
S3_4_c12_c11_5 at min EL2: ICH_ELRSR_EL2
S3_4_c12_c11_7 at min EL2: ICH_VMCR_EL2
S3_4_c12_c12_0 at min EL2: ICH_LR0_EL2
S3_4_c12_c12_1 at min EL2: ICH_LR1_EL2
S3_4_c12_c12_2 at min EL2: ICH_LR2_EL2
S3_4_c12_c12_3 at min EL2: ICH_LR3_EL2
S3_4_c12_c12_4 at min EL2: ICH_LR4_EL2
S3_4_c12_c12_5 at min EL2: ICH_LR5_EL2
S3_4_c12_c12_6 at min EL2: ICH_LR6_EL2
S3_4_c12_c12_7 at min EL2: ICH_LR7_EL2
S3_4_c12_c1_1 at min EL2: VDISR_EL2
S3_4_c12_c8_0 at min EL2: ICH_AP0R0_EL2
S3_4_c12_c9_0 at min EL2: ICH_AP1R0_EL2
S3_4_c12_c9_5 at min EL2: ICC_SRE_EL2
S3_4_c13_c0_1 at min EL2: CONTEXTIDR_EL2
S3_4_c13_c0_2 at min EL2: TPIDR_EL2
S3_4_c14_c0_3 at min EL2: CNTVOFF_EL2
S3_4_c14_c1_0 at min EL2: CNTHCTL_EL2
S3_4_c14_c1_0 at min EL2: REDIR_CNTHCTL_EL2
S3_4_c14_c2_0 at min EL2: CNTHP_TVAL_EL2
S3_4_c14_c2_0 at min EL2: REDIR_CNTHP_TVAL_EL2
S3_4_c14_c2_1 at min EL2: CNTHP_CTL_EL2
S3_4_c14_c2_1 at min EL2: REDIR_CNTHP_CTL_EL2
S3_4_c14_c2_2 at min EL2: CNTHP_CVAL_EL2
S3_4_c14_c2_2 at min EL2: REDIR_CNTHP_CVAL_EL2
S3_4_c14_c3_0 at min EL2: CNTHV_TVAL_EL2
S3_4_c14_c3_0 at min EL2: REDIR_CNTHV_TVAL_EL2
S3_4_c14_c3_1 at min EL2: CNTHV_CTL_EL2
S3_4_c14_c3_1 at min EL2: REDIR_CNTHV_CTL_EL2
S3_4_c14_c3_2 at min EL2: CNTHV_CVAL_EL2
S3_4_c14_c3_2 at min EL2: REDIR_CNTHV_CVAL_EL2
S3_4_c15_c0_0 at min EL1: FED_ERR_STS
S3_4_c15_c0_1 at min EL1: FED_ERR_CTL
S3_4_c15_c0_4 at min EL1: APCTL_EL1
S3_4_c15_c0_4 at min EL1: APCTL_EL21
S3_4_c15_c0_5 at min EL1: IMPL_MSR_RO_CTRL0_EL1
S3_4_c15_c0_5 at min EL1: IMPL_MSR_RO_CTRL0_EL21
S3_4_c15_c0_7 at min EL2: IMPL_MSR_RO_CTRL0_EL2
S3_4_c15_c10_0 at min EL1: PREDAKEYLo_EL1
S3_4_c15_c10_1 at min EL1: PREDAKEYHi_EL1
S3_4_c15_c10_2 at min EL1: PREDBKEYLo_EL1
S3_4_c15_c10_3 at min EL1: PREDBKEYHi_EL1
S3_4_c15_c10_4 at min EL1: SIQ_CFG_EL1
S3_4_c15_c10_5 at min EL1: ACNTPCTSS_EL0
S3_4_c15_c10_5 at min EL1: LCL_ACNTPCTSS_EL0
S3_4_c15_c10_5 at min EL1: REDIR_ACNTPCTSS_EL0
S3_4_c15_c10_5 at min EL1: REDIR_LCL_ACNTPCTSS_EL0
S3_4_c15_c10_6 at min EL1: ACNTVCTSS_EL0
S3_4_c15_c10_6 at min EL1: LCL_ACNTVCTSS_EL0
S3_4_c15_c10_6 at min EL1: REDIR_ACNTVCTSS_EL0
S3_4_c15_c10_6 at min EL1: REDIR_LCL_ACNTVCTSS_EL0
S3_4_c15_c10_7 at min EL2: AVNCR_EL2
S3_4_c15_c11_0 at min EL2: ACC_CTRR_A_LWR_EL2
S3_4_c15_c11_1 at min EL2: ACC_CTRR_A_UPR_EL2
S3_4_c15_c11_2 at min EL2: ACC_CTRR_B_LWR_EL2
S3_4_c15_c11_3 at min EL2: ACC_CTRR_B_UPR_EL2
S3_4_c15_c11_4 at min EL2: ACC_CTRR_CTL_EL2
S3_4_c15_c11_5 at min EL2: ACC_CTRR_LOCK_EL2
S3_4_c15_c11_6 at min EL1: ACNTPCT_EL0
S3_4_c15_c11_6 at min EL1: LCL_ACNTPCT_EL0
S3_4_c15_c11_6 at min EL1: REDIR_ACNTPCT_EL0
S3_4_c15_c11_6 at min EL1: REDIR_LCL_ACNTPCT_EL0
S3_4_c15_c11_7 at min EL1: ACNTVCT_EL0
S3_4_c15_c11_7 at min EL1: LCL_ACNTVCT_EL0
S3_4_c15_c11_7 at min EL1: REDIR_ACNTVCT_EL0
S3_4_c15_c11_7 at min EL1: REDIR_LCL_ACNTVCT_EL0
S3_4_c15_c12_0 at min EL1: ACFG_EL1
S3_4_c15_c12_1 at min EL2: AHCR_EL2
S3_4_c15_c12_2 at min EL1: APL_INTSTATUS_EL1
S3_4_c15_c12_2 at min EL1: APL_INTSTATUS_EL21
S3_4_c15_c12_3 at min EL2: APL_INTSTATUS_EL2
S3_4_c15_c12_5 at min EL1: IMPL_MSR_LOCK_EL1
S3_4_c15_c12_5 at min EL1: IMPL_MSR_LOCK_EL21
S3_4_c15_c12_6 at min EL2: ACNTHCTL_EL2
S3_4_c15_c12_6 at min EL2: REDIR_ACNTHCTL_EL2
S3_4_c15_c12_7 at min EL2: IMPL_MSR_LOCK_EL2
S3_4_c15_c13_0 at min EL1: JAPIAKeyLo_NV_EL21
S3_4_c15_c13_0 at min EL2: JAPIAKeyLo_EL2
S3_4_c15_c13_1 at min EL1: JAPIAKeyHi_NV_EL21
S3_4_c15_c13_1 at min EL2: JAPIAKeyHi_EL2
S3_4_c15_c13_2 at min EL1: JAPIBKeyLo_NV_EL21
S3_4_c15_c13_2 at min EL2: JAPIBKeyLo_EL2
S3_4_c15_c13_3 at min EL1: JAPIBKeyHi_NV_EL21
S3_4_c15_c13_3 at min EL2: JAPIBKeyHi_EL2
S3_4_c15_c13_4 at min EL1: JAPIAKeyLo_EL1
S3_4_c15_c13_4 at min EL1: JAPIAKeyLo_EL21
S3_4_c15_c13_5 at min EL1: JAPIAKeyHi_EL1
S3_4_c15_c13_5 at min EL1: JAPIAKeyHi_EL21
S3_4_c15_c13_6 at min EL1: JAPIBKeyLo_EL1
S3_4_c15_c13_6 at min EL1: JAPIBKeyLo_EL21
S3_4_c15_c13_7 at min EL1: JAPIBKeyHi_EL1
S3_4_c15_c13_7 at min EL1: JAPIBKeyHi_EL21
S3_4_c15_c14_0 at min EL2: JAPIAKeyLo_EL12
S3_4_c15_c14_1 at min EL2: JAPIAKeyHi_EL12
S3_4_c15_c14_2 at min EL2: JAPIBKeyLo_EL12
S3_4_c15_c14_3 at min EL2: JAPIBKeyHi_EL12
S3_4_c15_c14_5 at min EL2: ACNTRDIR_EL2
S3_4_c15_c14_6 at min EL2: ACNTRDIR_EL12
S3_4_c15_c15_0 at min EL2: JRANGE_EL2
S3_4_c15_c15_1 at min EL1: JRANGE_EL1
S3_4_c15_c15_1 at min EL1: JRANGE_EL21
S3_4_c15_c15_2 at min EL2: JRANGE_EL12
S3_4_c15_c15_3 at min EL2: JCTL_EL2
S3_4_c15_c15_4 at min EL1: JCTL_EL1
S3_4_c15_c15_4 at min EL1: JCTL_EL21
S3_4_c15_c15_5 at min EL2: JCTL_EL12
S3_4_c15_c15_6 at min EL1: JCTL_EL0
S3_4_c15_c15_7 at min EL1: AMDSCR_EL1
S3_4_c15_c1_0 at min EL1: KERNKEYLo_EL1
S3_4_c15_c1_0 at min EL1: KERNKEYLo_EL21
S3_4_c15_c1_1 at min EL1: KERNKEYHi_EL1
S3_4_c15_c1_1 at min EL1: KERNKEYHi_EL21
S3_4_c15_c1_2 at min EL1: VMSALock_EL21
S3_4_c15_c1_2 at min EL1: VMSA_LOCK_EL1
S3_4_c15_c1_3 at min EL1: AMX_STATE_T_EL1
S3_4_c15_c1_4 at min EL1: AMX_CONFIG_EL1
S3_4_c15_c1_4 at min EL1: AMX_CONFIG_EL21
S3_4_c15_c1_5 at min EL2: VMSA_LOCK_EL2
S3_4_c15_c1_6 at min EL1: CTRR_B_UPR_EL1
S3_4_c15_c1_6 at min EL1: CTRR_B_UPR_EL21
S3_4_c15_c1_7 at min EL1: CTRR_B_LWR_EL1
S3_4_c15_c1_7 at min EL1: CTRR_B_LWR_EL21
S3_4_c15_c2_0 at min EL1: SP_SETUP_GL1
S3_4_c15_c2_0 at min EL1: SP_SETUP_GL21
S3_4_c15_c2_1 at min EL2: SP_SETUP_GL2
S3_4_c15_c2_2 at min EL1: CTRR_LOCK_EL1
S3_4_c15_c2_2 at min EL1: CTRR_LOCK_EL21
S3_4_c15_c2_3 at min EL1: CTRR_A_LWR_EL1
S3_4_c15_c2_3 at min EL1: CTRR_A_LWR_EL21
S3_4_c15_c2_4 at min EL1: CTRR_A_UPR_EL1
S3_4_c15_c2_4 at min EL1: CTRR_A_UPR_EL21
S3_4_c15_c2_5 at min EL1: CTRR_CTL_EL1
S3_4_c15_c2_5 at min EL1: CTRR_CTL_EL21
S3_4_c15_c2_6 at min EL2: VMSA_LOCK_EL12
S3_4_c15_c2_7 at min EL1: ACNTV_CTL_EL02
S3_4_c15_c3_0 at min EL1: AMX_STATE_C0_EL1
S3_4_c15_c3_1 at min EL1: AMX_STATE_C1_EL1
S3_4_c15_c3_2 at min EL1: AMX_STATE_C2_EL1
S3_4_c15_c3_3 at min EL1: AMX_STATE_C3_EL1
S3_4_c15_c3_4 at min EL1: AMX_STATUS_C0_EL1
S3_4_c15_c3_5 at min EL1: AMX_STATUS_C1_EL1
S3_4_c15_c3_6 at min EL1: AMX_STATUS_C2_EL1
S3_4_c15_c3_7 at min EL1: AMX_STATUS_C3_EL1
S3_4_c15_c4_0 at min EL1: AMX_NUMCTXT_EL1
S3_4_c15_c4_1 at min EL1: ACNTP_CVAL_EL02
S3_4_c15_c4_2 at min EL1: REDIR_ACNTP_TVAL_EL02
S3_4_c15_c4_3 at min EL1: ACNTP_CTL_EL02
S3_4_c15_c4_4 at min EL1: ACNTV_CVAL_EL02
S3_4_c15_c4_5 at min EL1: ACNTV_TVAL_EL02
S3_4_c15_c4_6 at min EL2: AMX_CONFIG_EL12
S3_4_c15_c4_7 at min EL2: AMX_CONFIG_EL2
S3_4_c15_c5_0 at min EL1: AMX_CONTEXT_EL1
S3_4_c15_c5_1 at min EL1: SPRR_HUPERM_EL0
S3_4_c15_c5_2 at min EL1: SPRR_VUPERM_EL0
S3_4_c15_c5_6 at min EL1: AMX_PRIORITY_C0_EL1
S3_4_c15_c5_7 at min EL1: AMX_PRIORITY_C1_EL1
S3_4_c15_c6_0 at min EL1: AMX_PRIORITY_C2_EL1
S3_4_c15_c6_1 at min EL1: AMX_PRIORITY_C3_EL1
S3_4_c15_c6_2 at min EL2: CTRR_CTL_EL2
S3_4_c15_c6_3 at min EL2: CTRR_LOCK_EL2
S3_4_c15_c6_4 at min EL2: CTRR_A_LWR_EL2
S3_4_c15_c6_5 at min EL2: CTRR_A_UPR_EL2
S3_4_c15_c6_6 at min EL2: CTRR_B_LWR_EL2
S3_4_c15_c6_7 at min EL2: CTRR_B_UPR_EL2
S3_4_c15_c7_0 at min EL2: SPRR_HUMPRR_EL2
S3_4_c15_c7_1 at min EL2: SPRR_HUPERM_SH01_EL2
S3_4_c15_c7_2 at min EL2: SPRR_HUPERM_SH02_EL2
S3_4_c15_c7_3 at min EL2: SPRR_HUPERM_SH03_EL2
S3_4_c15_c7_4 at min EL2: SPRR_HUPERM_SH04_EL2
S3_4_c15_c7_5 at min EL2: SPRR_HUPERM_SH05_EL2
S3_4_c15_c7_6 at min EL2: SPRR_HUPERM_SH06_EL2
S3_4_c15_c7_7 at min EL2: SPRR_HUPERM_SH07_EL2
S3_4_c15_c8_0 at min EL1: SPRR_VUMPRR_EL1
S3_4_c15_c8_1 at min EL1: SPRR_VUPERM_SH01_EL1
S3_4_c15_c8_2 at min EL1: SPRR_VUPERM_SH02_EL1
S3_4_c15_c8_3 at min EL1: SPRR_VUPERM_SH03_EL1
S3_4_c15_c8_4 at min EL1: SPRR_VUPERM_SH04_EL1
S3_4_c15_c8_5 at min EL1: SPRR_VUPERM_SH05_EL1
S3_4_c15_c8_6 at min EL1: SPRR_VUPERM_SH06_EL1
S3_4_c15_c8_7 at min EL1: SPRR_VUPERM_SH07_EL1
S3_4_c15_c9_0 at min EL2: CTRR_A_LWR_EL12
S3_4_c15_c9_1 at min EL2: CTRR_A_UPR_EL12
S3_4_c15_c9_2 at min EL2: CTRR_B_LWR_EL12
S3_4_c15_c9_3 at min EL2: CTRR_B_UPR_EL12
S3_4_c15_c9_4 at min EL2: CTRR_CTL_EL12
S3_4_c15_c9_5 at min EL2: CTRR_LOCK_EL12
S3_4_c15_c9_6 at min EL1: ACNTHCTL_EL21
S3_4_c15_c9_6 at min EL1: ACNTKCTL_EL1
S3_4_c15_c9_6 at min EL1: REDIR_ACNTHCTL_EL21
S3_4_c15_c9_6 at min EL1: REDIR_ACNTKCTL_EL1
S3_4_c15_c9_7 at min EL2: ACNTKCTL_EL12
S3_4_c1_c0_0 at min EL2: SCTLR_EL2
S3_4_c1_c0_1 at min EL2: ACTLR_EL2
S3_4_c1_c1_0 at min EL2: HCR_EL2
S3_4_c1_c1_1 at min EL2: MDCR_EL2
S3_4_c1_c1_2 at min EL2: CPTR_EL2
S3_4_c1_c1_3 at min EL2: HSTR_EL2
S3_4_c1_c1_4 at min EL2: HFGRTR_EL2
S3_4_c1_c1_5 at min EL2: HFGWTR_EL2
S3_4_c1_c1_6 at min EL2: HFGITR_EL2
S3_4_c1_c1_7 at min EL2: HACR_EL2
S3_4_c1_c2_2 at min EL2: HCRX_EL2
S3_4_c2_c0_0 at min EL2: TTBR0_EL2
S3_4_c2_c0_1 at min EL2: TTBR1_EL2
S3_4_c2_c0_2 at min EL2: TCR_EL2
S3_4_c2_c1_0 at min EL2: VTTBR_EL2
S3_4_c2_c1_2 at min EL2: VTCR_EL2
S3_4_c2_c2_0 at min EL2: VNCR_EL2
S3_4_c3_c0_0 at min EL2: DACR32_EL2
S3_4_c3_c1_4 at min EL2: HDFGRTR_EL2
S3_4_c3_c1_5 at min EL2: HDFGWTR_EL2
S3_4_c4_c0_0 at min EL1: SPSR_NV_EL21
S3_4_c4_c0_0 at min EL2: SPSR_EL2
S3_4_c4_c0_1 at min EL1: ELR_NV_EL21
S3_4_c4_c0_1 at min EL2: ELR_EL2
S3_4_c4_c1_0 at min EL1: SP_EL1
S3_4_c4_c3_0 at min EL1: SPSR_irq
S3_4_c4_c3_1 at min EL1: SPSR_abt
S3_4_c4_c3_2 at min EL1: SPSR_und
S3_4_c4_c3_3 at min EL1: SPSR_fiq
S3_4_c5_c0_1 at min EL2: IFSR32_EL2
S3_4_c5_c1_0 at min EL2: AFSR0_EL2
S3_4_c5_c1_1 at min EL2: AFSR1_EL2
S3_4_c5_c2_0 at min EL1: ESR_NV_EL21
S3_4_c5_c2_0 at min EL2: ESR_EL2
S3_4_c5_c2_3 at min EL2: VSESR_EL2
S3_4_c5_c3_0 at min EL2: FPEXC32_EL2
S3_4_c6_c0_0 at min EL1: FAR_NV_EL21
S3_4_c6_c0_0 at min EL2: FAR_EL2
S3_4_c6_c0_4 at min EL2: HPFAR_EL2
S3_5_c10_c2_0 at min EL2: MAIR_EL12
S3_5_c10_c3_0 at min EL2: AMAIR_EL12
S3_5_c12_c0_0 at min EL2: VBAR_EL12
S3_5_c13_c0_1 at min EL2: CONTEXTIDR_EL12
S3_5_c14_c1_0 at min EL2: CNTKCTL_EL12
S3_5_c14_c2_0 at min EL1: CNTP_TVAL_EL02
S3_5_c14_c2_1 at min EL1: CNTP_CTL_EL02
S3_5_c14_c2_2 at min EL1: CNTP_CVAL_EL02
S3_5_c14_c3_0 at min EL1: CNTV_TVAL_EL02
S3_5_c14_c3_1 at min EL1: CNTV_CTL_EL02
S3_5_c14_c3_2 at min EL1: CNTV_CVAL_EL02
S3_5_c15_c0_0 at min EL1: IPI_RR_LOCAL_EL1
S3_5_c15_c0_1 at min EL1: IPI_RR_GLOBAL_EL1
S3_5_c15_c0_2 at min EL1: AF_ERR_CFG0
S3_5_c15_c0_3 at min EL1: AP_ERR_CFG0
S3_5_c15_c0_4 at min EL1: AF_ERR_SRC_IDS
S3_5_c15_c0_5 at min EL1: DPC_ERR_STS
S3_5_c15_c0_6 at min EL1: DPC_ERR_CTL
S3_5_c15_c10_0 at min EL1: CPU_STS
S3_5_c15_c10_1 at min EL1: HIST_TRIG
S3_5_c15_c11_0 at min EL1: ARRAY_INDEX
S3_5_c15_c12_0 at min EL1: IL1_DATA0
S3_5_c15_c12_1 at min EL1: IL1_DATA1
S3_5_c15_c12_2 at min EL1: DL1_DATA0
S3_5_c15_c12_3 at min EL1: DL1_DATA1
S3_5_c15_c12_4 at min EL1: MMUDATA0
S3_5_c15_c12_5 at min EL1: MMUDATA1
S3_5_c15_c13_4 at min EL1: LLC_DATA0
S3_5_c15_c13_5 at min EL1: LLC_DATA1
S3_5_c15_c1_0 at min EL1: TRACE_CORE_CFG
S3_5_c15_c1_1 at min EL1: IPI_SR
S3_5_c15_c1_2 at min EL2: APL_LRTMR_EL2
S3_5_c15_c1_3 at min EL2: APL_INTENABLE_EL2
S3_5_c15_c1_4 at min EL1: KTRACE_MESSAGE
S3_5_c15_c1_5 at min EL1: TRACE_CORE_CFG_EXT
S3_5_c15_c1_6 at min EL1: WatchDogDiag0
S3_5_c15_c1_7 at min EL1: WatchDogDiag1
S3_5_c15_c2_0 at min EL1: DBG_WRAP_GLB
S3_5_c15_c2_1 at min EL1: TRACE_STREAM_BASE
S3_5_c15_c2_2 at min EL1: TRACE_STREAM_FILL
S3_5_c15_c2_3 at min EL1: TRACE_STREAM_BASE1
S3_5_c15_c2_4 at min EL1: TRACE_STREAM_FILL1
S3_5_c15_c2_5 at min EL1: TRACE_STREAM_IRQ
S3_5_c15_c3_0 at min EL1: TRACE_AUX_CTL
S3_5_c15_c3_1 at min EL1: IPI_CR
S3_5_c15_c3_2 at min EL1: UTRIG_EVENT
S3_5_c15_c3_4 at min EL1: TRACE_CTL
S3_5_c15_c3_5 at min EL1: TRACE_DAT
S3_5_c15_c4_0 at min EL1: CPU_CFG
S3_5_c15_c4_1 at min EL1: PBLK_STS
S3_5_c15_c5_0 at min EL1: CPU_OVRD
S3_5_c15_c5_2 at min EL1: PBLK_EXE_ST
S3_5_c15_c6_0 at min EL1: ACC_OVRD
S3_5_c15_c6_2 at min EL1: CPM_PWRDN_CTL
S3_5_c15_c7_0 at min EL1: PRE_LLCFLUSH_TMR
S3_5_c15_c8_0 at min EL1: PRE_TD_TMR
S3_5_c15_c8_1 at min EL1: ACC_SLP_WAKE_UP_TMR
S3_5_c15_c9_0 at min EL1: PBLK_PSW_DLY
S3_5_c1_c0_0 at min EL2: SCTLR_EL12
S3_5_c1_c0_1 at min EL2: ACTLR_EL12
S3_5_c1_c0_2 at min EL2: CPACR_EL12
S3_5_c2_c0_0 at min EL2: TTBR0_EL12
S3_5_c2_c0_1 at min EL2: TTBR1_EL12
S3_5_c2_c0_2 at min EL2: TCR_EL12
S3_5_c4_c0_0 at min EL2: SPSR_EL12
S3_5_c4_c0_1 at min EL2: ELR_EL12
S3_5_c5_c1_0 at min EL2: AFSR0_EL12
S3_5_c5_c1_1 at min EL2: AFSR1_EL12
S3_5_c5_c2_0 at min EL2: ESR_EL12
S3_5_c6_c0_0 at min EL2: FAR_EL12
S3_6_c10_c2_0 at min EL3: MAIR_EL3
S3_6_c10_c3_0 at min EL3: AMAIR_EL3
S3_6_c12_c0_0 at min EL3: VBAR_EL3
S3_6_c12_c0_1 at min EL3: RVBAR_EL3
S3_6_c12_c0_2 at min EL3: RMR_EL3
S3_6_c13_c0_2 at min EL3: TPIDR_EL3
S3_6_c15_c0_0 at min EL1: MMU_ERR_STS
S3_6_c15_c0_1 at min EL1: AFSR1_GL1
S3_6_c15_c0_1 at min EL1: AFSR1_GL21
S3_6_c15_c0_2 at min EL2: AFSR1_GL2
S3_6_c15_c0_3 at min EL2: AFSR1_GL12
S3_6_c15_c0_4 at min EL1: BP_OBJC_ADR_EL1
S3_6_c15_c0_5 at min EL1: BP_OBJC_CTL_EL1
S3_6_c15_c0_6 at min EL1: SP_GL11
S3_6_c15_c0_6 at min EL1: SP_GL11_GL21
S3_6_c15_c0_7 at min EL2: MMU_SESR_EL2
S3_6_c15_c10_0 at min EL1: SP_GL1
S3_6_c15_c10_1 at min EL1: TPIDR_GL1
S3_6_c15_c10_2 at min EL1: VBAR_GL1
S3_6_c15_c10_2 at min EL1: VBAR_GL21
S3_6_c15_c10_3 at min EL1: SPSR_GL1
S3_6_c15_c10_3 at min EL1: SPSR_GL21
S3_6_c15_c10_4 at min EL1: ASPSR_GL1
S3_6_c15_c10_4 at min EL1: ASPSR_GL21
S3_6_c15_c10_5 at min EL1: ESR_GL1
S3_6_c15_c10_5 at min EL1: ESR_GL21
S3_6_c15_c10_6 at min EL1: ELR_GL1
S3_6_c15_c10_6 at min EL1: ELR_GL21
S3_6_c15_c10_7 at min EL1: FAR_GL1
S3_6_c15_c10_7 at min EL1: FAR_GL21
S3_6_c15_c11_0 at min EL2: SP_GL2
S3_6_c15_c11_1 at min EL2: TPIDR_GL2
S3_6_c15_c11_2 at min EL2: VBAR_GL2
S3_6_c15_c11_3 at min EL2: SPSR_GL2
S3_6_c15_c11_4 at min EL2: ASPSR_GL2
S3_6_c15_c11_5 at min EL2: ESR_GL2
S3_6_c15_c11_6 at min EL2: ELR_GL2
S3_6_c15_c11_7 at min EL2: FAR_GL2
S3_6_c15_c12_0 at min EL2: GXF_ENTRY_EL2
S3_6_c15_c12_1 at min EL2: GXF_PABENTRY_EL2
S3_6_c15_c12_2 at min EL2: APCTL_EL2
S3_6_c15_c12_3 at min EL2: APSTS_EL2
S3_6_c15_c12_4 at min EL1: APSTS_EL1
S3_6_c15_c12_4 at min EL1: APSTS_EL21
S3_6_c15_c12_5 at min EL1: KERNKEYLo_NV_EL21
S3_6_c15_c12_5 at min EL2: KERNKEYLo_EL2
S3_6_c15_c12_6 at min EL1: KERNKEYHi_NV_EL21
S3_6_c15_c12_6 at min EL2: KERNKEYHi_EL2
S3_6_c15_c12_7 at min EL2: ASPSR_EL12
S3_6_c15_c13_0 at min EL1: APIAKeyLo_NV_EL21
S3_6_c15_c13_0 at min EL2: APIAKeyLo_EL2
S3_6_c15_c13_1 at min EL1: APIAKeyHi_NV_EL21
S3_6_c15_c13_1 at min EL2: APIAKeyHi_EL2
S3_6_c15_c13_2 at min EL1: APIBKeyLo_NV_EL21
S3_6_c15_c13_2 at min EL2: APIBKeyLo_EL2
S3_6_c15_c13_3 at min EL1: APIBKeyHi_NV_EL21
S3_6_c15_c13_3 at min EL2: APIBKeyHi_EL2
S3_6_c15_c13_4 at min EL1: APDAKeyLo_NV_EL21
S3_6_c15_c13_4 at min EL2: APDAKeyLo_EL2
S3_6_c15_c13_5 at min EL1: APDAKeyHi_NV_EL21
S3_6_c15_c13_5 at min EL2: APDAKeyHi_EL2
S3_6_c15_c13_6 at min EL1: APDBKeyLo_NV_EL21
S3_6_c15_c13_6 at min EL2: APDBKeyLo_EL2
S3_6_c15_c13_7 at min EL1: APDBKeyHi_NV_EL21
S3_6_c15_c13_7 at min EL2: APDBKeyHi_EL2
S3_6_c15_c14_0 at min EL1: APGAKeyLo_NV_EL21
S3_6_c15_c14_0 at min EL2: APGAKeyLo_EL2
S3_6_c15_c14_1 at min EL1: APGAKeyHi_NV_EL21
S3_6_c15_c14_1 at min EL2: APGAKeyHi_EL2
S3_6_c15_c14_2 at min EL2: SPRR_CONFIG_EL2
S3_6_c15_c14_3 at min EL2: SPRR_AMRANGE_EL2
S3_6_c15_c14_4 at min EL2: VMKEYLo_EL2
S3_6_c15_c14_5 at min EL2: VMKEYHi_EL2
S3_6_c15_c14_6 at min EL2: MMU_SFAR_EL2
S3_6_c15_c14_7 at min EL2: APSTS_EL12
S3_6_c15_c15_0 at min EL2: APCTL_EL12
S3_6_c15_c15_1 at min EL2: GXF_CONFIG_EL12
S3_6_c15_c15_2 at min EL2: GXF_ENTRY_EL12
S3_6_c15_c15_3 at min EL2: GXF_PABENTRY_EL12
S3_6_c15_c15_4 at min EL2: SPRR_CONFIG_EL12
S3_6_c15_c15_5 at min EL2: SPRR_AMRANGE_EL12
S3_6_c15_c15_6 at min EL2: MMU_SESR_CTL_EL2
S3_6_c15_c15_7 at min EL2: SPRR_PPERM_EL12
S3_6_c15_c1_0 at min EL1: SPRR_CONFIG_EL1
S3_6_c15_c1_0 at min EL1: SPRR_CONFIG_EL21
S3_6_c15_c1_1 at min EL2: HPFAR_GL2
S3_6_c15_c1_2 at min EL1: GXF_CONFIG_EL1
S3_6_c15_c1_2 at min EL1: GXF_CONFIG_EL21
S3_6_c15_c1_3 at min EL1: AMRANGE_EL21
S3_6_c15_c1_3 at min EL1: SPRR_AMRANGE_EL1
S3_6_c15_c1_4 at min EL2: GXF_CONFIG_EL2
S3_6_c15_c1_5 at min EL1: SPRR_UPERM_EL0
S3_6_c15_c1_5 at min EL1: SPRR_UPERM_EL02
S3_6_c15_c1_6 at min EL1: SPRR_PPERM_EL1
S3_6_c15_c1_6 at min EL1: SPRR_PPERM_EL21
S3_6_c15_c1_7 at min EL2: SPRR_PPERM_EL2
S3_6_c15_c2_1 at min EL2: APGAKeyLo_EL12
S3_6_c15_c2_2 at min EL2: APGAKeyHi_EL12
S3_6_c15_c2_3 at min EL2: KERNKEYLo_EL12
S3_6_c15_c2_4 at min EL2: KERNKEYHi_EL12
S3_6_c15_c2_5 at min EL1: AFPCR_EL0
S3_6_c15_c2_6 at min EL2: SP_GL22
S3_6_c15_c2_7 at min EL1: AMXIDR_EL1
S3_6_c15_c3_0 at min EL1: SPRR_HUMPRR_EL21
S3_6_c15_c3_0 at min EL1: SPRR_UMPRR_EL1
S3_6_c15_c3_1 at min EL1: SPRR_PMPRR_EL1
S3_6_c15_c3_1 at min EL1: SPRR_PMPRR_EL21
S3_6_c15_c3_2 at min EL2: SPRR_PMPRR_EL2
S3_6_c15_c3_3 at min EL1: SPRR_HUPERM_SH01_EL21
S3_6_c15_c3_3 at min EL1: SPRR_UPERM_SH01_EL1
S3_6_c15_c3_4 at min EL1: SPRR_HUPERM_SH02_EL21
S3_6_c15_c3_4 at min EL1: SPRR_UPERM_SH02_EL1
S3_6_c15_c3_5 at min EL1: SPRR_HUPERM_SH03_EL21
S3_6_c15_c3_5 at min EL1: SPRR_UPERM_SH03_EL1
S3_6_c15_c3_6 at min EL1: SPRR_HUPERM_SH04_EL21
S3_6_c15_c3_6 at min EL1: SPRR_UPERM_SH04_EL1
S3_6_c15_c3_7 at min EL1: SPRR_HUPERM_SH05_EL21
S3_6_c15_c3_7 at min EL1: SPRR_UPERM_SH05_EL1
S3_6_c15_c4_0 at min EL1: SPRR_HUPERM_SH06_EL21
S3_6_c15_c4_0 at min EL1: SPRR_UPERM_SH06_EL1
S3_6_c15_c4_1 at min EL1: SPRR_HUPERM_SH07_EL21
S3_6_c15_c4_1 at min EL1: SPRR_UPERM_SH07_EL1
S3_6_c15_c4_2 at min EL1: SPRR_PPERM_SH01_EL1
S3_6_c15_c4_2 at min EL1: SPRR_PPERM_SH01_EL21
S3_6_c15_c4_3 at min EL1: SPRR_PPERM_SH02_EL1
S3_6_c15_c4_3 at min EL1: SPRR_PPERM_SH02_EL21
S3_6_c15_c4_4 at min EL1: SPRR_PPERM_SH03_EL1
S3_6_c15_c4_4 at min EL1: SPRR_PPERM_SH03_EL21
S3_6_c15_c4_5 at min EL1: SPRR_PPERM_SH04_EL1
S3_6_c15_c4_5 at min EL1: SPRR_PPERM_SH04_EL21
S3_6_c15_c4_6 at min EL1: SPRR_PPERM_SH05_EL1
S3_6_c15_c4_6 at min EL1: SPRR_PPERM_SH05_EL21
S3_6_c15_c4_7 at min EL1: SPRR_PPERM_SH06_EL1
S3_6_c15_c4_7 at min EL1: SPRR_PPERM_SH06_EL21
S3_6_c15_c5_0 at min EL1: SPRR_PPERM_SH07_EL1
S3_6_c15_c5_0 at min EL1: SPRR_PPERM_SH07_EL21
S3_6_c15_c5_1 at min EL2: SPRR_PPERM_SH01_EL2
S3_6_c15_c5_2 at min EL2: SPRR_PPERM_SH02_EL2
S3_6_c15_c5_3 at min EL2: SPRR_PPERM_SH03_EL2
S3_6_c15_c5_4 at min EL2: SPRR_PPERM_SH04_EL2
S3_6_c15_c5_5 at min EL2: SPRR_PPERM_SH05_EL2
S3_6_c15_c5_6 at min EL2: SPRR_PPERM_SH06_EL2
S3_6_c15_c5_7 at min EL2: SPRR_PPERM_SH07_EL2
S3_6_c15_c6_0 at min EL2: SPRR_PMPRR_EL12
S3_6_c15_c6_1 at min EL2: SPRR_PPERM_SH01_EL12
S3_6_c15_c6_2 at min EL2: SPRR_PPERM_SH02_EL12
S3_6_c15_c6_3 at min EL2: SPRR_PPERM_SH03_EL12
S3_6_c15_c6_4 at min EL2: SPRR_PPERM_SH04_EL12
S3_6_c15_c6_5 at min EL2: SPRR_PPERM_SH05_EL12
S3_6_c15_c6_6 at min EL2: SPRR_PPERM_SH06_EL12
S3_6_c15_c6_7 at min EL2: SPRR_PPERM_SH07_EL12
S3_6_c15_c7_0 at min EL2: APIAKeyLo_EL12
S3_6_c15_c7_1 at min EL2: APIAKeyHi_EL12
S3_6_c15_c7_2 at min EL2: APIBKeyLo_EL12
S3_6_c15_c7_3 at min EL2: APIBKeyHi_EL12
S3_6_c15_c7_4 at min EL2: APDAKeyLo_EL12
S3_6_c15_c7_5 at min EL2: APDAKeyHi_EL12
S3_6_c15_c7_6 at min EL2: APDBKeyLo_EL12
S3_6_c15_c7_7 at min EL2: APDBKeyHi_EL12
S3_6_c15_c8_0 at min EL1: CurrentG
S3_6_c15_c8_1 at min EL1: GXF_ENTRY_EL1
S3_6_c15_c8_1 at min EL1: GXF_ENTRY_EL21
S3_6_c15_c8_2 at min EL1: GXF_PABENTRY_EL1
S3_6_c15_c8_2 at min EL1: GXF_PABENTRY_EL21
S3_6_c15_c8_3 at min EL1: ASPSR_EL1
S3_6_c15_c8_3 at min EL1: ASPSR_EL21
S3_6_c15_c8_4 at min EL1: ADSPSR_EL0
S3_6_c15_c8_5 at min EL2: PMCR1_GL2
S3_6_c15_c8_6 at min EL1: ASPSR_NV_EL21
S3_6_c15_c8_6 at min EL2: ASPSR_EL2
S3_6_c15_c8_7 at min EL1: PMCR1_GL1
S3_6_c15_c8_7 at min EL1: PMCR1_GL21
S3_6_c15_c9_2 at min EL2: VBAR_GL12
S3_6_c15_c9_3 at min EL2: SPSR_GL12
S3_6_c15_c9_4 at min EL2: ASPSR_GL12
S3_6_c15_c9_5 at min EL2: ESR_GL12
S3_6_c15_c9_6 at min EL2: ELR_GL12
S3_6_c15_c9_7 at min EL2: FAR_GL12
S3_6_c1_c0_0 at min EL3: SCTLR_EL3
S3_6_c1_c0_1 at min EL3: ACTLR_EL3
S3_6_c1_c1_0 at min EL3: SCR_EL3
S3_6_c1_c1_1 at min EL3: SDER32_EL3
S3_6_c1_c1_2 at min EL3: CPTR_EL3
S3_6_c1_c3_1 at min EL3: MDCR_EL3
S3_6_c2_c0_0 at min EL3: TTBR0_EL3
S3_6_c2_c0_2 at min EL3: TCR_EL3
S3_6_c4_c0_0 at min EL3: SPSR_EL3
S3_6_c4_c0_1 at min EL3: ELR_EL3
S3_6_c4_c1_0 at min EL2: SP_EL2
S3_6_c5_c1_0 at min EL3: AFSR0_EL3
S3_6_c5_c1_1 at min EL3: AFSR1_EL3
S3_6_c5_c2_0 at min EL3: ESR_EL3
S3_6_c6_c0_0 at min EL3: FAR_EL3
S3_7_c14_c2_0 at min EL1: CNTPS_TVAL_EL1
S3_7_c14_c2_1 at min EL1: CNTPS_CTL_EL1
S3_7_c14_c2_2 at min EL1: CNTPS_CVAL_EL1
S3_7_c15_c0_0 at min EL1: PWRDNSAVE0
S3_7_c15_c0_1 at min EL1: NRG_ACC_CTL
S3_7_c15_c0_2 at min EL1: AON_CNT0
S3_7_c15_c0_3 at min EL1: CPU_CNT0
S3_7_c15_c0_4 at min EL1: UPMCR0_EL1
S3_7_c15_c0_5 at min EL1: UPMC8
S3_7_c15_c10_2 at min EL1: AON_CNT5
S3_7_c15_c10_3 at min EL1: CPU_CNT5
S3_7_c15_c10_4 at min EL1: UPMC3
S3_7_c15_c10_5 at min EL1: UPMCR1_EL1
S3_7_c15_c11_2 at min EL1: AON_CNT_CTL5
S3_7_c15_c11_3 at min EL1: CPU_CNT_CTL5
S3_7_c15_c11_4 at min EL1: UPMC4
S3_7_c15_c11_5 at min EL1: UPMESR1_EL1
S3_7_c15_c12_2 at min EL1: AON_CNT6
S3_7_c15_c12_3 at min EL1: CPU_CNT6
S3_7_c15_c12_4 at min EL1: UPMC5
S3_7_c15_c13_2 at min EL1: AON_CNT_CTL6
S3_7_c15_c13_3 at min EL1: CPU_CNT_CTL6
S3_7_c15_c13_4 at min EL1: UPMC6
S3_7_c15_c14_2 at min EL1: AON_CNT7
S3_7_c15_c14_3 at min EL1: CPU_CNT7
S3_7_c15_c14_4 at min EL1: UPMC7
S3_7_c15_c15_2 at min EL1: AON_CNT_CTL7
S3_7_c15_c15_3 at min EL1: CPU_CNT_CTL7
S3_7_c15_c1_0 at min EL1: PWRDNSAVE1
S3_7_c15_c1_1 at min EL1: CORE_NRG_ACC_DAT
S3_7_c15_c1_2 at min EL1: AON_CNT_CTL0
S3_7_c15_c1_3 at min EL1: CPU_CNT_CTL0
S3_7_c15_c1_4 at min EL1: UPMESR0_EL1
S3_7_c15_c1_5 at min EL1: UPMC9
S3_7_c15_c2_0 at min EL1: ACC_PWR_DN_SAVE
S3_7_c15_c2_1 at min EL1: CPM_NRG_ACC_DAT
S3_7_c15_c2_2 at min EL1: AON_CNT1
S3_7_c15_c2_3 at min EL1: CPU_CNT1
S3_7_c15_c2_4 at min EL1: UPMSWCTRL_EL1
S3_7_c15_c2_5 at min EL1: UPMC10
S3_7_c15_c3_1 at min EL1: CORE_SRM_NRG_ACC_DAT
S3_7_c15_c3_2 at min EL1: AON_CNT_CTL1
S3_7_c15_c3_3 at min EL1: CPU_CNT_CTL1
S3_7_c15_c3_4 at min EL1: UPMECM0_EL1
S3_7_c15_c3_5 at min EL1: UPMC11
S3_7_c15_c4_0 at min EL1: AON_CNT_CTL
S3_7_c15_c4_1 at min EL1: CPM_SRM_NRG_ACC_DAT
S3_7_c15_c4_2 at min EL1: AON_CNT2
S3_7_c15_c4_3 at min EL1: CPU_CNT2
S3_7_c15_c4_4 at min EL1: UPMECM1_EL1
S3_7_c15_c4_5 at min EL1: UPMC12
S3_7_c15_c5_0 at min EL1: CPU_CNT_CTL
S3_7_c15_c5_2 at min EL1: AON_CNT_CTL2
S3_7_c15_c5_3 at min EL1: CPU_CNT_CTL2
S3_7_c15_c5_4 at min EL1: UPMPCM_EL1
S3_7_c15_c5_5 at min EL1: UPMC13
S3_7_c15_c6_2 at min EL1: AON_CNT3
S3_7_c15_c6_3 at min EL1: CPU_CNT3
S3_7_c15_c6_4 at min EL1: UPMSR_EL1
S3_7_c15_c6_5 at min EL1: UPMC14
S3_7_c15_c7_2 at min EL1: AON_CNT_CTL3
S3_7_c15_c7_3 at min EL1: CPU_CNT_CTL3
S3_7_c15_c7_4 at min EL1: UPMC0
S3_7_c15_c7_5 at min EL1: UPMC15
S3_7_c15_c8_2 at min EL1: AON_CNT4
S3_7_c15_c8_3 at min EL1: CPU_CNT4
S3_7_c15_c8_4 at min EL1: UPMC1
S3_7_c15_c8_5 at min EL1: UPMECM2_EL1
S3_7_c15_c9_2 at min EL1: AON_CNT_CTL4
S3_7_c15_c9_3 at min EL1: CPU_CNT_CTL4
S3_7_c15_c9_4 at min EL1: UPMC2
S3_7_c15_c9_5 at min EL1: UPMECM3_EL1