counter 2

gistfile1.v

reg enable;
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        count <= max_count;
    end
    else if (enable) begin // enable = 1'b1 の時のみカウント動作
        else if (count == 0) begin
            count <= max_count;
        end
        else begin
            count <= count - 1;
        end
    end
end