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@jz5
Created December 3, 2013 03:07
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counter 2
reg enable;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
count <= max_count;
end
else if (enable) begin // enable = 1'b1 の時のみカウント動作
else if (count == 0) begin
count <= max_count;
end
else begin
count <= count - 1;
end
end
end
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