Skip to content

Instantly share code, notes, and snippets.

@jz5
Created December 3, 2013 03:08
Embed
What would you like to do?
counter enable
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
enable <= 1'b0;
end
else if (start) begin
enable <= 1'b1;
end
else if (finish) begin
enable <= 1'b0;
end
end
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment