train for making basic testbench

top_level.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity top_level is
    port(
        A, B : in std_logic := 'X';
        C : out std_logic := 'X'
    );
end entity;

architecture IMP of top_level is
begin

    C <= A and B;

end architecture;

top_level.vht

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY top_level_vhd_tst IS
END top_level_vhd_tst;

ARCHITECTURE top_level_arch OF top_level_vhd_tst IS

    -- signals
    SIGNAL A : STD_LOGIC;
    SIGNAL B : STD_LOGIC;
    SIGNAL C : STD_LOGIC;
    COMPONENT top_level
        PORT (
        A : IN STD_LOGIC;
        B : IN STD_LOGIC;
        C : OUT STD_LOGIC
        );
    END COMPONENT;

BEGIN
    i1 : top_level
    PORT MAP (
        A => A,
        B => B,
        C => C
    );

    test : process
    begin
        wait for 40 ns; assert C = '1' report "#1";
        wait for 30 ns; assert C = '1' report "#2";
        wait for 20 ns; assert C = '1' report "#3";
        wait for 10 ns;
        report "simulation end" severity failure;
    wait;
    end process;

    process
    begin
        A <= '0';
        wait for 20 ns; A <= '1';
        wait for 25 ns; A <= '0';
        wait for 10 ns; A <= '1';
        wait;
    end process;

    process
    begin
        B <= '0';
        wait for 35 ns; B <= '1';
        wait for 55 ns; B <= '0';
        wait;
    end process;

END top_level_arch;