TD4 implemented by VHDL (work in progress...)

td4.vhd

-- td4.vhd

-- This file was auto-generated as a prototype implementation of a module
-- created in component editor.  It ties off all outputs to ground and
-- ignores all inputs.  It needs to be edited to make it do something
-- useful.
-- 
-- This file will not be automatically regenerated.  You should check it in
-- to your version control system if you want to keep it.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity td4 is
	port (
		avs_s0_address     : in  std_logic                     := '0';             --    s0.address
		avs_s0_read        : in  std_logic                     := '0';             --      .read
		avs_s0_readdata    : out std_logic_vector(31 downto 0);                    --      .readdata
		avs_s0_writedata   : in  std_logic_vector(31 downto 0) := (others => '0'); --      .writedata
		avs_s0_waitrequest : out std_logic;                                        --      .waitrequest
		avs_s0_write       : in  std_logic                     := '0';             --      .write
		clk                : in  std_logic                     := '0';             -- clock.clk
		reset              : in  std_logic                     := '0'              -- reset.reset
	);
end entity td4;


architecture rtl of td4 is

signal reg_A : std_logic_vector(3 downto 0) := "1010";
signal reg_B : std_logic_vector(3 downto 0) := "0101";

begin

	-- TODO: Auto-generated HDL template

	avs_s0_waitrequest <= '0';

    process (all)
    begin
    
    case avs_s0_address is
        when '0' => avs_s0_readdata <= ("0000000000000000000000000000" & reg_A);
        when '1' => avs_s0_readdata <= ("0000000000000000000000000000" & reg_B);
        when others => avs_s0_readdata <= (others => '1');
    end case;
    
    end process;
end architecture rtl; -- of td4

I have that book. Got it many years ago in Japan. Thinking of doing something like that in VHDL finally. I also have a half done project of wiring that too.(I should probably finish that too)