Intel ValleyView on Haiku

intel-valleyview.diff

diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h
index 1703898..c1d1166 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -39,6 +39,7 @@
 #define INTEL_TYPE_ILK			(INTEL_TYPE_9xx | 0x1000)
 #define INTEL_TYPE_SNB			(INTEL_TYPE_9xx | 0x2000)
 #define INTEL_TYPE_IVB			(INTEL_TYPE_9xx | 0x4000)
+#define INTEL_TYPE_VLV			(INTEL_TYPE_9xx | 0x8000)
 // models
 #define INTEL_TYPE_SERVER		0x0004
 #define INTEL_TYPE_MOBILE		0x0008
@@ -61,6 +62,11 @@
 #define INTEL_TYPE_IVBG			(INTEL_TYPE_IVB)
 #define INTEL_TYPE_IVBGM		(INTEL_TYPE_IVB | INTEL_TYPE_MOBILE)
 #define INTEL_TYPE_IVBGS		(INTEL_TYPE_IVB | INTEL_TYPE_SERVER)
+#define INTEL_TYPE_VLVG			(INTEL_TYPE_VLV)
+#define INTEL_TYPE_VLVGM		(INTEL_TYPE_VLV | INTEL_TYPE_MOBILE)
+
+// ValleyView MMIO is offset
+#define VLV_DISPLAY_BASE		0x180000
 
 #define DEVICE_NAME				"intel_extreme"
 #define INTEL_ACCELERANT_NAME	"intel_extreme.accelerant"
@@ -131,7 +137,7 @@ struct DeviceType {
 	bool HasPlatformControlHub() const
 	{
 		return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB)
-			|| InGroup(INTEL_TYPE_IVB);
+			|| InGroup(INTEL_TYPE_IVB) || InGroup(INTEL_TYPE_VLV);
 	}
 };
 
@@ -368,7 +374,6 @@ struct intel_free_graphics_memory {
 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
 
 // display ports
-#define INTEL_DISPLAY_A_ANALOG_PORT		(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
 #define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
 #define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
 #define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
@@ -380,9 +385,6 @@ struct intel_free_graphics_memory {
 #define DISPLAY_MONITOR_POLARITY_MASK	(3UL << 3)
 #define DISPLAY_MONITOR_POSITIVE_HSYNC	(1UL << 3)
 #define DISPLAY_MONITOR_POSITIVE_VSYNC	(2UL << 3)
-#define INTEL_DISPLAY_A_DIGITAL_PORT	(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
-#define INTEL_DISPLAY_C_DIGITAL			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
-#define INTEL_DISPLAY_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
 #define LVDS_POST2_RATE_SLOW			14 // PLL Divisors
 #define LVDS_POST2_RATE_FAST			7
 #define LVDS_CLKB_POWER_MASK			(3 << 4)
@@ -436,7 +438,11 @@ struct intel_free_graphics_memory {
 #define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
 #define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)
 
+#define INTEL_DISPLAY_A_ANALOG_PORT		(0x1100 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_A_DIGITAL_PORT	(0x1120 | REGS_SOUTH_TRANSCODER_PORT)
 #define INTEL_DISPLAY_B_DIGITAL_PORT	(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_C_DIGITAL			(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_LVDS_PORT			(0x1180 | REGS_SOUTH_TRANSCODER_PORT)
 
 // planes
 #define INTEL_DISPLAY_A_PIPE_CONTROL	(0x0008 | REGS_NORTH_PLANE_CONTROL)
diff --git a/src/add-ons/accelerants/intel_extreme/hooks.cpp b/src/add-ons/accelerants/intel_extreme/hooks.cpp
index e97a8d7..975551b 100644
--- a/src/add-ons/accelerants/intel_extreme/hooks.cpp
+++ b/src/add-ons/accelerants/intel_extreme/hooks.cpp
@@ -118,7 +118,8 @@ get_accelerant_hook(uint32 feature, void* data)
 				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)
 				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
 				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB))
+				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
+				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV))
 				return NULL;
 
 			return (void*)intel_allocate_overlay_buffer;
diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp
index ca9b522..8f61573 100755
--- a/src/add-ons/accelerants/intel_extreme/mode.cpp
+++ b/src/add-ons/accelerants/intel_extreme/mode.cpp
@@ -140,7 +140,8 @@ get_pll_limits(pll_limits &limits)
 
 	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
 		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
-		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)) {
+		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
+		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV)) {
 		// TODO: support LVDS output limits as well
 		static const pll_limits kLimits = {
 			// p, p1, p2, high,   n,   m, m1, m2
@@ -565,7 +566,8 @@ set_frame_buffer_base()
 		|| sharedInfo.device_type.InGroup(INTEL_TYPE_G4x)
 		|| sharedInfo.device_type.InGroup(INTEL_TYPE_ILK)
 		|| sharedInfo.device_type.InGroup(INTEL_TYPE_SNB)
-		|| sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)) {
+		|| sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)
+		|| sharedInfo.device_type.InGroup(INTEL_TYPE_VLV)) {
 		write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
 			+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
 		read32(baseRegister);
diff --git a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
index 4618721..f9bc499 100644
--- a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
+++ b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
@@ -1,6 +1,14 @@
 /*
  * Copyright 2008-2010, Axel Dörfler, axeld@pinc-software.de.
+ * Copyright 2011-2015, Haiku, Inc. All Rights Reserved.
  * Distributed under the terms of the MIT License.
+ *
+ * Authors:
+ *		Axel Dörfler, axeld@pinc-software.de
+ *		Jerome Duval, jerome.duval@gmail.com
+ *		Adrien Destugues, pulkomandy@gmail.com
+ *		Michael Lotz, mmlr@mlotz.ch
+ *		Alexander von Gluck IV, kallisti5@unixzen.com
  */
 
 
@@ -16,7 +24,7 @@
 
 //#define TRACE_INTEL
 #ifdef TRACE_INTEL
-#	define TRACE(x...) dprintf("\33[33magp-intel:\33[0m " x)
+#	define TRACE(x...) dprintf("\33[33mgart-intel:\33[0m " x)
 #else
 #	define TRACE(x...) ;
 #endif
@@ -104,6 +112,14 @@ const struct supported_device {
 	{0x0c00, 0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
 	{0x0c04, 0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
 	{0x0d04, 0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
+
+	// XXX: 0x0f00 only confirmed on 0x0f30, 0x0f31
+	{0x0f00, 0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
+	{0x0f00, 0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f00, 0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f00, 0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f00, 0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f00, 0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
 };
 
 struct intel_info {
@@ -387,11 +403,18 @@ intel_map(intel_info &info)
 		fbIndex = 2;
 	}
 
+	phys_addr_t mmioOffset = 0;
+
+	// If ValleyView (VLV) the mmio is offset
+	if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_VLV)
+		mmioOffset = VLV_DISPLAY_BASE;
+
 	AreaKeeper mmioMapper;
 	info.registers_area = mmioMapper.Map("intel GMCH mmio",
-		info.display.u.h0.base_registers[mmioIndex],
-		info.display.u.h0.base_register_sizes[mmioIndex], B_ANY_KERNEL_ADDRESS,
-		B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers);
+		info.display.u.h0.base_registers[mmioIndex] + mmioOffset,
+		info.display.u.h0.base_register_sizes[mmioIndex] - mmioOffset,
+		B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
+		(void**)&info.registers);
 	if (mmioMapper.InitCheck() < B_OK) {
 		dprintf("agp_intel: could not map memory I/O!\n");
 		return info.registers_area;
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
index d9f62fb..22dd3f0 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
@@ -100,6 +100,13 @@ const struct supported_device {
 	{0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
 	{0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
 	{0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
+
+	{0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
+	{0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
 };
 
 int32 api_version = B_CUR_DRIVER_API_VERSION;
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
index 204d52c..0e1028a 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
@@ -4,6 +4,7 @@
  *
  * Authors:
  *		Axel Dörfler, axeld@pinc-software.de
+ *		Alexander von Gluck IV, kallisti5@unixzen.com
  */
 
 
@@ -300,13 +301,19 @@ intel_extreme_init(intel_info &info)
 
 	// memory mapped I/O
 
+	phys_addr_t mmioOffset = 0;
+
+	// If ValleyView (VLV) the mmio is offset
+	if (info.device_type.InFamily(INTEL_TYPE_VLV))
+		mmioOffset = VLV_DISPLAY_BASE;
+
 	// TODO: registers are mapped twice (by us and intel_gart), maybe we
 	// can share it between the drivers
 
 	AreaKeeper mmioMapper;
 	info.registers_area = mmioMapper.Map("intel extreme mmio",
-		info.pci->u.h0.base_registers[mmioIndex],
-		info.pci->u.h0.base_register_sizes[mmioIndex],
+		info.pci->u.h0.base_registers[mmioIndex] + mmioOffset,
+		info.pci->u.h0.base_register_sizes[mmioIndex] - mmioOffset,
 		B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
 		(void**)&info.registers);
 	if (mmioMapper.InitCheck() < B_OK) {
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
index 9c4f6c7..904992a 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
@@ -37,6 +37,10 @@ intel_en_gating(intel_info &info)
 	} else if (info.device_type.InGroup(INTEL_TYPE_IVB)) {
 		TRACE("IvyBridge clock gating\n");
 		write32(info, 0x42020, (1L << 28));
+	} else if (info.device_type.InGroup(INTEL_TYPE_VLV)) {
+		// TODO: Confirm same as IvyBridge
+		TRACE("ValleyView clock gating\n");
+		write32(info, 0x42020, (1L << 28));
 	} else if (info.device_type.InGroup(INTEL_TYPE_ILK)) {
 		TRACE("IronLake clock gating\n");
 		write32(info, 0x42020, (1L << 7) | (1L << 5));
@@ -172,4 +176,4 @@ intel_en_downclock(intel_info &info)
 	write32(info, INTEL6_PMINTRMSK, 0);
 
 	return B_OK;
-}
\ No newline at end of file
+}