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OnePlus 6T FDT
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| /dts-v1/; | |
| / { | |
| interrupt-parent = <0x01>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| model = "OnePlus 6T"; | |
| compatible = "oneplus,fajita\0qcom,sdm845"; | |
| aliases { | |
| i2c0 = "/soc@0/geniqup@8c0000/i2c@880000"; | |
| i2c1 = "/soc@0/geniqup@8c0000/i2c@884000"; | |
| i2c2 = "/soc@0/geniqup@8c0000/i2c@888000"; | |
| i2c3 = "/soc@0/geniqup@8c0000/i2c@88c000"; | |
| i2c4 = "/soc@0/geniqup@8c0000/i2c@890000"; | |
| i2c5 = "/soc@0/geniqup@8c0000/i2c@894000"; | |
| i2c6 = "/soc@0/geniqup@8c0000/i2c@898000"; | |
| i2c7 = "/soc@0/geniqup@8c0000/i2c@89c000"; | |
| i2c8 = "/soc@0/geniqup@ac0000/i2c@a80000"; | |
| i2c9 = "/soc@0/geniqup@ac0000/i2c@a84000"; | |
| i2c10 = "/soc@0/geniqup@ac0000/i2c@a88000"; | |
| i2c11 = "/soc@0/geniqup@ac0000/i2c@a8c000"; | |
| i2c12 = "/soc@0/geniqup@ac0000/i2c@a90000"; | |
| i2c13 = "/soc@0/geniqup@ac0000/i2c@a94000"; | |
| i2c14 = "/soc@0/geniqup@ac0000/i2c@a98000"; | |
| i2c15 = "/soc@0/geniqup@ac0000/i2c@a9c000"; | |
| spi0 = "/soc@0/geniqup@8c0000/spi@880000"; | |
| spi1 = "/soc@0/geniqup@8c0000/spi@884000"; | |
| spi2 = "/soc@0/geniqup@8c0000/spi@888000"; | |
| spi3 = "/soc@0/geniqup@8c0000/spi@88c000"; | |
| spi4 = "/soc@0/geniqup@8c0000/spi@890000"; | |
| spi5 = "/soc@0/geniqup@8c0000/spi@894000"; | |
| spi6 = "/soc@0/geniqup@8c0000/spi@898000"; | |
| spi7 = "/soc@0/geniqup@8c0000/spi@89c000"; | |
| spi8 = "/soc@0/geniqup@ac0000/spi@a80000"; | |
| spi9 = "/soc@0/geniqup@ac0000/spi@a84000"; | |
| spi10 = "/soc@0/geniqup@ac0000/spi@a88000"; | |
| spi11 = "/soc@0/geniqup@ac0000/spi@a8c000"; | |
| spi12 = "/soc@0/geniqup@ac0000/spi@a90000"; | |
| spi13 = "/soc@0/geniqup@ac0000/spi@a94000"; | |
| spi14 = "/soc@0/geniqup@ac0000/spi@a98000"; | |
| spi15 = "/soc@0/geniqup@ac0000/spi@a9c000"; | |
| serial0 = "/soc@0/geniqup@ac0000/serial@a84000"; | |
| hsuart0 = "/soc@0/geniqup@8c0000/serial@898000"; | |
| }; | |
| chosen { | |
| stdout-path = "serial0:115200n8"; | |
| }; | |
| memory@80000000 { | |
| device_type = "memory"; | |
| reg = <0x00 0x80000000 0x00 0x00>; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| memory@85700000 { | |
| reg = <0x00 0x85700000 0x00 0x600000>; | |
| no-map; | |
| }; | |
| memory@85e00000 { | |
| reg = <0x00 0x85e00000 0x00 0x100000>; | |
| no-map; | |
| }; | |
| memory@85fc0000 { | |
| reg = <0x00 0x85fc0000 0x00 0x20000>; | |
| no-map; | |
| }; | |
| memory@85fe0000 { | |
| compatible = "qcom,cmd-db"; | |
| reg = <0x00 0x85fe0000 0x00 0x20000>; | |
| no-map; | |
| }; | |
| memory@86000000 { | |
| reg = <0x00 0x86000000 0x00 0x200000>; | |
| no-map; | |
| phandle = <0x28>; | |
| }; | |
| memory@86200000 { | |
| reg = <0x00 0x86200000 0x00 0x2d00000>; | |
| no-map; | |
| }; | |
| memory@88f00000 { | |
| reg = <0x00 0x88f00000 0x00 0x1c00000>; | |
| no-map; | |
| }; | |
| memory@8ab00000 { | |
| reg = <0x00 0x8ab00000 0x00 0x1400000>; | |
| no-map; | |
| }; | |
| memory@8bf00000 { | |
| reg = <0x00 0x8bf00000 0x00 0x500000>; | |
| no-map; | |
| }; | |
| memory@8c400000 { | |
| reg = <0x00 0x8c400000 0x00 0x100000>; | |
| no-map; | |
| phandle = <0xd9>; | |
| }; | |
| memory@8c515000 { | |
| reg = <0x00 0x8c515000 0x00 0x2000>; | |
| no-map; | |
| phandle = <0xcc>; | |
| }; | |
| memory@8c517000 { | |
| reg = <0x00 0x8c517000 0x00 0x5a000>; | |
| no-map; | |
| phandle = <0x79>; | |
| }; | |
| memory@8c600000 { | |
| reg = <0x00 0x8c600000 0x00 0x1a00000>; | |
| no-map; | |
| phandle = <0x20>; | |
| }; | |
| memory@8e000000 { | |
| reg = <0x00 0x8e000000 0x00 0x7800000>; | |
| no-map; | |
| phandle = <0x81>; | |
| }; | |
| memory@95800000 { | |
| reg = <0x00 0x95800000 0x00 0x500000>; | |
| no-map; | |
| phandle = <0xb1>; | |
| }; | |
| memory@95d00000 { | |
| reg = <0x00 0x95d00000 0x00 0x800000>; | |
| no-map; | |
| phandle = <0x25>; | |
| }; | |
| memory@96500000 { | |
| reg = <0x00 0x96500000 0x00 0x200000>; | |
| no-map; | |
| phandle = <0x80>; | |
| }; | |
| memory@96700000 { | |
| reg = <0x00 0x96700000 0x00 0x1400000>; | |
| no-map; | |
| }; | |
| memory@97b00000 { | |
| reg = <0x00 0x97b00000 0x00 0x100000>; | |
| no-map; | |
| }; | |
| memory@f5b00000 { | |
| no-map; | |
| reg = <0x00 0xf5b00000 0x00 0x1000>; | |
| }; | |
| memory@f5b01000 { | |
| compatible = "qcom,rmtfs-mem"; | |
| reg = <0x00 0xf5b01000 0x00 0x200000>; | |
| no-map; | |
| qcom,client-id = <0x01>; | |
| qcom,vmid = <0x0f>; | |
| }; | |
| memory@f5d01000 { | |
| no-map; | |
| reg = <0x00 0xf5d01000 0x00 0x1000>; | |
| }; | |
| ramoops@ac300000 { | |
| compatible = "ramoops"; | |
| reg = <0x00 0xac300000 0x00 0x400000>; | |
| record-size = <0x40000>; | |
| console-size = <0x40000>; | |
| ftrace-size = <0x40000>; | |
| pmsg-size = <0x200000>; | |
| devinfo-size = <0x1000>; | |
| ecc-size = <0x10>; | |
| }; | |
| }; | |
| cpus { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x00>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0x02 0x03 0x04>; | |
| capacity-dmips-mhz = <0x25f>; | |
| dynamic-power-coefficient = <0x64>; | |
| qcom,freq-domain = <0x05 0x00>; | |
| operating-points-v2 = <0x06>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x0a>; | |
| phandle = <0x16>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x0a>; | |
| l3-cache { | |
| compatible = "cache"; | |
| phandle = <0x0b>; | |
| }; | |
| }; | |
| }; | |
| cpu@100 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x100>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0x02 0x03 0x04>; | |
| capacity-dmips-mhz = <0x25f>; | |
| dynamic-power-coefficient = <0x64>; | |
| qcom,freq-domain = <0x05 0x00>; | |
| operating-points-v2 = <0x06>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x0c>; | |
| phandle = <0x17>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x0c>; | |
| }; | |
| }; | |
| cpu@200 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x200>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0x02 0x03 0x04>; | |
| capacity-dmips-mhz = <0x25f>; | |
| dynamic-power-coefficient = <0x64>; | |
| qcom,freq-domain = <0x05 0x00>; | |
| operating-points-v2 = <0x06>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x0d>; | |
| phandle = <0x18>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x0d>; | |
| }; | |
| }; | |
| cpu@300 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x300>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0x02 0x03 0x04>; | |
| capacity-dmips-mhz = <0x25f>; | |
| dynamic-power-coefficient = <0x64>; | |
| qcom,freq-domain = <0x05 0x00>; | |
| operating-points-v2 = <0x06>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x0e>; | |
| phandle = <0x19>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x0e>; | |
| }; | |
| }; | |
| cpu@400 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x400>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x400>; | |
| cpu-idle-states = <0x0f 0x10 0x04>; | |
| dynamic-power-coefficient = <0x18c>; | |
| qcom,freq-domain = <0x05 0x01>; | |
| operating-points-v2 = <0x11>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x12>; | |
| phandle = <0x1a>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x12>; | |
| }; | |
| }; | |
| cpu@500 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x500>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x400>; | |
| cpu-idle-states = <0x0f 0x10 0x04>; | |
| dynamic-power-coefficient = <0x18c>; | |
| qcom,freq-domain = <0x05 0x01>; | |
| operating-points-v2 = <0x11>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x13>; | |
| phandle = <0x1b>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x13>; | |
| }; | |
| }; | |
| cpu@600 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x600>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x400>; | |
| cpu-idle-states = <0x0f 0x10 0x04>; | |
| dynamic-power-coefficient = <0x18c>; | |
| qcom,freq-domain = <0x05 0x01>; | |
| operating-points-v2 = <0x11>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x14>; | |
| phandle = <0x1c>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x14>; | |
| }; | |
| }; | |
| cpu@700 { | |
| device_type = "cpu"; | |
| compatible = "qcom,kryo385"; | |
| reg = <0x00 0x700>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x400>; | |
| cpu-idle-states = <0x0f 0x10 0x04>; | |
| dynamic-power-coefficient = <0x18c>; | |
| qcom,freq-domain = <0x05 0x01>; | |
| operating-points-v2 = <0x11>; | |
| interconnects = <0x07 0x00 0x03 0x08 0x0e 0x03 0x09 0x00 0x09 0x01>; | |
| #cooling-cells = <0x02>; | |
| next-level-cache = <0x15>; | |
| phandle = <0x1d>; | |
| l2-cache { | |
| compatible = "cache"; | |
| next-level-cache = <0x0b>; | |
| phandle = <0x15>; | |
| }; | |
| }; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0x16>; | |
| }; | |
| core1 { | |
| cpu = <0x17>; | |
| }; | |
| core2 { | |
| cpu = <0x18>; | |
| }; | |
| core3 { | |
| cpu = <0x19>; | |
| }; | |
| core4 { | |
| cpu = <0x1a>; | |
| }; | |
| core5 { | |
| cpu = <0x1b>; | |
| }; | |
| core6 { | |
| cpu = <0x1c>; | |
| }; | |
| core7 { | |
| cpu = <0x1d>; | |
| }; | |
| }; | |
| }; | |
| idle-states { | |
| entry-method = "psci"; | |
| cpu-sleep-0-0 { | |
| compatible = "arm,idle-state"; | |
| idle-state-name = "little-power-down"; | |
| arm,psci-suspend-param = <0x40000003>; | |
| entry-latency-us = <0x15e>; | |
| exit-latency-us = <0x1cd>; | |
| min-residency-us = <0x762>; | |
| local-timer-stop; | |
| phandle = <0x02>; | |
| }; | |
| cpu-sleep-0-1 { | |
| compatible = "arm,idle-state"; | |
| idle-state-name = "little-rail-power-down"; | |
| arm,psci-suspend-param = <0x40000004>; | |
| entry-latency-us = <0x168>; | |
| exit-latency-us = <0x213>; | |
| min-residency-us = <0xf5e>; | |
| local-timer-stop; | |
| phandle = <0x03>; | |
| }; | |
| cpu-sleep-1-0 { | |
| compatible = "arm,idle-state"; | |
| idle-state-name = "big-power-down"; | |
| arm,psci-suspend-param = <0x40000003>; | |
| entry-latency-us = <0x108>; | |
| exit-latency-us = <0x26d>; | |
| min-residency-us = <0x3b8>; | |
| local-timer-stop; | |
| phandle = <0x0f>; | |
| }; | |
| cpu-sleep-1-1 { | |
| compatible = "arm,idle-state"; | |
| idle-state-name = "big-rail-power-down"; | |
| arm,psci-suspend-param = <0x40000004>; | |
| entry-latency-us = <0x2be>; | |
| exit-latency-us = <0x425>; | |
| min-residency-us = <0x1188>; | |
| local-timer-stop; | |
| phandle = <0x10>; | |
| }; | |
| cluster-sleep-0 { | |
| compatible = "arm,idle-state"; | |
| idle-state-name = "cluster-power-down"; | |
| arm,psci-suspend-param = <0x400000f4>; | |
| entry-latency-us = <0xcbf>; | |
| exit-latency-us = <0x19a2>; | |
| min-residency-us = <0x2703>; | |
| local-timer-stop; | |
| phandle = <0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu0_opp_table { | |
| compatible = "operating-points-v2"; | |
| opp-shared; | |
| phandle = <0x06>; | |
| opp-300000000 { | |
| opp-hz = <0x00 0x11e1a300>; | |
| opp-peak-kBps = "\0\f5\0\0I>"; | |
| }; | |
| opp-403200000 { | |
| opp-hz = <0x00 0x18085800>; | |
| opp-peak-kBps = "\0\f5\0\0I>"; | |
| }; | |
| opp-480000000 { | |
| opp-hz = <0x00 0x1c9c3800>; | |
| opp-peak-kBps = "\0\f5\0\0bp"; | |
| }; | |
| opp-576000000 { | |
| opp-hz = <0x00 0x22551000>; | |
| opp-peak-kBps = "\0\f5\0\0bp"; | |
| }; | |
| opp-652800000 { | |
| opp-hz = <0x00 0x26e8f000>; | |
| opp-peak-kBps = "\0\f5\0\0u0"; | |
| }; | |
| opp-748800000 { | |
| opp-hz = <0x00 0x2ca1c800>; | |
| opp-peak-kBps = <0x1b86e0 0x8ca000>; | |
| }; | |
| opp-825600000 { | |
| opp-hz = <0x00 0x3135a800>; | |
| opp-peak-kBps = <0x1b86e0 0x8ca000>; | |
| }; | |
| opp-902400000 { | |
| opp-hz = <0x00 0x35c98800>; | |
| opp-peak-kBps = <0x1b86e0 0x9f6000>; | |
| }; | |
| opp-979200000 { | |
| opp-hz = <0x00 0x3a5d6800>; | |
| opp-peak-kBps = <0x1b86e0 0xb6d000>; | |
| }; | |
| opp-1056000000 { | |
| opp-hz = <0x00 0x3ef14800>; | |
| opp-peak-kBps = <0x1b86e0 0xb6d000>; | |
| }; | |
| opp-1132800000 { | |
| opp-hz = <0x00 0x43852800>; | |
| opp-peak-kBps = <0x2162e0 0xce4000>; | |
| }; | |
| opp-1228800000 { | |
| opp-hz = <0x00 0x493e0000>; | |
| opp-peak-kBps = <0x2162e0 0xe5b000>; | |
| }; | |
| opp-1324800000 { | |
| opp-hz = <0x00 0x4ef6d800>; | |
| opp-peak-kBps = <0x2162e0 0xfd2000>; | |
| }; | |
| opp-1420800000 { | |
| opp-hz = <0x00 0x54afb000>; | |
| opp-peak-kBps = <0x2ee000 0x1149000>; | |
| }; | |
| opp-1516800000 { | |
| opp-hz = <0x00 0x5a688800>; | |
| opp-peak-kBps = <0x2ee000 0x1275000>; | |
| }; | |
| opp-1612800000 { | |
| opp-hz = <0x00 0x60216000>; | |
| opp-peak-kBps = <0x3e12a0 0x1275000>; | |
| }; | |
| opp-1689600000 { | |
| opp-hz = <0x00 0x64b54000>; | |
| opp-peak-kBps = <0x3e12a0 0x13ec000>; | |
| }; | |
| opp-1766400000 { | |
| opp-hz = <0x00 0x69492000>; | |
| opp-peak-kBps = <0x3e12a0 0x1563000>; | |
| }; | |
| }; | |
| cpu4_opp_table { | |
| compatible = "operating-points-v2"; | |
| opp-shared; | |
| phandle = <0x11>; | |
| opp-300000000 { | |
| opp-hz = <0x00 0x11e1a300>; | |
| opp-peak-kBps = "\0\f5\0\0I>"; | |
| }; | |
| opp-403200000 { | |
| opp-hz = <0x00 0x18085800>; | |
| opp-peak-kBps = "\0\f5\0\0I>"; | |
| }; | |
| opp-480000000 { | |
| opp-hz = <0x00 0x1c9c3800>; | |
| opp-peak-kBps = <0x1b86e0 0x493e00>; | |
| }; | |
| opp-576000000 { | |
| opp-hz = <0x00 0x22551000>; | |
| opp-peak-kBps = <0x1b86e0 0x493e00>; | |
| }; | |
| opp-652800000 { | |
| opp-hz = <0x00 0x26e8f000>; | |
| opp-peak-kBps = <0x1b86e0 0x493e00>; | |
| }; | |
| opp-748800000 { | |
| opp-hz = <0x00 0x2ca1c800>; | |
| opp-peak-kBps = <0x1b86e0 0x493e00>; | |
| }; | |
| opp-825600000 { | |
| opp-hz = <0x00 0x3135a800>; | |
| opp-peak-kBps = <0x2162e0 0x8ca000>; | |
| }; | |
| opp-902400000 { | |
| opp-hz = <0x00 0x35c98800>; | |
| opp-peak-kBps = <0x2162e0 0x8ca000>; | |
| }; | |
| opp-979200000 { | |
| opp-hz = <0x00 0x3a5d6800>; | |
| opp-peak-kBps = <0x2162e0 0x8ca000>; | |
| }; | |
| opp-1056000000 { | |
| opp-hz = <0x00 0x3ef14800>; | |
| opp-peak-kBps = <0x2ee000 0x8ca000>; | |
| }; | |
| opp-1132800000 { | |
| opp-hz = <0x00 0x43852800>; | |
| opp-peak-kBps = <0x2ee000 0xb6d000>; | |
| }; | |
| opp-1209600000 { | |
| opp-hz = <0x00 0x48190800>; | |
| opp-peak-kBps = <0x3e12a0 0xb6d000>; | |
| }; | |
| opp-1286400000 { | |
| opp-hz = <0x00 0x4cace800>; | |
| opp-peak-kBps = <0x3e12a0 0xb6d000>; | |
| }; | |
| opp-1363200000 { | |
| opp-hz = <0x00 0x5140c800>; | |
| opp-peak-kBps = <0x3e12a0 0xe5b000>; | |
| }; | |
| opp-1459200000 { | |
| opp-hz = <0x00 0x56f9a000>; | |
| opp-peak-kBps = <0x3e12a0 0xe5b000>; | |
| }; | |
| opp-1536000000 { | |
| opp-hz = <0x00 0x5b8d8000>; | |
| opp-peak-kBps = <0x5294a0 0xe5b000>; | |
| }; | |
| opp-1612800000 { | |
| opp-hz = <0x00 0x60216000>; | |
| opp-peak-kBps = <0x5294a0 0xe5b000>; | |
| }; | |
| opp-1689600000 { | |
| opp-hz = <0x00 0x64b54000>; | |
| opp-peak-kBps = <0x5294a0 0x1275000>; | |
| }; | |
| opp-1766400000 { | |
| opp-hz = <0x00 0x69492000>; | |
| opp-peak-kBps = <0x5ee8e0 0x1275000>; | |
| }; | |
| opp-1843200000 { | |
| opp-hz = <0x00 0x6ddd0000>; | |
| opp-peak-kBps = <0x5ee8e0 0x1275000>; | |
| }; | |
| opp-1920000000 { | |
| opp-hz = <0x00 0x7270e000>; | |
| opp-peak-kBps = <0x6e1b80 0x1275000>; | |
| }; | |
| opp-1996800000 { | |
| opp-hz = <0x00 0x7704c000>; | |
| opp-peak-kBps = <0x6e1b80 0x13ec000>; | |
| }; | |
| opp-2092800000 { | |
| opp-hz = <0x00 0x7cbd9800>; | |
| opp-peak-kBps = <0x6e1b80 0x13ec000>; | |
| }; | |
| opp-2169600000 { | |
| opp-hz = <0x00 0x81517800>; | |
| opp-peak-kBps = <0x6e1b80 0x13ec000>; | |
| }; | |
| opp-2246400000 { | |
| opp-hz = <0x00 0x85e55800>; | |
| opp-peak-kBps = <0x6e1b80 0x13ec000>; | |
| }; | |
| opp-2323200000 { | |
| opp-hz = <0x00 0x8a793800>; | |
| opp-peak-kBps = <0x6e1b80 0x13ec000>; | |
| }; | |
| opp-2400000000 { | |
| opp-hz = <0x00 0x8f0d1800>; | |
| opp-peak-kBps = <0x6e1b80 0x1563000>; | |
| }; | |
| opp-2476800000 { | |
| opp-hz = <0x00 0x93a0f800>; | |
| opp-peak-kBps = <0x6e1b80 0x1563000>; | |
| }; | |
| opp-2553600000 { | |
| opp-hz = <0x00 0x9834d800>; | |
| opp-peak-kBps = <0x6e1b80 0x1563000>; | |
| }; | |
| opp-2649600000 { | |
| opp-hz = <0x00 0x9dedb000>; | |
| opp-peak-kBps = <0x6e1b80 0x1563000>; | |
| }; | |
| opp-2745600000 { | |
| opp-hz = <0x00 0xa3a68800>; | |
| opp-peak-kBps = <0x6e1b80 0x1851000>; | |
| }; | |
| opp-2803200000 { | |
| opp-hz = <0x00 0xa7157000>; | |
| opp-peak-kBps = <0x6e1b80 0x1851000>; | |
| }; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupts = <0x01 0x05 0x04>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x01 0x01 0x08 0x01 0x02 0x08 0x01 0x03 0x08 0x01 0x00 0x08>; | |
| }; | |
| clocks { | |
| xo-board { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x249f000>; | |
| clock-output-names = "xo_board"; | |
| phandle = <0xd2>; | |
| }; | |
| sleep-clk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x7ffc>; | |
| phandle = <0x2a>; | |
| }; | |
| }; | |
| firmware { | |
| scm { | |
| compatible = "qcom,scm-sdm845\0qcom,scm"; | |
| }; | |
| }; | |
| remoteproc-adsp { | |
| compatible = "qcom,sdm845-adsp-pas"; | |
| interrupts-extended = <0x01 0x00 0xa2 0x01 0x1e 0x00 0x01 0x1e 0x01 0x01 0x1e 0x02 0x01 0x1e 0x03 0x01>; | |
| interrupt-names = "wdog\0fatal\0ready\0handover\0stop-ack"; | |
| clocks = <0x1f 0x00>; | |
| clock-names = "xo"; | |
| memory-region = <0x20>; | |
| qcom,smem-states = <0x21 0x00>; | |
| qcom,smem-state-names = "stop"; | |
| status = "okay"; | |
| firmware-name = "qcom/sdm845/oneplus6/adsp.mbn"; | |
| glink-edge { | |
| interrupts = <0x00 0x9c 0x01>; | |
| label = "lpass"; | |
| qcom,remote-pid = <0x02>; | |
| mboxes = <0x22 0x08>; | |
| apr { | |
| compatible = "qcom,apr-v2"; | |
| qcom,glink-channels = "apr_audio_svc"; | |
| qcom,apr-domain = <0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,intents = <0x200 0x14>; | |
| apr-service@3 { | |
| reg = <0x03>; | |
| compatible = "qcom,q6core"; | |
| qcom,protection-domain = "avs/audio\0msm/adsp/audio_pd"; | |
| }; | |
| apr-service@4 { | |
| compatible = "qcom,q6afe"; | |
| reg = <0x04>; | |
| qcom,protection-domain = "avs/audio\0msm/adsp/audio_pd"; | |
| dais { | |
| compatible = "qcom,q6afe-dais"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #sound-dai-cells = <0x01>; | |
| }; | |
| }; | |
| apr-service@7 { | |
| compatible = "qcom,q6asm"; | |
| reg = <0x07>; | |
| qcom,protection-domain = "avs/audio\0msm/adsp/audio_pd"; | |
| dais { | |
| compatible = "qcom,q6asm-dais"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #sound-dai-cells = <0x01>; | |
| iommus = <0x23 0x1821 0x00>; | |
| }; | |
| }; | |
| apr-service@8 { | |
| compatible = "qcom,q6adm"; | |
| reg = <0x08>; | |
| qcom,protection-domain = "avs/audio\0msm/adsp/audio_pd"; | |
| routing { | |
| compatible = "qcom,q6adm-routing"; | |
| #sound-dai-cells = <0x00>; | |
| }; | |
| }; | |
| }; | |
| fastrpc { | |
| compatible = "qcom,fastrpc"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| label = "adsp"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compute-cb@3 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x03>; | |
| iommus = <0x23 0x1823 0x00>; | |
| }; | |
| compute-cb@4 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x04>; | |
| iommus = <0x23 0x1824 0x00>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| remoteproc-cdsp { | |
| compatible = "qcom,sdm845-cdsp-pas"; | |
| interrupts-extended = <0x01 0x00 0x242 0x01 0x24 0x00 0x01 0x24 0x01 0x01 0x24 0x02 0x01 0x24 0x03 0x01>; | |
| interrupt-names = "wdog\0fatal\0ready\0handover\0stop-ack"; | |
| clocks = <0x1f 0x00>; | |
| clock-names = "xo"; | |
| memory-region = <0x25>; | |
| qcom,smem-states = <0x26 0x00>; | |
| qcom,smem-state-names = "stop"; | |
| status = "okay"; | |
| firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn"; | |
| glink-edge { | |
| interrupts = <0x00 0x23e 0x01>; | |
| label = "turing"; | |
| qcom,remote-pid = <0x05>; | |
| mboxes = <0x22 0x04>; | |
| fastrpc { | |
| compatible = "qcom,fastrpc"; | |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| label = "cdsp"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compute-cb@1 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x01>; | |
| iommus = <0x23 0x1401 0x30>; | |
| }; | |
| compute-cb@2 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x02>; | |
| iommus = <0x23 0x1402 0x30>; | |
| }; | |
| compute-cb@3 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x03>; | |
| iommus = <0x23 0x1403 0x30>; | |
| }; | |
| compute-cb@4 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x04>; | |
| iommus = <0x23 0x1404 0x30>; | |
| }; | |
| compute-cb@5 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x05>; | |
| iommus = <0x23 0x1405 0x30>; | |
| }; | |
| compute-cb@6 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x06>; | |
| iommus = <0x23 0x1406 0x30>; | |
| }; | |
| compute-cb@7 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x07>; | |
| iommus = <0x23 0x1407 0x30>; | |
| }; | |
| compute-cb@8 { | |
| compatible = "qcom,fastrpc-compute-cb"; | |
| reg = <0x08>; | |
| iommus = <0x23 0x1408 0x30>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| hwlock { | |
| compatible = "qcom,tcsr-mutex"; | |
| syscon = <0x27 0x00 0x1000>; | |
| #hwlock-cells = <0x01>; | |
| phandle = <0x29>; | |
| }; | |
| smem { | |
| compatible = "qcom,smem"; | |
| memory-region = <0x28>; | |
| hwlocks = <0x29 0x03>; | |
| }; | |
| smp2p-cdsp { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <0x5e 0x1b0>; | |
| interrupts = <0x00 0x240 0x01>; | |
| mboxes = <0x22 0x06>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x05>; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x26>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x24>; | |
| }; | |
| }; | |
| smp2p-lpass { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <0x1bb 0x1ad>; | |
| interrupts = <0x00 0x9e 0x01>; | |
| mboxes = <0x22 0x0a>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x02>; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x21>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1e>; | |
| }; | |
| }; | |
| smp2p-mpss { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <0x1b3 0x1ac>; | |
| interrupts = <0x00 0x1c3 0x01>; | |
| mboxes = <0x22 0x0e>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x01>; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x7c>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x7b>; | |
| }; | |
| ipa-ap-to-modem { | |
| qcom,entry-name = "ipa"; | |
| #qcom,smem-state-cells = <0x01>; | |
| phandle = <0x78>; | |
| }; | |
| ipa-modem-to-ap { | |
| qcom,entry-name = "ipa"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x76>; | |
| }; | |
| }; | |
| smp2p-slpi { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <0x1e1 0x1ae>; | |
| interrupts = <0x00 0xac 0x01>; | |
| mboxes = <0x22 0x1a>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x03>; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <0x01>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| }; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| }; | |
| soc@0 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges = <0x00 0x00 0x00 0x00 0x10 0x00>; | |
| dma-ranges = <0x00 0x00 0x00 0x00 0x10 0x00>; | |
| compatible = "simple-bus"; | |
| clock-controller@100000 { | |
| compatible = "qcom,gcc-sdm845"; | |
| reg = <0x00 0x100000 0x00 0x1f0000>; | |
| clocks = <0x1f 0x00 0x1f 0x01 0x2a 0x2b 0x2c>; | |
| clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0pcie_0_pipe_clk\0pcie_1_pipe_clk"; | |
| #clock-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| #power-domain-cells = <0x01>; | |
| protected-clocks = <0xbc 0xbb 0xbd 0xbe 0xbf>; | |
| phandle = <0x2d>; | |
| }; | |
| qfprom@784000 { | |
| compatible = "qcom,qfprom"; | |
| reg = <0x00 0x784000 0x00 0x8ff>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| hstx-trim-primary@1eb { | |
| reg = <0x1eb 0x01>; | |
| bits = <0x01 0x04>; | |
| phandle = <0xa8>; | |
| }; | |
| hstx-trim-secondary@1eb { | |
| reg = <0x1eb 0x02>; | |
| bits = <0x06 0x04>; | |
| phandle = <0xab>; | |
| }; | |
| }; | |
| rng@793000 { | |
| compatible = "qcom,prng-ee"; | |
| reg = <0x00 0x793000 0x00 0x1000>; | |
| clocks = <0x2d 0x40>; | |
| clock-names = "core"; | |
| }; | |
| qup-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x36>; | |
| opp-50000000 { | |
| opp-hz = <0x00 0x2faf080>; | |
| required-opps = <0x2e>; | |
| }; | |
| opp-75000000 { | |
| opp-hz = <0x00 0x47868c0>; | |
| required-opps = <0x2f>; | |
| }; | |
| opp-100000000 { | |
| opp-hz = <0x00 0x5f5e100>; | |
| required-opps = <0x30>; | |
| }; | |
| opp-128000000 { | |
| opp-hz = <0x00 0x7a12000>; | |
| required-opps = <0x31>; | |
| }; | |
| }; | |
| geniqup@8c0000 { | |
| compatible = "qcom,geni-se-qup"; | |
| reg = <0x00 0x8c0000 0x00 0x6000>; | |
| clock-names = "m-ahb\0s-ahb"; | |
| clocks = <0x2d 0x64 0x2d 0x65>; | |
| iommus = <0x23 0x03 0x00>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core"; | |
| status = "okay"; | |
| i2c@880000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x880000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x44>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x34>; | |
| interrupts = <0x00 0x259 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00 0x32 0x0a 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@880000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x880000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x44>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x37>; | |
| interrupts = <0x00 0x259 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@880000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x880000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x44>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x38>; | |
| interrupts = <0x00 0x259 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@884000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x884000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x46>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x39>; | |
| interrupts = <0x00 0x25a 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00 0x32 0x0a 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@884000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x884000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x46>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3a>; | |
| interrupts = <0x00 0x25a 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@884000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x884000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x46>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3b>; | |
| interrupts = <0x00 0x25a 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@888000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x888000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x48>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3c>; | |
| interrupts = <0x00 0x25b 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00 0x32 0x0a 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@888000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x888000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x48>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3d>; | |
| interrupts = <0x00 0x25b 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@888000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x888000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x48>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3e>; | |
| interrupts = <0x00 0x25b 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@88c000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x88c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4a>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3f>; | |
| interrupts = <0x00 0x25c 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00 0x32 0x0a 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@88c000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x88c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4a>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x40>; | |
| interrupts = <0x00 0x25c 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@88c000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x88c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4a>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x41>; | |
| interrupts = <0x00 0x25c 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@890000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x890000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4c>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x42>; | |
| interrupts = <0x00 0x25d 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00 0x32 0x0a 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@890000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x890000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4c>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x43>; | |
| interrupts = <0x00 0x25d 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@890000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x890000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4c>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x44>; | |
| interrupts = <0x00 0x25d 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@894000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x894000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4e>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x45>; | |
| interrupts = <0x00 0x25e 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00 0x32 0x0a 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@894000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x894000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4e>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x46>; | |
| interrupts = <0x00 0x25e 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@894000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x894000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x4e>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x47>; | |
| interrupts = <0x00 0x25e 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@898000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x898000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x50>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x48>; | |
| interrupts = <0x00 0x25f 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00 0x32 0x0a 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@898000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x898000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x50>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x49>; | |
| interrupts = <0x00 0x25f 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@898000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x898000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x50>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x4a>; | |
| interrupts = <0x00 0x25f 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "okay"; | |
| bluetooth { | |
| compatible = "qcom,wcn3990-bt"; | |
| firmware-name = "oneplus6/crnv21.bin"; | |
| vddio-supply = <0x4b>; | |
| vddxo-supply = <0x4c>; | |
| vddrf-supply = <0x4d>; | |
| vddch0-supply = <0x4e>; | |
| max-speed = <0x30d400>; | |
| }; | |
| }; | |
| i2c@89c000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0x89c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x52>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x4f>; | |
| interrupts = <0x00 0x260 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| status = "disabled"; | |
| }; | |
| spi@89c000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0x89c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x52>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x50>; | |
| interrupts = <0x00 0x260 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@89c000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0x89c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x52>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x51>; | |
| interrupts = <0x00 0x260 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x32 0x0a 0x00 0x33 0x1d 0x00 0x07 0x00 0x00 0x33 0x1d 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| }; | |
| geniqup@ac0000 { | |
| compatible = "qcom,geni-se-qup"; | |
| reg = <0x00 0xac0000 0x00 0x6000>; | |
| clock-names = "m-ahb\0s-ahb"; | |
| clocks = <0x2d 0x66 0x2d 0x67>; | |
| iommus = <0x23 0x6c3 0x00>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core"; | |
| status = "okay"; | |
| i2c@a80000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa80000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x54>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x53>; | |
| interrupts = <0x00 0x161 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@a80000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa80000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x54>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x54>; | |
| interrupts = <0x00 0x161 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a80000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0xa80000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x54>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x55>; | |
| interrupts = <0x00 0x161 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@a84000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa84000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x56>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x56>; | |
| interrupts = <0x00 0x162 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@a84000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa84000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x56>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x57>; | |
| interrupts = <0x00 0x162 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a84000 { | |
| compatible = "qcom,geni-debug-uart"; | |
| reg = <0x00 0xa84000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x56>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x58>; | |
| interrupts = <0x00 0x162 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "okay"; | |
| label = "LS-UART1"; | |
| }; | |
| i2c@a88000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa88000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x58>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x59>; | |
| interrupts = <0x00 0x163 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@a88000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa88000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x58>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5a>; | |
| interrupts = <0x00 0x163 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a88000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0xa88000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x58>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5b>; | |
| interrupts = <0x00 0x163 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@a8c000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa8c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5a>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5c>; | |
| interrupts = <0x00 0x164 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@a8c000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa8c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5a>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5d>; | |
| interrupts = <0x00 0x164 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a8c000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0xa8c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5a>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5e>; | |
| interrupts = <0x00 0x164 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@a90000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa90000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5c>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5f>; | |
| interrupts = <0x00 0x165 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "okay"; | |
| clock-frequency = <0x61a80>; | |
| synaptics-rmi4-i2c@20 { | |
| compatible = "syna,rmi4-i2c"; | |
| reg = <0x20>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interrupts-extended = <0x60 0x7d 0x02>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x61>; | |
| vdd-supply = <0x62>; | |
| vio-supply = <0x63>; | |
| syna,reset-delay-ms = <0xc8>; | |
| syna,startup-delay-ms = <0xc8>; | |
| rmi4-f01@1 { | |
| reg = <0x01>; | |
| syna,nosleep-mode = <0x01>; | |
| }; | |
| rmi4-f12@12 { | |
| reg = <0x12>; | |
| touchscreen-x-mm = <0x44>; | |
| touchscreen-y-mm = <0x94>; | |
| syna,sensor-type = <0x01>; | |
| syna,rezero-wait-ms = <0xc8>; | |
| }; | |
| }; | |
| }; | |
| spi@a90000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa90000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5c>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x64>; | |
| interrupts = <0x00 0x165 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a90000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0xa90000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5c>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x65>; | |
| interrupts = <0x00 0x165 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@a94000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa94000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5e>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x66>; | |
| interrupts = <0x00 0x166 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@a94000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa94000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5e>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x67>; | |
| interrupts = <0x00 0x166 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a94000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0xa94000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x5e>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x68>; | |
| interrupts = <0x00 0x166 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@a98000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa98000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x60>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x69>; | |
| interrupts = <0x00 0x167 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| status = "disabled"; | |
| }; | |
| spi@a98000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa98000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x60>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x6a>; | |
| interrupts = <0x00 0x167 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a98000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0xa98000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x60>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x6b>; | |
| interrupts = <0x00 0x167 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| i2c@a9c000 { | |
| compatible = "qcom,geni-i2c"; | |
| reg = <0x00 0xa9c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x62>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x6c>; | |
| interrupts = <0x00 0x168 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| status = "disabled"; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00 0x52 0x0c 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "qup-core\0qup-config\0qup-memory"; | |
| }; | |
| spi@a9c000 { | |
| compatible = "qcom,geni-spi"; | |
| reg = <0x00 0xa9c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x62>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x6d>; | |
| interrupts = <0x00 0x168 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| serial@a9c000 { | |
| compatible = "qcom,geni-uart"; | |
| reg = <0x00 0xa9c000 0x00 0x4000>; | |
| clock-names = "se"; | |
| clocks = <0x2d 0x62>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x6e>; | |
| interrupts = <0x00 0x168 0x04>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0x36>; | |
| interconnects = <0x52 0x0c 0x00 0x33 0x1c 0x00 0x07 0x00 0x00 0x33 0x1c 0x00>; | |
| interconnect-names = "qup-core\0qup-config"; | |
| status = "disabled"; | |
| }; | |
| }; | |
| system-cache-controller@1100000 { | |
| compatible = "qcom,sdm845-llcc"; | |
| reg = <0x00 0x1100000 0x00 0x200000 0x00 0x1300000 0x00 0x50000>; | |
| reg-names = "llcc_base\0llcc_broadcast_base"; | |
| interrupts = <0x00 0x246 0x04>; | |
| }; | |
| pci@1c00000 { | |
| compatible = "qcom,pcie-sdm845\0snps,dw-pcie"; | |
| reg = <0x00 0x1c00000 0x00 0x2000 0x00 0x60000000 0x00 0xf1d 0x00 0x60000f20 0x00 0xa8 0x00 0x60100000 0x00 0x100000>; | |
| reg-names = "parf\0dbi\0elbi\0config"; | |
| device_type = "pci"; | |
| linux,pci-domain = <0x00>; | |
| bus-range = <0x00 0xff>; | |
| num-lanes = <0x01>; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| ranges = <0x1000000 0x00 0x60200000 0x00 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x00 0x60300000 0x00 0xd00000>; | |
| interrupts = <0x00 0x8d 0x04>; | |
| interrupt-names = "msi"; | |
| #interrupt-cells = <0x01>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x95 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x96 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x97 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x98 0x04>; | |
| clocks = <0x2d 0x2e 0x2d 0x29 0x2d 0x2b 0x2d 0x2d 0x2d 0x2f 0x2d 0x30 0x2d 0x00>; | |
| clock-names = "pipe\0aux\0cfg\0bus_master\0bus_slave\0slave_q2a\0tbu"; | |
| iommus = <0x23 0x1c10 0x0f>; | |
| iommu-map = <0x00 0x23 0x1c10 0x01 0x100 0x23 0x1c11 0x01 0x200 0x23 0x1c12 0x01 0x300 0x23 0x1c13 0x01 0x400 0x23 0x1c14 0x01 0x500 0x23 0x1c15 0x01 0x600 0x23 0x1c16 0x01 0x700 0x23 0x1c17 0x01 0x800 0x23 0x1c18 0x01 0x900 0x23 0x1c19 0x01 0xa00 0x23 0x1c1a 0x01 0xb00 0x23 0x1c1b 0x01 0xc00 0x23 0x1c1c 0x01 0xd00 0x23 0x1c1d 0x01 0xe00 0x23 0x1c1e 0x01 0xf00 0x23 0x1c1f 0x01>; | |
| resets = <0x2d 0x01>; | |
| reset-names = "pci"; | |
| power-domains = <0x2d 0x00>; | |
| phys = <0x2b>; | |
| phy-names = "pciephy"; | |
| status = "disabled"; | |
| }; | |
| phy@1c06000 { | |
| compatible = "qcom,sdm845-qmp-pcie-phy"; | |
| reg = <0x00 0x1c06000 0x00 0x18c>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| clocks = <0x2d 0x39 0x2d 0x2b 0x2d 0x2c 0x2d 0x3a>; | |
| clock-names = "aux\0cfg_ahb\0ref\0refgen"; | |
| resets = <0x2d 0x18>; | |
| reset-names = "phy"; | |
| assigned-clocks = <0x2d 0x3a>; | |
| assigned-clock-rates = <0x5f5e100>; | |
| status = "disabled"; | |
| lanes@1c06200 { | |
| reg = <0x00 0x1c06200 0x00 0x128 0x00 0x1c06400 0x00 0x1fc 0x00 0x1c06800 0x00 0x218 0x00 0x1c06600 0x00 0x70>; | |
| clocks = <0x2d 0x2e>; | |
| clock-names = "pipe0"; | |
| #clock-cells = <0x00>; | |
| #phy-cells = <0x00>; | |
| clock-output-names = "pcie_0_pipe_clk"; | |
| phandle = <0x2b>; | |
| }; | |
| }; | |
| pci@1c08000 { | |
| compatible = "qcom,pcie-sdm845\0snps,dw-pcie"; | |
| reg = <0x00 0x1c08000 0x00 0x2000 0x00 0x40000000 0x00 0xf1d 0x00 0x40000f20 0x00 0xa8 0x00 0x40100000 0x00 0x100000>; | |
| reg-names = "parf\0dbi\0elbi\0config"; | |
| device_type = "pci"; | |
| linux,pci-domain = <0x01>; | |
| bus-range = <0x00 0xff>; | |
| num-lanes = <0x01>; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| ranges = <0x1000000 0x00 0x40200000 0x00 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x00 0x40300000 0x00 0x1fd00000>; | |
| interrupts = <0x00 0x133 0x01>; | |
| interrupt-names = "msi"; | |
| #interrupt-cells = <0x01>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x1b2 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x1b3 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x1b6 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x1b7 0x04>; | |
| clocks = <0x2d 0x36 0x2d 0x31 0x2d 0x33 0x2d 0x35 0x2d 0x37 0x2d 0x38 0x2d 0x34 0x2d 0x00>; | |
| clock-names = "pipe\0aux\0cfg\0bus_master\0bus_slave\0slave_q2a\0ref\0tbu"; | |
| assigned-clocks = <0x2d 0x31>; | |
| assigned-clock-rates = <0x124f800>; | |
| iommus = <0x23 0x1c00 0x0f>; | |
| iommu-map = <0x00 0x23 0x1c00 0x01 0x100 0x23 0x1c01 0x01 0x200 0x23 0x1c02 0x01 0x300 0x23 0x1c03 0x01 0x400 0x23 0x1c04 0x01 0x500 0x23 0x1c05 0x01 0x600 0x23 0x1c06 0x01 0x700 0x23 0x1c07 0x01 0x800 0x23 0x1c08 0x01 0x900 0x23 0x1c09 0x01 0xa00 0x23 0x1c0a 0x01 0xb00 0x23 0x1c0b 0x01 0xc00 0x23 0x1c0c 0x01 0xd00 0x23 0x1c0d 0x01 0xe00 0x23 0x1c0e 0x01 0xf00 0x23 0x1c0f 0x01>; | |
| resets = <0x2d 0x02>; | |
| reset-names = "pci"; | |
| power-domains = <0x2d 0x01>; | |
| phys = <0x2c>; | |
| phy-names = "pciephy"; | |
| status = "disabled"; | |
| }; | |
| phy@1c0a000 { | |
| compatible = "qcom,sdm845-qhp-pcie-phy"; | |
| reg = <0x00 0x1c0a000 0x00 0x800>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| clocks = <0x2d 0x39 0x2d 0x33 0x2d 0x34 0x2d 0x3a>; | |
| clock-names = "aux\0cfg_ahb\0ref\0refgen"; | |
| resets = <0x2d 0x19>; | |
| reset-names = "phy"; | |
| assigned-clocks = <0x2d 0x3a>; | |
| assigned-clock-rates = <0x5f5e100>; | |
| status = "disabled"; | |
| lanes@1c06200 { | |
| reg = <0x00 0x1c0a800 0x00 0x800 0x00 0x1c0a800 0x00 0x800 0x00 0x1c0b800 0x00 0x400>; | |
| clocks = <0x2d 0x36>; | |
| clock-names = "pipe0"; | |
| #clock-cells = <0x00>; | |
| #phy-cells = <0x00>; | |
| clock-output-names = "pcie_1_pipe_clk"; | |
| phandle = <0x2c>; | |
| }; | |
| }; | |
| interconnect@1380000 { | |
| compatible = "qcom,sdm845-mem-noc"; | |
| reg = <0x00 0x1380000 0x00 0x27200>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| phandle = <0x08>; | |
| }; | |
| interconnect@14e0000 { | |
| compatible = "qcom,sdm845-dc-noc"; | |
| reg = <0x00 0x14e0000 0x00 0x400>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| }; | |
| interconnect@1500000 { | |
| compatible = "qcom,sdm845-config-noc"; | |
| reg = <0x00 0x1500000 0x00 0x5080>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| phandle = <0x33>; | |
| }; | |
| interconnect@1620000 { | |
| compatible = "qcom,sdm845-system-noc"; | |
| reg = <0x00 0x1620000 0x00 0x18080>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| phandle = <0x77>; | |
| }; | |
| interconnect@16e0000 { | |
| compatible = "qcom,sdm845-aggre1-noc"; | |
| reg = <0x00 0x16e0000 0x00 0x15080>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| phandle = <0x32>; | |
| }; | |
| interconnect@1700000 { | |
| compatible = "qcom,sdm845-aggre2-noc"; | |
| reg = <0x00 0x1700000 0x00 0x1f300>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| phandle = <0x52>; | |
| }; | |
| interconnect@1740000 { | |
| compatible = "qcom,sdm845-mmss-noc"; | |
| reg = <0x00 0x1740000 0x00 0x1c100>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| phandle = <0xb2>; | |
| }; | |
| ufshc@1d84000 { | |
| compatible = "qcom,sdm845-ufshc\0qcom,ufshc\0jedec,ufs-2.0"; | |
| reg = <0x00 0x1d84000 0x00 0x2500 0x00 0x1d90000 0x00 0x8000>; | |
| reg-names = "std\0ice"; | |
| interrupts = <0x00 0x109 0x04>; | |
| phys = <0x70>; | |
| phy-names = "ufsphy"; | |
| lanes-per-direction = <0x02>; | |
| power-domains = <0x2d 0x03>; | |
| #reset-cells = <0x01>; | |
| resets = <0x2d 0x0e>; | |
| reset-names = "rst"; | |
| iommus = <0x23 0x100 0x0f>; | |
| clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk\0ice_core_clk"; | |
| clocks = <0x2d 0x82 0x2d 0x02 0x2d 0x81 0x2d 0x8b 0x1f 0x00 0x2d 0x8a 0x2d 0x88 0x2d 0x89 0x2d 0x84>; | |
| freq-table-hz = <0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x11e1a300>; | |
| status = "okay"; | |
| reset-gpios = <0x60 0x96 0x01>; | |
| vcc-supply = <0x71>; | |
| vcc-max-microamp = <0x927c0>; | |
| phandle = <0x72>; | |
| }; | |
| phy@1d87000 { | |
| compatible = "qcom,sdm845-qmp-ufs-phy"; | |
| reg = <0x00 0x1d87000 0x00 0x18c>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| clock-names = "ref\0ref_aux"; | |
| clocks = <0x2d 0x80 0x2d 0x86>; | |
| resets = <0x72 0x00>; | |
| reset-names = "ufsphy"; | |
| status = "okay"; | |
| vdda-phy-supply = <0x73>; | |
| vdda-pll-supply = <0x74>; | |
| lanes@1d87400 { | |
| reg = <0x00 0x1d87400 0x00 0x108 0x00 0x1d87600 0x00 0x1e0 0x00 0x1d87c00 0x00 0x1dc 0x00 0x1d87800 0x00 0x108 0x00 0x1d87a00 0x00 0x1e0>; | |
| #phy-cells = <0x00>; | |
| phandle = <0x70>; | |
| }; | |
| }; | |
| dma@1dc4000 { | |
| compatible = "qcom,bam-v1.7.0"; | |
| reg = <0x00 0x1dc4000 0x00 0x24000>; | |
| interrupts = <0x00 0x110 0x04>; | |
| clocks = <0x1f 0x0f>; | |
| clock-names = "bam_clk"; | |
| #dma-cells = <0x01>; | |
| qcom,ee = <0x00>; | |
| qcom,controlled-remotely = <0x01>; | |
| iommus = <0x23 0x704 0x01 0x23 0x706 0x01 0x23 0x714 0x01 0x23 0x716 0x01>; | |
| phandle = <0x75>; | |
| }; | |
| crypto@1dfa000 { | |
| compatible = "qcom,crypto-v5.4"; | |
| reg = <0x00 0x1dfa000 0x00 0x6000>; | |
| clocks = <0x2d 0x09 0x2d 0x09 0x1f 0x0f>; | |
| clock-names = "iface\0bus\0core"; | |
| dmas = <0x75 0x06 0x75 0x07>; | |
| dma-names = "rx\0tx"; | |
| iommus = <0x23 0x704 0x01 0x23 0x706 0x01 0x23 0x714 0x01 0x23 0x716 0x01>; | |
| }; | |
| ipa@1e40000 { | |
| compatible = "qcom,sdm845-ipa"; | |
| iommus = <0x23 0x720 0x00 0x23 0x722 0x00>; | |
| reg = <0x00 0x1e40000 0x00 0x7000 0x00 0x1e47000 0x00 0x2000 0x00 0x1e04000 0x00 0x2c000>; | |
| reg-names = "ipa-reg\0ipa-shared\0gsi"; | |
| interrupts-extended = <0x01 0x00 0x137 0x01 0x01 0x00 0x1b0 0x04 0x76 0x00 0x01 0x76 0x01 0x01>; | |
| interrupt-names = "ipa\0gsi\0ipa-clock-query\0ipa-setup-ready"; | |
| clocks = <0x1f 0x0c>; | |
| clock-names = "core"; | |
| interconnects = <0x52 0x04 0x00 0x08 0x0e 0x00 0x52 0x04 0x00 0x77 0x0c 0x00 0x07 0x00 0x00 0x33 0x13 0x00>; | |
| interconnect-names = "memory\0imem\0config"; | |
| qcom,smem-states = <0x78 0x00 0x78 0x01>; | |
| qcom,smem-state-names = "ipa-clock-enabled-valid\0ipa-clock-enabled"; | |
| status = "okay"; | |
| memory-region = <0x79>; | |
| firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn"; | |
| }; | |
| syscon@1f40000 { | |
| compatible = "syscon"; | |
| reg = <0x00 0x1f40000 0x00 0x40000>; | |
| phandle = <0x27>; | |
| }; | |
| pinctrl@3400000 { | |
| compatible = "qcom,sdm845-pinctrl"; | |
| reg = <0x00 0x3400000 0x00 0xc00000>; | |
| interrupts = <0x00 0xd0 0x04>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| gpio-ranges = <0x60 0x00 0x00 0x97>; | |
| wakeup-parent = <0x7a>; | |
| gpio-reserved-ranges = <0x00 0x04 0x51 0x04>; | |
| phandle = <0x60>; | |
| cci0-default { | |
| pins = "gpio17\0gpio18"; | |
| function = "cci_i2c"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| phandle = <0xb5>; | |
| }; | |
| cci0-sleep { | |
| pins = "gpio17\0gpio18"; | |
| function = "cci_i2c"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| phandle = <0xb7>; | |
| }; | |
| cci1-default { | |
| pins = "gpio19\0gpio20"; | |
| function = "cci_i2c"; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| phandle = <0xb6>; | |
| }; | |
| cci1-sleep { | |
| pins = "gpio19\0gpio20"; | |
| function = "cci_i2c"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| phandle = <0xb8>; | |
| }; | |
| qspi-clk { | |
| pinmux { | |
| pins = "gpio95"; | |
| function = "qspi_clk"; | |
| }; | |
| }; | |
| qspi-cs0 { | |
| pinmux { | |
| pins = "gpio90"; | |
| function = "qspi_cs"; | |
| }; | |
| }; | |
| qspi-cs1 { | |
| pinmux { | |
| pins = "gpio89"; | |
| function = "qspi_cs"; | |
| }; | |
| }; | |
| qspi-data01 { | |
| pinmux-data { | |
| pins = "gpio91\0gpio92"; | |
| function = "qspi_data"; | |
| }; | |
| }; | |
| qspi-data12 { | |
| pinmux-data { | |
| pins = "gpio93\0gpio94"; | |
| function = "qspi_data"; | |
| }; | |
| }; | |
| qup-i2c0-default { | |
| phandle = <0x34>; | |
| pinmux { | |
| pins = "gpio0\0gpio1"; | |
| function = "qup0"; | |
| }; | |
| }; | |
| qup-i2c1-default { | |
| phandle = <0x39>; | |
| pinmux { | |
| pins = "gpio17\0gpio18"; | |
| function = "qup1"; | |
| }; | |
| }; | |
| qup-i2c2-default { | |
| phandle = <0x3c>; | |
| pinmux { | |
| pins = "gpio27\0gpio28"; | |
| function = "qup2"; | |
| }; | |
| }; | |
| qup-i2c3-default { | |
| phandle = <0x3f>; | |
| pinmux { | |
| pins = "gpio41\0gpio42"; | |
| function = "qup3"; | |
| }; | |
| }; | |
| qup-i2c4-default { | |
| phandle = <0x42>; | |
| pinmux { | |
| pins = "gpio89\0gpio90"; | |
| function = "qup4"; | |
| }; | |
| }; | |
| qup-i2c5-default { | |
| phandle = <0x45>; | |
| pinmux { | |
| pins = "gpio85\0gpio86"; | |
| function = "qup5"; | |
| }; | |
| }; | |
| qup-i2c6-default { | |
| phandle = <0x48>; | |
| pinmux { | |
| pins = "gpio45\0gpio46"; | |
| function = "qup6"; | |
| }; | |
| }; | |
| qup-i2c7-default { | |
| phandle = <0x4f>; | |
| pinmux { | |
| pins = "gpio93\0gpio94"; | |
| function = "qup7"; | |
| }; | |
| }; | |
| qup-i2c8-default { | |
| phandle = <0x53>; | |
| pinmux { | |
| pins = "gpio65\0gpio66"; | |
| function = "qup8"; | |
| }; | |
| }; | |
| qup-i2c9-default { | |
| phandle = <0x56>; | |
| pinmux { | |
| pins = "gpio6\0gpio7"; | |
| function = "qup9"; | |
| }; | |
| }; | |
| qup-i2c10-default { | |
| phandle = <0x59>; | |
| pinmux { | |
| pins = "gpio55\0gpio56"; | |
| function = "qup10"; | |
| }; | |
| pinconf { | |
| pins = "gpio55\0gpio56"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qup-i2c11-default { | |
| phandle = <0x5c>; | |
| pinmux { | |
| pins = "gpio31\0gpio32"; | |
| function = "qup11"; | |
| }; | |
| }; | |
| qup-i2c12-default { | |
| phandle = <0x5f>; | |
| pinmux { | |
| pins = "gpio49\0gpio50"; | |
| function = "qup12"; | |
| }; | |
| mux { | |
| pins = "gpio49\0gpio50"; | |
| function = "qup12"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| qup-i2c13-default { | |
| phandle = <0x66>; | |
| pinmux { | |
| pins = "gpio105\0gpio106"; | |
| function = "qup13"; | |
| }; | |
| }; | |
| qup-i2c14-default { | |
| phandle = <0x69>; | |
| pinmux { | |
| pins = "gpio33\0gpio34"; | |
| function = "qup14"; | |
| }; | |
| }; | |
| qup-i2c15-default { | |
| phandle = <0x6c>; | |
| pinmux { | |
| pins = "gpio81\0gpio82"; | |
| function = "qup15"; | |
| }; | |
| }; | |
| qup-spi0-default { | |
| phandle = <0x37>; | |
| pinmux { | |
| pins = "gpio0\0gpio1\0gpio2\0gpio3"; | |
| function = "qup0"; | |
| }; | |
| }; | |
| qup-spi1-default { | |
| phandle = <0x3a>; | |
| pinmux { | |
| pins = "gpio17\0gpio18\0gpio19\0gpio20"; | |
| function = "qup1"; | |
| }; | |
| }; | |
| qup-spi2-default { | |
| phandle = <0x3d>; | |
| pinmux { | |
| pins = "gpio27\0gpio28\0gpio29\0gpio30"; | |
| function = "qup2"; | |
| }; | |
| }; | |
| qup-spi3-default { | |
| phandle = <0x40>; | |
| pinmux { | |
| pins = "gpio41\0gpio42\0gpio43\0gpio44"; | |
| function = "qup3"; | |
| }; | |
| }; | |
| qup-spi4-default { | |
| phandle = <0x43>; | |
| pinmux { | |
| pins = "gpio89\0gpio90\0gpio91\0gpio92"; | |
| function = "qup4"; | |
| }; | |
| }; | |
| qup-spi5-default { | |
| phandle = <0x46>; | |
| pinmux { | |
| pins = "gpio85\0gpio86\0gpio87\0gpio88"; | |
| function = "qup5"; | |
| }; | |
| }; | |
| qup-spi6-default { | |
| phandle = <0x49>; | |
| pinmux { | |
| pins = "gpio45\0gpio46\0gpio47\0gpio48"; | |
| function = "qup6"; | |
| }; | |
| }; | |
| qup-spi7-default { | |
| phandle = <0x50>; | |
| pinmux { | |
| pins = "gpio93\0gpio94\0gpio95\0gpio96"; | |
| function = "qup7"; | |
| }; | |
| }; | |
| qup-spi8-default { | |
| phandle = <0x54>; | |
| pinmux { | |
| pins = "gpio65\0gpio66\0gpio67\0gpio68"; | |
| function = "qup8"; | |
| }; | |
| }; | |
| qup-spi9-default { | |
| phandle = <0x57>; | |
| pinmux { | |
| pins = "gpio6\0gpio7\0gpio4\0gpio5"; | |
| function = "qup9"; | |
| }; | |
| }; | |
| qup-spi10-default { | |
| phandle = <0x5a>; | |
| pinmux { | |
| pins = "gpio55\0gpio56\0gpio53\0gpio54"; | |
| function = "qup10"; | |
| }; | |
| }; | |
| qup-spi11-default { | |
| phandle = <0x5d>; | |
| pinmux { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| function = "qup11"; | |
| }; | |
| }; | |
| qup-spi12-default { | |
| phandle = <0x64>; | |
| pinmux { | |
| pins = "gpio49\0gpio50\0gpio51\0gpio52"; | |
| function = "qup12"; | |
| }; | |
| }; | |
| qup-spi13-default { | |
| phandle = <0x67>; | |
| pinmux { | |
| pins = "gpio105\0gpio106\0gpio107\0gpio108"; | |
| function = "qup13"; | |
| }; | |
| }; | |
| qup-spi14-default { | |
| phandle = <0x6a>; | |
| pinmux { | |
| pins = "gpio33\0gpio34\0gpio31\0gpio32"; | |
| function = "qup14"; | |
| }; | |
| }; | |
| qup-spi15-default { | |
| phandle = <0x6d>; | |
| pinmux { | |
| pins = "gpio81\0gpio82\0gpio83\0gpio84"; | |
| function = "qup15"; | |
| }; | |
| }; | |
| qup-uart0-default { | |
| phandle = <0x38>; | |
| pinmux { | |
| pins = "gpio2\0gpio3"; | |
| function = "qup0"; | |
| }; | |
| }; | |
| qup-uart1-default { | |
| phandle = <0x3b>; | |
| pinmux { | |
| pins = "gpio19\0gpio20"; | |
| function = "qup1"; | |
| }; | |
| }; | |
| qup-uart2-default { | |
| phandle = <0x3e>; | |
| pinmux { | |
| pins = "gpio29\0gpio30"; | |
| function = "qup2"; | |
| }; | |
| }; | |
| qup-uart3-default { | |
| phandle = <0x41>; | |
| pinmux { | |
| pins = "gpio43\0gpio44"; | |
| function = "qup3"; | |
| }; | |
| }; | |
| qup-uart4-default { | |
| phandle = <0x44>; | |
| pinmux { | |
| pins = "gpio91\0gpio92"; | |
| function = "qup4"; | |
| }; | |
| }; | |
| qup-uart5-default { | |
| phandle = <0x47>; | |
| pinmux { | |
| pins = "gpio87\0gpio88"; | |
| function = "qup5"; | |
| }; | |
| }; | |
| qup-uart6-default { | |
| phandle = <0x4a>; | |
| pinmux { | |
| pins = "gpio45\0gpio46\0gpio47\0gpio48"; | |
| function = "qup6"; | |
| }; | |
| cts { | |
| pins = "gpio45"; | |
| bias-pull-down; | |
| }; | |
| rts-tx { | |
| pins = "gpio46\0gpio47"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| rx { | |
| pins = "gpio48"; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qup-uart7-default { | |
| phandle = <0x51>; | |
| pinmux { | |
| pins = "gpio95\0gpio96"; | |
| function = "qup7"; | |
| }; | |
| }; | |
| qup-uart8-default { | |
| phandle = <0x55>; | |
| pinmux { | |
| pins = "gpio67\0gpio68"; | |
| function = "qup8"; | |
| }; | |
| }; | |
| qup-uart9-default { | |
| phandle = <0x58>; | |
| pinmux { | |
| pins = "gpio4\0gpio5"; | |
| function = "qup9"; | |
| }; | |
| pinconf-tx { | |
| pins = "gpio4"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| pinconf-rx { | |
| pins = "gpio5"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qup-uart10-default { | |
| phandle = <0x5b>; | |
| pinmux { | |
| pins = "gpio53\0gpio54"; | |
| function = "qup10"; | |
| }; | |
| }; | |
| qup-uart11-default { | |
| phandle = <0x5e>; | |
| pinmux { | |
| pins = "gpio33\0gpio34"; | |
| function = "qup11"; | |
| }; | |
| }; | |
| qup-uart12-default { | |
| phandle = <0x65>; | |
| pinmux { | |
| pins = "gpio51\0gpio52"; | |
| function = "qup12"; | |
| }; | |
| }; | |
| qup-uart13-default { | |
| phandle = <0x68>; | |
| pinmux { | |
| pins = "gpio107\0gpio108"; | |
| function = "qup13"; | |
| }; | |
| }; | |
| qup-uart14-default { | |
| phandle = <0x6b>; | |
| pinmux { | |
| pins = "gpio31\0gpio32"; | |
| function = "qup14"; | |
| }; | |
| }; | |
| qup-uart15-default { | |
| phandle = <0x6e>; | |
| pinmux { | |
| pins = "gpio83\0gpio84"; | |
| function = "qup15"; | |
| }; | |
| }; | |
| quat_mi2s_sleep { | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_active { | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "qua_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| quat_mi2s_sd0_sleep { | |
| mux { | |
| pins = "gpio60"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio60"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd0_active { | |
| mux { | |
| pins = "gpio60"; | |
| function = "qua_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio60"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| quat_mi2s_sd1_sleep { | |
| mux { | |
| pins = "gpio61"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio61"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd1_active { | |
| mux { | |
| pins = "gpio61"; | |
| function = "qua_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio61"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| quat_mi2s_sd2_sleep { | |
| mux { | |
| pins = "gpio62"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio62"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd2_active { | |
| mux { | |
| pins = "gpio62"; | |
| function = "qua_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio62"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| quat_mi2s_sd3_sleep { | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| quat_mi2s_sd3_active { | |
| mux { | |
| pins = "gpio63"; | |
| function = "qua_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| tri_state_key_default { | |
| mux { | |
| pins = "gpio40\0gpio42\0gpio26"; | |
| function = "gpio"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| }; | |
| }; | |
| ts-int { | |
| phandle = <0x61>; | |
| mux { | |
| pins = "gpio99\0gpio125"; | |
| function = "gpio"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| panel-reset { | |
| phandle = <0xc3>; | |
| mux { | |
| pins = "gpio6\0gpio25\0gpio26"; | |
| function = "gpio"; | |
| drive-strength = <0x08>; | |
| bias-disable = <0x00>; | |
| }; | |
| }; | |
| panel-te { | |
| phandle = <0xc4>; | |
| mux { | |
| pins = "gpio10"; | |
| function = "mdp_vsync"; | |
| drive-strength = <0x02>; | |
| bias-disable; | |
| input-enable; | |
| }; | |
| }; | |
| panel-esd { | |
| phandle = <0xc5>; | |
| mux { | |
| pins = "gpio30"; | |
| function = "gpio"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| remoteproc@4080000 { | |
| compatible = "qcom,sdm845-mss-pil"; | |
| reg = <0x00 0x4080000 0x00 0x408 0x00 0x4180000 0x00 0x48>; | |
| reg-names = "qdsp6\0rmb"; | |
| interrupts-extended = <0x01 0x00 0x10a 0x01 0x7b 0x00 0x01 0x7b 0x01 0x01 0x7b 0x02 0x01 0x7b 0x03 0x01 0x7b 0x07 0x01>; | |
| interrupt-names = "wdog\0fatal\0ready\0handover\0stop-ack\0shutdown-ack"; | |
| clocks = <0x2d 0x24 0x2d 0x27 0x2d 0x05 0x2d 0x25 0x2d 0x28 0x2d 0x26 0x2d 0x40 0x1f 0x00>; | |
| clock-names = "iface\0bus\0mem\0gpll0_mss\0snoc_axi\0mnoc_axi\0prng\0xo"; | |
| qcom,smem-states = <0x7c 0x00>; | |
| qcom,smem-state-names = "stop"; | |
| resets = <0x7d 0x00 0x7e 0x09>; | |
| reset-names = "mss_restart\0pdc_reset"; | |
| qcom,halt-regs = <0x27 0x23000 0x25000 0x24000>; | |
| power-domains = <0x7f 0x02 0x35 0x03 0x35 0x01 0x35 0x08>; | |
| power-domain-names = "load_state\0cx\0mx\0mss"; | |
| status = "okay"; | |
| firmware-name = "qcom/sdm845/oneplus6/mba.mbn\0qcom/sdm845/oneplus6/modem.mbn"; | |
| mba { | |
| memory-region = <0x80>; | |
| }; | |
| mpss { | |
| memory-region = <0x81>; | |
| }; | |
| glink-edge { | |
| interrupts = <0x00 0x1c1 0x01>; | |
| label = "modem"; | |
| qcom,remote-pid = <0x01>; | |
| mboxes = <0x22 0x0c>; | |
| }; | |
| }; | |
| clock-controller@5090000 { | |
| compatible = "qcom,sdm845-gpucc"; | |
| reg = <0x00 0x5090000 0x00 0x9000>; | |
| #clock-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| #power-domain-cells = <0x01>; | |
| clocks = <0x1f 0x00 0x2d 0x1f 0x2d 0x20>; | |
| clock-names = "bi_tcxo\0gcc_gpu_gpll0_clk_src\0gcc_gpu_gpll0_div_clk_src"; | |
| phandle = <0xcd>; | |
| }; | |
| stm@6002000 { | |
| compatible = "arm,coresight-stm\0arm,primecell"; | |
| reg = <0x00 0x6002000 0x00 0x1000 0x00 0x16280000 0x00 0x180000>; | |
| reg-names = "stm-base\0stm-stimulus-base"; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x82>; | |
| phandle = <0x84>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6041000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x6041000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x83>; | |
| phandle = <0x88>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x84>; | |
| phandle = <0x82>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6043000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x6043000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x85>; | |
| phandle = <0x89>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x86>; | |
| phandle = <0xa0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6045000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x6045000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x87>; | |
| phandle = <0x8d>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x88>; | |
| phandle = <0x83>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x89>; | |
| phandle = <0x85>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| replicator@6046000 { | |
| compatible = "arm,coresight-dynamic-replicator\0arm,primecell"; | |
| reg = <0x00 0x6046000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8a>; | |
| phandle = <0x8e>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8b>; | |
| phandle = <0x8c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etf@6047000 { | |
| compatible = "arm,coresight-tmc\0arm,primecell"; | |
| reg = <0x00 0x6047000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8c>; | |
| phandle = <0x8b>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x8d>; | |
| phandle = <0x87>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etr@6048000 { | |
| compatible = "arm,coresight-tmc\0arm,primecell"; | |
| reg = <0x00 0x6048000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,scatter-gather; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8e>; | |
| phandle = <0x8a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7040000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7040000 0x00 0x1000>; | |
| cpu = <0x16>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8f>; | |
| phandle = <0x98>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7140000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7140000 0x00 0x1000>; | |
| cpu = <0x17>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x90>; | |
| phandle = <0x99>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7240000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7240000 0x00 0x1000>; | |
| cpu = <0x18>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x91>; | |
| phandle = <0x9a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7340000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7340000 0x00 0x1000>; | |
| cpu = <0x19>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x92>; | |
| phandle = <0x9b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7440000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7440000 0x00 0x1000>; | |
| cpu = <0x1a>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x93>; | |
| phandle = <0x9c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7540000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7540000 0x00 0x1000>; | |
| cpu = <0x1b>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x94>; | |
| phandle = <0x9d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7640000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7640000 0x00 0x1000>; | |
| cpu = <0x1c>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x95>; | |
| phandle = <0x9e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7740000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x7740000 0x00 0x1000>; | |
| cpu = <0x1d>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| arm,coresight-loses-context-with-cpu; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x96>; | |
| phandle = <0x9f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@7800000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x7800000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x97>; | |
| phandle = <0xa1>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x98>; | |
| phandle = <0x8f>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x99>; | |
| phandle = <0x90>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x9a>; | |
| phandle = <0x91>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x9b>; | |
| phandle = <0x92>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x9c>; | |
| phandle = <0x93>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x9d>; | |
| phandle = <0x94>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x9e>; | |
| phandle = <0x95>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x9f>; | |
| phandle = <0x96>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@7810000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x7810000 0x00 0x1000>; | |
| clocks = <0x7f>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa0>; | |
| phandle = <0x86>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xa1>; | |
| phandle = <0x97>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| sdhci@8804000 { | |
| compatible = "qcom,sdm845-sdhci\0qcom,sdhci-msm-v5"; | |
| reg = <0x00 0x8804000 0x00 0x1000>; | |
| interrupts = <0x00 0xcc 0x04 0x00 0xde 0x04>; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| clocks = <0x2d 0x68 0x2d 0x69>; | |
| clock-names = "iface\0core"; | |
| iommus = <0x23 0xa0 0x0f>; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0xa2>; | |
| status = "disabled"; | |
| sdhc2-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xa2>; | |
| opp-9600000 { | |
| opp-hz = <0x00 0x927c00>; | |
| required-opps = <0x2e>; | |
| }; | |
| opp-19200000 { | |
| opp-hz = <0x00 0x124f800>; | |
| required-opps = <0x2f>; | |
| }; | |
| opp-100000000 { | |
| opp-hz = <0x00 0x5f5e100>; | |
| required-opps = <0x30>; | |
| }; | |
| opp-201500000 { | |
| opp-hz = <0x00 0xc02a560>; | |
| required-opps = <0xa3>; | |
| }; | |
| }; | |
| }; | |
| qspi-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xa4>; | |
| opp-19200000 { | |
| opp-hz = <0x00 0x124f800>; | |
| required-opps = <0x2e>; | |
| }; | |
| opp-100000000 { | |
| opp-hz = <0x00 0x5f5e100>; | |
| required-opps = <0x2f>; | |
| }; | |
| opp-150000000 { | |
| opp-hz = <0x00 0x8f0d180>; | |
| required-opps = <0x30>; | |
| }; | |
| opp-300000000 { | |
| opp-hz = <0x00 0x11e1a300>; | |
| required-opps = <0x31>; | |
| }; | |
| }; | |
| spi@88df000 { | |
| compatible = "qcom,sdm845-qspi\0qcom,qspi-v1"; | |
| reg = <0x00 0x88df000 0x00 0x600>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interrupts = <0x00 0x52 0x04>; | |
| clocks = <0x2d 0xbd 0x2d 0xbc>; | |
| clock-names = "iface\0core"; | |
| power-domains = <0x35 0x03>; | |
| operating-points-v2 = <0xa4>; | |
| status = "disabled"; | |
| }; | |
| slim@171c0000 { | |
| compatible = "qcom,slim-ngd-v2.1.0"; | |
| reg = <0x00 0x171c0000 0x00 0x2c000>; | |
| interrupts = <0x00 0xa3 0x04>; | |
| qcom,apps-ch-pipes = <0x780000>; | |
| qcom,ea-pc = <0x270>; | |
| status = "okay"; | |
| dmas = <0xa5 0x03 0xa5 0x04 0xa5 0x05 0xa5 0x06>; | |
| dma-names = "rx\0tx\0tx2\0rx2"; | |
| iommus = <0x23 0x1806 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| ngd@1 { | |
| reg = <0x01>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| ifd@0 { | |
| compatible = "slim217,250"; | |
| reg = <0x00 0x00>; | |
| phandle = <0xa6>; | |
| }; | |
| codec@1 { | |
| compatible = "slim217,250"; | |
| reg = <0x01 0x00>; | |
| slim-ifc-dev = <0xa6>; | |
| #sound-dai-cells = <0x01>; | |
| interrupts-extended = <0x60 0x36 0x04>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x01>; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x927c00>; | |
| clock-output-names = "mclk"; | |
| qcom,micbias1-millivolt = <0x708>; | |
| qcom,micbias2-millivolt = <0x708>; | |
| qcom,micbias3-millivolt = <0x708>; | |
| qcom,micbias4-millivolt = <0x708>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0xa7>; | |
| gpio-controller@42 { | |
| compatible = "qcom,wcd9340-gpio"; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| reg = <0x42 0x02>; | |
| }; | |
| swm@c85 { | |
| compatible = "qcom,soundwire-v1.3.0"; | |
| reg = <0xc85 0x40>; | |
| interrupts-extended = <0xa7 0x14>; | |
| qcom,dout-ports = <0x06>; | |
| qcom,din-ports = <0x02>; | |
| qcom,ports-sinterval-low = <0x71f3f07 0x1f3f0f0f>; | |
| qcom,ports-offset1 = <0x1020c06 0x120d070a>; | |
| qcom,ports-offset2 = <0x1f00 0x1f0000>; | |
| #sound-dai-cells = <0x01>; | |
| clocks = <0xa7>; | |
| clock-names = "iface"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| sound { | |
| }; | |
| phy@88e2000 { | |
| compatible = "qcom,sdm845-qusb2-phy\0qcom,qusb2-v2-phy"; | |
| reg = <0x00 0x88e2000 0x00 0x400>; | |
| status = "okay"; | |
| #phy-cells = <0x00>; | |
| clocks = <0x2d 0xa1 0x1f 0x00>; | |
| clock-names = "cfg_ahb\0ref"; | |
| resets = <0x2d 0x08>; | |
| nvmem-cells = <0xa8>; | |
| vdd-supply = <0x73>; | |
| vdda-pll-supply = <0xa9>; | |
| vdda-phy-dpdm-supply = <0xaa>; | |
| qcom,imp-res-offset-value = <0x08>; | |
| qcom,hstx-trim-value = <0x04>; | |
| qcom,preemphasis-level = <0x01>; | |
| qcom,preemphasis-width = <0x01>; | |
| phandle = <0xac>; | |
| }; | |
| phy@88e3000 { | |
| compatible = "qcom,sdm845-qusb2-phy\0qcom,qusb2-v2-phy"; | |
| reg = <0x00 0x88e3000 0x00 0x400>; | |
| status = "disabled"; | |
| #phy-cells = <0x00>; | |
| clocks = <0x2d 0xa1 0x1f 0x00>; | |
| clock-names = "cfg_ahb\0ref"; | |
| resets = <0x2d 0x09>; | |
| nvmem-cells = <0xab>; | |
| phandle = <0xad>; | |
| }; | |
| phy@88e9000 { | |
| compatible = "qcom,sdm845-qmp-usb3-phy"; | |
| reg = <0x00 0x88e9000 0x00 0x18c 0x00 0x88e8000 0x00 0x10>; | |
| reg-names = "reg-base\0dp_com"; | |
| status = "disabled"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| clocks = <0x2d 0x98 0x2d 0xa1 0x2d 0x97 0x2d 0x9a>; | |
| clock-names = "aux\0cfg_ahb\0ref\0com_aux"; | |
| resets = <0x2d 0x13 0x2d 0x11>; | |
| reset-names = "phy\0common"; | |
| lanes@88e9200 { | |
| reg = <0x00 0x88e9200 0x00 0x128 0x00 0x88e9400 0x00 0x200 0x00 0x88e9c00 0x00 0x218 0x00 0x88e9600 0x00 0x128 0x00 0x88e9800 0x00 0x200 0x00 0x88e9a00 0x00 0x100>; | |
| #clock-cells = <0x00>; | |
| #phy-cells = <0x00>; | |
| clocks = <0x2d 0x9b>; | |
| clock-names = "pipe0"; | |
| clock-output-names = "usb3_phy_pipe_clk_src"; | |
| }; | |
| }; | |
| phy@88eb000 { | |
| compatible = "qcom,sdm845-qmp-usb3-uni-phy"; | |
| reg = <0x00 0x88eb000 0x00 0x18c>; | |
| status = "disabled"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| clocks = <0x2d 0x9d 0x2d 0xa1 0x2d 0x9c 0x2d 0xa0>; | |
| clock-names = "aux\0cfg_ahb\0ref\0com_aux"; | |
| resets = <0x2d 0x15 0x2d 0x14>; | |
| reset-names = "phy\0common"; | |
| lane@88eb200 { | |
| reg = <0x00 0x88eb200 0x00 0x128 0x00 0x88eb400 0x00 0x1fc 0x00 0x88eb800 0x00 0x218 0x00 0x88eb600 0x00 0x70>; | |
| #clock-cells = <0x00>; | |
| #phy-cells = <0x00>; | |
| clocks = <0x2d 0x9f>; | |
| clock-names = "pipe0"; | |
| clock-output-names = "usb3_uni_phy_pipe_clk_src"; | |
| phandle = <0xae>; | |
| }; | |
| }; | |
| usb@a6f8800 { | |
| compatible = "qcom,sdm845-dwc3\0qcom,dwc3"; | |
| reg = <0x00 0xa6f8800 0x00 0x400>; | |
| status = "okay"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| dma-ranges; | |
| clocks = <0x2d 0x0c 0x2d 0x8d 0x2d 0x03 0x2d 0x8f 0x2d 0x91>; | |
| clock-names = "cfg_noc\0core\0iface\0mock_utmi\0sleep"; | |
| assigned-clocks = <0x2d 0x8f 0x2d 0x8d>; | |
| assigned-clock-rates = <0x124f800 0x8f0d180>; | |
| interrupts = <0x00 0x83 0x04 0x00 0x1e6 0x04 0x00 0x1e8 0x04 0x00 0x1e9 0x04>; | |
| interrupt-names = "hs_phy_irq\0ss_phy_irq\0dm_hs_phy_irq\0dp_hs_phy_irq"; | |
| power-domains = <0x2d 0x04>; | |
| resets = <0x2d 0x0f>; | |
| interconnects = <0x52 0x07 0x00 0x08 0x0e 0x00 0x07 0x00 0x00 0x33 0x29 0x00>; | |
| interconnect-names = "usb-ddr\0apps-usb"; | |
| qcom,select-utmi-as-pipe-clk; | |
| dwc3@a600000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x00 0xa600000 0x00 0xcd00>; | |
| interrupts = <0x00 0x85 0x04>; | |
| iommus = <0x23 0x740 0x00>; | |
| snps,dis_u2_susphy_quirk; | |
| snps,dis_enblslpm_quirk; | |
| phys = <0xac>; | |
| phy-names = "usb2-phy"; | |
| dr_mode = "peripheral"; | |
| maximum-speed = "high-speed"; | |
| }; | |
| }; | |
| usb@a8f8800 { | |
| compatible = "qcom,sdm845-dwc3\0qcom,dwc3"; | |
| reg = <0x00 0xa8f8800 0x00 0x400>; | |
| status = "disabled"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| dma-ranges; | |
| clocks = <0x2d 0x0d 0x2d 0x92 0x2d 0x04 0x2d 0x94 0x2d 0x96>; | |
| clock-names = "cfg_noc\0core\0iface\0mock_utmi\0sleep"; | |
| assigned-clocks = <0x2d 0x94 0x2d 0x92>; | |
| assigned-clock-rates = <0x124f800 0x8f0d180>; | |
| interrupts = <0x00 0x88 0x04 0x00 0x1e7 0x04 0x00 0x1ea 0x04 0x00 0x1eb 0x04>; | |
| interrupt-names = "hs_phy_irq\0ss_phy_irq\0dm_hs_phy_irq\0dp_hs_phy_irq"; | |
| power-domains = <0x2d 0x05>; | |
| resets = <0x2d 0x10>; | |
| interconnects = <0x52 0x08 0x00 0x08 0x0e 0x00 0x07 0x00 0x00 0x33 0x2a 0x00>; | |
| interconnect-names = "usb-ddr\0apps-usb"; | |
| dwc3@a800000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x00 0xa800000 0x00 0xcd00>; | |
| interrupts = <0x00 0x8a 0x04>; | |
| iommus = <0x23 0x760 0x00>; | |
| snps,dis_u2_susphy_quirk; | |
| snps,dis_enblslpm_quirk; | |
| phys = <0xad 0xae>; | |
| phy-names = "usb2-phy\0usb3-phy"; | |
| }; | |
| }; | |
| video-codec@aa00000 { | |
| compatible = "qcom,sdm845-venus-v2"; | |
| reg = <0x00 0xaa00000 0x00 0xff000>; | |
| interrupts = <0x00 0xae 0x04>; | |
| power-domains = <0xaf 0x00 0xaf 0x01 0xaf 0x02 0x35 0x03>; | |
| power-domain-names = "venus\0vcodec0\0vcodec1\0cx"; | |
| operating-points-v2 = <0xb0>; | |
| clocks = <0xaf 0x0b 0xaf 0x08 0xaf 0x0a 0xaf 0x05 0xaf 0x04 0xaf 0x07 0xaf 0x06>; | |
| clock-names = "core\0iface\0bus\0vcodec0_core\0vcodec0_bus\0vcodec1_core\0vcodec1_bus"; | |
| iommus = <0x23 0x10a0 0x08 0x23 0x10b0 0x00>; | |
| memory-region = <0xb1>; | |
| interconnects = <0xb2 0x07 0x00 0x08 0x0e 0x00 0x07 0x00 0x00 0x33 0x2b 0x00>; | |
| interconnect-names = "video-mem\0cpu-cfg"; | |
| video-core0 { | |
| compatible = "venus-decoder"; | |
| }; | |
| video-core1 { | |
| compatible = "venus-encoder"; | |
| }; | |
| venus-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xb0>; | |
| opp-100000000 { | |
| opp-hz = <0x00 0x5f5e100>; | |
| required-opps = <0x2e>; | |
| }; | |
| opp-200000000 { | |
| opp-hz = <0x00 0xbebc200>; | |
| required-opps = <0x2f>; | |
| }; | |
| opp-320000000 { | |
| opp-hz = <0x00 0x1312d000>; | |
| required-opps = <0x30>; | |
| }; | |
| opp-380000000 { | |
| opp-hz = <0x00 0x16a65700>; | |
| required-opps = <0xa3>; | |
| }; | |
| opp-444000000 { | |
| opp-hz = <0x00 0x1a76e700>; | |
| required-opps = <0x31>; | |
| }; | |
| opp-533000097 { | |
| opp-hz = <0x00 0x1fc4efa1>; | |
| required-opps = <0xb3>; | |
| }; | |
| }; | |
| }; | |
| clock-controller@ab00000 { | |
| compatible = "qcom,sdm845-videocc"; | |
| reg = <0x00 0xab00000 0x00 0x10000>; | |
| clocks = <0x1f 0x00>; | |
| clock-names = "bi_tcxo"; | |
| #clock-cells = <0x01>; | |
| #power-domain-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| phandle = <0xaf>; | |
| }; | |
| camss@a00000 { | |
| compatible = "qcom,sdm845-camss"; | |
| reg = <0x00 0xacb3000 0x00 0x1000 0x00 0xacba000 0x00 0x1000 0x00 0xacc8000 0x00 0x1000 0x00 0xac65000 0x00 0x1000 0x00 0xac66000 0x00 0x1000 0x00 0xac67000 0x00 0x1000 0x00 0xac68000 0x00 0x1000 0x00 0xacaf000 0x00 0x4000 0x00 0xacb6000 0x00 0x4000 0x00 0xacc4000 0x00 0x4000>; | |
| reg-names = "csid0\0csid1\0csid2\0csiphy0\0csiphy1\0csiphy2\0csiphy3\0vfe0\0vfe1\0vfe_lite"; | |
| interrupts = <0x00 0x1d0 0x04 0x00 0x1d2 0x04 0x00 0x1d4 0x04 0x00 0x1dd 0x04 0x00 0x1de 0x04 0x00 0x1df 0x04 0x00 0x1c0 0x04 0x00 0x1d1 0x04 0x00 0x1d3 0x04 0x00 0x1d5 0x04>; | |
| interrupt-names = "csid0\0csid1\0csid2\0csiphy0\0csiphy1\0csiphy2\0csiphy3\0vfe0\0vfe1\0vfe_lite"; | |
| power-domains = <0xb4 0x03 0xb4 0x04 0xb4 0x05>; | |
| clocks = <0xb4 0x06 0xb4 0x09 0xb4 0x0a 0xb4 0x25 0xb4 0x26 0xb4 0x2c 0xb4 0x2d 0xb4 0x32 0xb4 0x33 0xb4 0x13 0xb4 0x0b 0xb4 0x0c 0xb4 0x14 0xb4 0x0d 0xb4 0x0e 0xb4 0x15 0xb4 0x0f 0xb4 0x10 0xb4 0x16 0xb4 0x11 0xb4 0x12 0x2d 0x06 0x2d 0x07 0xb4 0x52 0xb4 0x53 0xb4 0x21 0xb4 0x22 0xb4 0x24 0xb4 0x23 0xb4 0x28 0xb4 0x29 0xb4 0x2b 0xb4 0x2a 0xb4 0x2f 0xb4 0x31 0xb4 0x30>; | |
| clock-names = "camnoc_axi\0cpas_ahb\0cphy_rx_src\0csi0\0csi0_src\0csi1\0csi1_src\0csi2\0csi2_src\0csiphy0\0csiphy0_timer\0csiphy0_timer_src\0csiphy1\0csiphy1_timer\0csiphy1_timer_src\0csiphy2\0csiphy2_timer\0csiphy2_timer_src\0csiphy3\0csiphy3_timer\0csiphy3_timer_src\0gcc_camera_ahb\0gcc_camera_axi\0slow_ahb_src\0soc_ahb\0vfe0_axi\0vfe0\0vfe0_cphy_rx\0vfe0_src\0vfe1_axi\0vfe1\0vfe1_cphy_rx\0vfe1_src\0vfe_lite\0vfe_lite_cphy_rx\0vfe_lite_src"; | |
| iommus = <0x23 0x808 0x00 0x23 0x810 0x08 0x23 0xc08 0x00 0x23 0xc10 0x08>; | |
| status = "disabled"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| }; | |
| cci@ac4a000 { | |
| compatible = "qcom,sdm845-cci"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0xac4a000 0x00 0x4000>; | |
| interrupts = <0x00 0x1cc 0x01>; | |
| power-domains = <0xb4 0x05>; | |
| clocks = <0xb4 0x06 0xb4 0x53 0xb4 0x52 0xb4 0x09 0xb4 0x07 0xb4 0x08>; | |
| clock-names = "camnoc_axi\0soc_ahb\0slow_ahb_src\0cpas_ahb\0cci\0cci_src"; | |
| assigned-clocks = <0xb4 0x06 0xb4 0x07>; | |
| assigned-clock-rates = <0x4c4b400 0x23c3460>; | |
| pinctrl-names = "default\0sleep"; | |
| pinctrl-0 = <0xb5 0xb6>; | |
| pinctrl-1 = <0xb7 0xb8>; | |
| status = "disabled"; | |
| i2c-bus@0 { | |
| reg = <0x00>; | |
| clock-frequency = <0xf4240>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| i2c-bus@1 { | |
| reg = <0x01>; | |
| clock-frequency = <0xf4240>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| }; | |
| clock-controller@ad00000 { | |
| compatible = "qcom,sdm845-camcc"; | |
| reg = <0x00 0xad00000 0x00 0x10000>; | |
| #clock-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| #power-domain-cells = <0x01>; | |
| phandle = <0xb4>; | |
| }; | |
| dsi-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xbf>; | |
| opp-19200000 { | |
| opp-hz = <0x00 0x124f800>; | |
| required-opps = <0x2e>; | |
| }; | |
| opp-180000000 { | |
| opp-hz = <0x00 0xaba9500>; | |
| required-opps = <0x2f>; | |
| }; | |
| opp-275000000 { | |
| opp-hz = <0x00 0x10642ac0>; | |
| required-opps = <0x30>; | |
| }; | |
| opp-328580000 { | |
| opp-hz = <0x00 0x1395bba0>; | |
| required-opps = <0xa3>; | |
| }; | |
| opp-358000000 { | |
| opp-hz = <0x00 0x1556a580>; | |
| required-opps = <0x31>; | |
| }; | |
| }; | |
| mdss@ae00000 { | |
| compatible = "qcom,sdm845-mdss"; | |
| reg = <0x00 0xae00000 0x00 0x1000>; | |
| reg-names = "mdss"; | |
| power-domains = <0xb9 0x00>; | |
| clocks = <0x2d 0x13 0xb9 0x0c>; | |
| clock-names = "iface\0core"; | |
| assigned-clocks = <0xb9 0x0c>; | |
| assigned-clock-rates = <0x11e1a300>; | |
| interrupts = <0x00 0x53 0x04>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x01>; | |
| interconnects = <0xb2 0x04 0x00 0x08 0x0e 0x00 0xb2 0x05 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "mdp0-mem\0mdp1-mem"; | |
| iommus = <0x23 0x880 0x08 0x23 0xc80 0x08>; | |
| status = "okay"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| phandle = <0xbb>; | |
| mdp@ae01000 { | |
| compatible = "qcom,sdm845-dpu"; | |
| reg = <0x00 0xae01000 0x00 0x8f000 0x00 0xaeb0000 0x00 0x2008>; | |
| reg-names = "mdp\0vbif"; | |
| clocks = <0x2d 0x14 0xb9 0x00 0xb9 0x01 0xb9 0x0c 0xb9 0x17>; | |
| clock-names = "gcc-bus\0iface\0bus\0core\0vsync"; | |
| assigned-clocks = <0xb9 0x0c 0xb9 0x17>; | |
| assigned-clock-rates = <0x11e1a300 0x124f800>; | |
| operating-points-v2 = <0xba>; | |
| power-domains = <0x35 0x03>; | |
| interrupt-parent = <0xbb>; | |
| interrupts = <0x00 0x04>; | |
| status = "okay"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xbc>; | |
| phandle = <0xc0>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xbd>; | |
| phandle = <0xc8>; | |
| }; | |
| }; | |
| }; | |
| mdp-opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xba>; | |
| opp-19200000 { | |
| opp-hz = <0x00 0x124f800>; | |
| required-opps = <0x2e>; | |
| }; | |
| opp-171428571 { | |
| opp-hz = <0x00 0xa37cadb>; | |
| required-opps = <0x2f>; | |
| }; | |
| opp-344000000 { | |
| opp-hz = <0x00 0x14810600>; | |
| required-opps = <0xa3>; | |
| }; | |
| opp-430000000 { | |
| opp-hz = <0x00 0x19a14780>; | |
| required-opps = <0x31>; | |
| }; | |
| }; | |
| }; | |
| dsi@ae94000 { | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| reg = <0x00 0xae94000 0x00 0x400>; | |
| reg-names = "dsi_ctrl"; | |
| interrupt-parent = <0xbb>; | |
| interrupts = <0x04 0x04>; | |
| clocks = <0xb9 0x02 0xb9 0x04 0xb9 0x0f 0xb9 0x08 0xb9 0x00 0xb9 0x01>; | |
| clock-names = "byte\0byte_intf\0pixel\0core\0iface\0bus"; | |
| assigned-clocks = <0xb9 0x03 0xb9 0x10>; | |
| assigned-clock-parents = <0xbe 0x00 0xbe 0x01>; | |
| operating-points-v2 = <0xbf>; | |
| power-domains = <0x35 0x03>; | |
| phys = <0xbe>; | |
| phy-names = "dsi"; | |
| status = "okay"; | |
| vdda-supply = <0x74>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xc0>; | |
| phandle = <0xbc>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0xc1>; | |
| data-lanes = <0x00 0x01 0x02 0x03>; | |
| phandle = <0xc6>; | |
| }; | |
| }; | |
| }; | |
| panel@0 { | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| vddio-supply = <0xc2>; | |
| reset-gpios = <0x60 0x06 0x01>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xc3 0xc4 0xc5>; | |
| compatible = "samsung,s6e3fc2x01"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0xc6>; | |
| phandle = <0xc1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi-phy@ae94400 { | |
| compatible = "qcom,dsi-phy-10nm"; | |
| reg = <0x00 0xae94400 0x00 0x200 0x00 0xae94600 0x00 0x280 0x00 0xae94a00 0x00 0x1e0>; | |
| reg-names = "dsi_phy\0dsi_phy_lane\0dsi_pll"; | |
| #clock-cells = <0x01>; | |
| #phy-cells = <0x00>; | |
| clocks = <0xb9 0x00 0x1f 0x00>; | |
| clock-names = "iface\0ref"; | |
| status = "okay"; | |
| vdds-supply = <0x73>; | |
| phandle = <0xbe>; | |
| }; | |
| dsi@ae96000 { | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| reg = <0x00 0xae96000 0x00 0x400>; | |
| reg-names = "dsi_ctrl"; | |
| interrupt-parent = <0xbb>; | |
| interrupts = <0x05 0x04>; | |
| clocks = <0xb9 0x05 0xb9 0x07 0xb9 0x11 0xb9 0x0a 0xb9 0x00 0xb9 0x01>; | |
| clock-names = "byte\0byte_intf\0pixel\0core\0iface\0bus"; | |
| assigned-clocks = <0xb9 0x06 0xb9 0x12>; | |
| assigned-clock-parents = <0xc7 0x00 0xc7 0x01>; | |
| operating-points-v2 = <0xbf>; | |
| power-domains = <0x35 0x03>; | |
| phys = <0xc7>; | |
| phy-names = "dsi"; | |
| status = "disabled"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0xc8>; | |
| phandle = <0xbd>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi-phy@ae96400 { | |
| compatible = "qcom,dsi-phy-10nm"; | |
| reg = <0x00 0xae96400 0x00 0x200 0x00 0xae96600 0x00 0x280 0x00 0xae96a00 0x00 0x10e>; | |
| reg-names = "dsi_phy\0dsi_phy_lane\0dsi_pll"; | |
| #clock-cells = <0x01>; | |
| #phy-cells = <0x00>; | |
| clocks = <0xb9 0x00 0x1f 0x00>; | |
| clock-names = "iface\0ref"; | |
| status = "disabled"; | |
| phandle = <0xc7>; | |
| }; | |
| }; | |
| gpu@5000000 { | |
| compatible = "qcom,adreno-630.2\0qcom,adreno"; | |
| #stream-id-cells = <0x10>; | |
| reg = <0x00 0x5000000 0x00 0x40000 0x00 0x509e000 0x00 0x10>; | |
| reg-names = "kgsl_3d0_reg_memory\0cx_mem"; | |
| interrupts = <0x00 0x12c 0x04>; | |
| iommus = <0xc9 0x00>; | |
| operating-points-v2 = <0xca>; | |
| qcom,gmu = <0xcb>; | |
| interconnects = <0x08 0x07 0x00 0x08 0x0e 0x00>; | |
| interconnect-names = "gfx-mem"; | |
| opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xca>; | |
| opp-710000000 { | |
| opp-hz = <0x00 0x2a51bd80>; | |
| opp-level = <0x1a0>; | |
| opp-peak-kBps = <0x6e1b80>; | |
| }; | |
| opp-675000000 { | |
| opp-hz = <0x00 0x283baec0>; | |
| opp-level = <0x180>; | |
| opp-peak-kBps = <0x6e1b80>; | |
| }; | |
| opp-596000000 { | |
| opp-hz = <0x00 0x23863d00>; | |
| opp-level = <0x140>; | |
| opp-peak-kBps = <0x5ee8e0>; | |
| }; | |
| opp-520000000 { | |
| opp-hz = <0x00 0x1efe9200>; | |
| opp-level = <0x100>; | |
| opp-peak-kBps = <0x5ee8e0>; | |
| }; | |
| opp-414000000 { | |
| opp-hz = <0x00 0x18ad2380>; | |
| opp-level = <0xc0>; | |
| opp-peak-kBps = <0x3e12a0>; | |
| }; | |
| opp-342000000 { | |
| opp-hz = <0x00 0x14628180>; | |
| opp-level = <0x80>; | |
| opp-peak-kBps = <0x2990a0>; | |
| }; | |
| opp-257000000 { | |
| opp-hz = <0x00 0xf518240>; | |
| opp-level = <0x40>; | |
| opp-peak-kBps = <0x192580>; | |
| }; | |
| }; | |
| zap-shader { | |
| memory-region = <0xcc>; | |
| firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; | |
| }; | |
| }; | |
| iommu@5040000 { | |
| compatible = "qcom,sdm845-smmu-v2\0qcom,adreno-smmu\0qcom,smmu-v2"; | |
| reg = <0x00 0x5040000 0x00 0x10000>; | |
| #iommu-cells = <0x01>; | |
| #global-interrupts = <0x02>; | |
| interrupts = <0x00 0xe5 0x04 0x00 0xe7 0x04 0x00 0x16c 0x01 0x00 0x16d 0x01 0x00 0x16e 0x01 0x00 0x16f 0x01 0x00 0x170 0x01 0x00 0x171 0x01 0x00 0x172 0x01 0x00 0x173 0x01>; | |
| clocks = <0x2d 0x21 0x2d 0x1e>; | |
| clock-names = "bus\0iface"; | |
| power-domains = <0xcd 0x00>; | |
| phandle = <0xc9>; | |
| }; | |
| gmu@506a000 { | |
| compatible = "qcom,adreno-gmu-630.2\0qcom,adreno-gmu"; | |
| reg = <0x00 0x506a000 0x00 0x30000 0x00 0xb280000 0x00 0x10000 0x00 0xb480000 0x00 0x10000>; | |
| reg-names = "gmu\0gmu_pdc\0gmu_pdc_seq"; | |
| interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; | |
| interrupt-names = "hfi\0gmu"; | |
| clocks = <0xcd 0x00 0xcd 0x01 0x2d 0x12 0x2d 0x21>; | |
| clock-names = "gmu\0cxo\0axi\0memnoc"; | |
| power-domains = <0xcd 0x00 0xcd 0x01>; | |
| power-domain-names = "cx\0gx"; | |
| iommus = <0xc9 0x05>; | |
| operating-points-v2 = <0xce>; | |
| phandle = <0xcb>; | |
| opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xce>; | |
| opp-400000000 { | |
| opp-hz = <0x00 0x17d78400>; | |
| opp-level = <0x80>; | |
| }; | |
| opp-200000000 { | |
| opp-hz = <0x00 0xbebc200>; | |
| opp-level = <0x30>; | |
| }; | |
| }; | |
| }; | |
| clock-controller@af00000 { | |
| compatible = "qcom,sdm845-dispcc"; | |
| reg = <0x00 0xaf00000 0x00 0x10000>; | |
| clocks = <0x1f 0x00 0x2d 0x15 0x2d 0x16 0xbe 0x00 0xbe 0x01 0xc7 0x00 0xc7 0x01 0x00 0x00>; | |
| clock-names = "bi_tcxo\0gcc_disp_gpll0_clk_src\0gcc_disp_gpll0_div_clk_src\0dsi0_phy_pll_out_byteclk\0dsi0_phy_pll_out_dsiclk\0dsi1_phy_pll_out_byteclk\0dsi1_phy_pll_out_dsiclk\0dp_link_clk_divsel_ten\0dp_vco_divided_clk_src_mux"; | |
| #clock-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| #power-domain-cells = <0x01>; | |
| phandle = <0xb9>; | |
| }; | |
| interrupt-controller@b220000 { | |
| compatible = "qcom,sdm845-pdc\0qcom,pdc"; | |
| reg = <0x00 0xb220000 0x00 0x30000>; | |
| qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x0f 0x73 0x276 0x07>; | |
| #interrupt-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| interrupt-controller; | |
| phandle = <0x7a>; | |
| }; | |
| reset-controller@b2e0000 { | |
| compatible = "qcom,sdm845-pdc-global"; | |
| reg = <0x00 0xb2e0000 0x00 0x20000>; | |
| #reset-cells = <0x01>; | |
| phandle = <0x7e>; | |
| }; | |
| thermal-sensor@c263000 { | |
| compatible = "qcom,sdm845-tsens\0qcom,tsens-v2"; | |
| reg = <0x00 0xc263000 0x00 0x1ff 0x00 0xc222000 0x00 0x1ff>; | |
| #qcom,sensors = <0x0d>; | |
| interrupts = <0x00 0x1fa 0x04 0x00 0x1fc 0x04>; | |
| interrupt-names = "uplow\0critical"; | |
| #thermal-sensor-cells = <0x01>; | |
| phandle = <0xdb>; | |
| }; | |
| thermal-sensor@c265000 { | |
| compatible = "qcom,sdm845-tsens\0qcom,tsens-v2"; | |
| reg = <0x00 0xc265000 0x00 0x1ff 0x00 0xc223000 0x00 0x1ff>; | |
| #qcom,sensors = <0x08>; | |
| interrupts = <0x00 0x1fb 0x04 0x00 0x1fd 0x04>; | |
| interrupt-names = "uplow\0critical"; | |
| #thermal-sensor-cells = <0x01>; | |
| phandle = <0xec>; | |
| }; | |
| reset-controller@c2a0000 { | |
| compatible = "qcom,sdm845-aoss-cc"; | |
| reg = <0x00 0xc2a0000 0x00 0x31000>; | |
| #reset-cells = <0x01>; | |
| phandle = <0x7d>; | |
| }; | |
| power-controller@c300000 { | |
| compatible = "qcom,sdm845-aoss-qmp"; | |
| reg = <0x00 0xc300000 0x00 0x100000>; | |
| interrupts = <0x00 0x185 0x01>; | |
| mboxes = <0x22 0x00>; | |
| #clock-cells = <0x00>; | |
| #power-domain-cells = <0x01>; | |
| phandle = <0x7f>; | |
| cx { | |
| #cooling-cells = <0x02>; | |
| }; | |
| ebi { | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| spmi@c440000 { | |
| compatible = "qcom,spmi-pmic-arb"; | |
| reg = <0x00 0xc440000 0x00 0x1100 0x00 0xc600000 0x00 0x2000000 0x00 0xe600000 0x00 0x100000 0x00 0xe700000 0x00 0xa0000 0x00 0xc40a000 0x00 0x26000>; | |
| reg-names = "core\0chnls\0obsrvr\0intr\0cnfg"; | |
| interrupt-names = "periph_irq"; | |
| interrupts = <0x00 0x1e1 0x04>; | |
| qcom,ee = <0x00>; | |
| qcom,channel = <0x00>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x04>; | |
| cell-index = <0x00>; | |
| pmic@0 { | |
| compatible = "qcom,pm8998\0qcom,spmi-pmic"; | |
| reg = <0x00 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| pon@800 { | |
| compatible = "qcom,pm8998-pon"; | |
| reg = <0x800>; | |
| mode-bootloader = <0x02>; | |
| mode-recovery = <0x01>; | |
| pwrkey { | |
| compatible = "qcom,pm8941-pwrkey"; | |
| interrupts = <0x00 0x08 0x00 0x03>; | |
| debounce = <0x3d09>; | |
| bias-pull-up; | |
| linux,code = <0x74>; | |
| }; | |
| }; | |
| temp-alarm@2400 { | |
| compatible = "qcom,spmi-temp-alarm"; | |
| reg = <0x2400>; | |
| interrupts = <0x00 0x24 0x00 0x01>; | |
| io-channels = <0xcf 0x06>; | |
| io-channel-names = "thermal"; | |
| #thermal-sensor-cells = <0x00>; | |
| phandle = <0xed>; | |
| }; | |
| coincell@2800 { | |
| compatible = "qcom,pm8941-coincell"; | |
| reg = <0x2800>; | |
| status = "disabled"; | |
| }; | |
| adc@3100 { | |
| compatible = "qcom,spmi-adc-rev2"; | |
| reg = <0x3100>; | |
| interrupts = <0x00 0x31 0x00 0x01>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #io-channel-cells = <0x01>; | |
| phandle = <0xcf>; | |
| adc-chan@6 { | |
| reg = <0x06>; | |
| label = "die_temp"; | |
| }; | |
| }; | |
| rtc@6000 { | |
| compatible = "qcom,pm8941-rtc"; | |
| reg = <0x6000 0x6100>; | |
| reg-names = "rtc\0alarm"; | |
| interrupts = <0x00 0x61 0x01 0x01>; | |
| }; | |
| gpios@c000 { | |
| compatible = "qcom,pm8998-gpio\0qcom,spmi-gpio"; | |
| reg = <0xc000>; | |
| gpio-controller; | |
| gpio-ranges = <0xd0 0x00 0x00 0x1a>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xd0>; | |
| pm8998_gpio5 { | |
| phandle = <0xee>; | |
| pinconf { | |
| pins = "gpio5"; | |
| function = "normal"; | |
| input-enable; | |
| bias-pull-up; | |
| qcom,drive-strength = <0x00>; | |
| }; | |
| }; | |
| pm8998_gpio6 { | |
| phandle = <0xef>; | |
| pinconf { | |
| pins = "gpio6"; | |
| function = "normal"; | |
| input-enable; | |
| bias-pull-up; | |
| qcom,drive-strength = <0x00>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| pmic@1 { | |
| compatible = "qcom,pm8998\0qcom,spmi-pmic"; | |
| reg = <0x01 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| }; | |
| pmic@2 { | |
| compatible = "qcom,pmi8998\0qcom,spmi-pmic"; | |
| reg = <0x02 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| gpios@c000 { | |
| compatible = "qcom,pmi8998-gpio\0qcom,spmi-gpio"; | |
| reg = <0xc000>; | |
| gpio-controller; | |
| gpio-ranges = <0xd1 0x00 0x00 0x0e>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xd1>; | |
| }; | |
| }; | |
| pmic@3 { | |
| compatible = "qcom,pmi8998\0qcom,spmi-pmic"; | |
| reg = <0x03 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| labibb { | |
| compatible = "qcom,pmi8998-lab-ibb"; | |
| ibb { | |
| interrupts = <0x03 0xdc 0x02 0x01 0x03 0xdc 0x00 0x04>; | |
| interrupt-names = "sc-err\0ocp"; | |
| }; | |
| lab { | |
| interrupts = <0x03 0xde 0x01 0x01 0x03 0xde 0x00 0x08>; | |
| interrupt-names = "sc-err\0ocp"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| imem@146bf000 { | |
| compatible = "simple-mfd"; | |
| reg = <0x00 0x146bf000 0x00 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges = <0x00 0x00 0x146bf000 0x1000>; | |
| pil-reloc@94c { | |
| compatible = "qcom,pil-reloc-info"; | |
| reg = <0x94c 0xc8>; | |
| }; | |
| }; | |
| iommu@15000000 { | |
| compatible = "qcom,sdm845-smmu-500\0arm,mmu-500"; | |
| reg = <0x00 0x15000000 0x00 0x80000>; | |
| #iommu-cells = <0x02>; | |
| #global-interrupts = <0x01>; | |
| interrupts = <0x00 0x41 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04>; | |
| phandle = <0x23>; | |
| }; | |
| clock-controller@17014000 { | |
| compatible = "qcom,sdm845-lpasscc"; | |
| reg = <0x00 0x17014000 0x00 0x1f004 0x00 0x17300000 0x00 0x200>; | |
| reg-names = "cc\0qdsp6ss"; | |
| #clock-cells = <0x01>; | |
| status = "disabled"; | |
| }; | |
| interconnect@17900000 { | |
| compatible = "qcom,sdm845-gladiator-noc"; | |
| reg = <0x00 0x17900000 0x00 0xd080>; | |
| #interconnect-cells = <0x02>; | |
| qcom,bcm-voters = <0x6f>; | |
| phandle = <0x07>; | |
| }; | |
| watchdog@17980000 { | |
| compatible = "qcom,apss-wdt-sdm845\0qcom,kpss-wdt"; | |
| reg = <0x00 0x17980000 0x00 0x1000>; | |
| clocks = <0x2a>; | |
| interrupts = <0x00 0x00 0x04>; | |
| }; | |
| mailbox@17990000 { | |
| compatible = "qcom,sdm845-apss-shared"; | |
| reg = <0x00 0x17990000 0x00 0x1000>; | |
| #mbox-cells = <0x01>; | |
| phandle = <0x22>; | |
| }; | |
| rsc@179c0000 { | |
| label = "apps_rsc"; | |
| compatible = "qcom,rpmh-rsc"; | |
| reg = <0x00 0x179c0000 0x00 0x10000 0x00 0x179d0000 0x00 0x10000 0x00 0x179e0000 0x00 0x10000>; | |
| reg-names = "drv-0\0drv-1\0drv-2"; | |
| interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; | |
| qcom,tcs-offset = <0xd00>; | |
| qcom,drv-id = <0x02>; | |
| qcom,tcs-config = <0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x01>; | |
| bcm-voter { | |
| compatible = "qcom,bcm-voter"; | |
| phandle = <0x6f>; | |
| }; | |
| clock-controller { | |
| compatible = "qcom,sdm845-rpmh-clk"; | |
| #clock-cells = <0x01>; | |
| clock-names = "xo"; | |
| clocks = <0xd2>; | |
| phandle = <0x1f>; | |
| }; | |
| power-controller { | |
| compatible = "qcom,sdm845-rpmhpd"; | |
| #power-domain-cells = <0x01>; | |
| operating-points-v2 = <0xd3>; | |
| phandle = <0x35>; | |
| opp-table { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xd3>; | |
| opp1 { | |
| opp-level = <0x10>; | |
| }; | |
| opp2 { | |
| opp-level = <0x30>; | |
| phandle = <0x2e>; | |
| }; | |
| opp3 { | |
| opp-level = <0x40>; | |
| phandle = <0x2f>; | |
| }; | |
| opp4 { | |
| opp-level = <0x80>; | |
| phandle = <0x30>; | |
| }; | |
| opp5 { | |
| opp-level = <0xc0>; | |
| phandle = <0xa3>; | |
| }; | |
| opp6 { | |
| opp-level = <0x100>; | |
| phandle = <0x31>; | |
| }; | |
| opp7 { | |
| opp-level = <0x140>; | |
| }; | |
| opp8 { | |
| opp-level = <0x150>; | |
| }; | |
| opp9 { | |
| opp-level = <0x180>; | |
| phandle = <0xb3>; | |
| }; | |
| opp10 { | |
| opp-level = <0x1a0>; | |
| }; | |
| }; | |
| }; | |
| pm8998-rpmh-regulators { | |
| compatible = "qcom,pm8998-rpmh-regulators"; | |
| qcom,pmic-id = "a"; | |
| vdd-s1-supply = <0xd4>; | |
| vdd-s2-supply = <0xd4>; | |
| vdd-s3-supply = <0xd4>; | |
| vdd-s4-supply = <0xd4>; | |
| vdd-s5-supply = <0xd4>; | |
| vdd-s6-supply = <0xd4>; | |
| vdd-s7-supply = <0xd4>; | |
| vdd-s8-supply = <0xd4>; | |
| vdd-s9-supply = <0xd4>; | |
| vdd-s10-supply = <0xd4>; | |
| vdd-s11-supply = <0xd4>; | |
| vdd-s12-supply = <0xd4>; | |
| vdd-s13-supply = <0xd4>; | |
| vdd-l1-l27-supply = <0xd5>; | |
| vdd-l2-l8-l17-supply = <0xd6>; | |
| vdd-l3-l11-supply = <0xd5>; | |
| vdd-l4-l5-supply = <0xd5>; | |
| vdd-l6-supply = <0xd4>; | |
| vdd-l7-l12-l14-l15-supply = <0xd7>; | |
| vdd-l9-supply = <0xd8>; | |
| vdd-l10-l23-l25-supply = <0xd8>; | |
| vdd-l13-l19-l21-supply = <0xd8>; | |
| vdd-l16-l28-supply = <0xd8>; | |
| vdd-l18-l22-supply = <0xd8>; | |
| vdd-l20-l24-supply = <0xd8>; | |
| vdd-l26-supply = <0xd6>; | |
| vin-lvs-1-2-supply = <0x4b>; | |
| smps3 { | |
| regulator-min-microvolt = <0x14a140>; | |
| regulator-max-microvolt = <0x14a140>; | |
| phandle = <0xd6>; | |
| }; | |
| smps5 { | |
| regulator-min-microvolt = <0x1d0d80>; | |
| regulator-max-microvolt = <0x1f20c0>; | |
| phandle = <0xd7>; | |
| }; | |
| smps7 { | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0xfafa0>; | |
| phandle = <0xd5>; | |
| }; | |
| ldo1 { | |
| regulator-min-microvolt = <0xd6d80>; | |
| regulator-max-microvolt = <0xd6d80>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0x73>; | |
| }; | |
| ldo2 { | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-initial-mode = <0x03>; | |
| regulator-always-on; | |
| }; | |
| ldo5 { | |
| regulator-min-microvolt = "\0\f5"; | |
| regulator-max-microvolt = "\0\f5"; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0xda>; | |
| }; | |
| ldo7 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0x4c>; | |
| }; | |
| ldo12 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0xa9>; | |
| }; | |
| ldo14 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-initial-mode = <0x03>; | |
| regulator-always-on; | |
| phandle = <0xc2>; | |
| }; | |
| ldo17 { | |
| regulator-min-microvolt = <0x13e5c0>; | |
| regulator-max-microvolt = <0x13e5c0>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0x4d>; | |
| }; | |
| ldo20 { | |
| regulator-min-microvolt = <0x294280>; | |
| regulator-max-microvolt = <0x2d2a80>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0x71>; | |
| }; | |
| ldo24 { | |
| regulator-min-microvolt = <0x2f1e80>; | |
| regulator-max-microvolt = <0x2f1e80>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0xaa>; | |
| }; | |
| ldo25 { | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x328980>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0x4e>; | |
| }; | |
| ldo26 { | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0x74>; | |
| }; | |
| ldo28 { | |
| regulator-min-microvolt = <0x2b9440>; | |
| regulator-max-microvolt = <0x2de600>; | |
| regulator-initial-mode = <0x03>; | |
| phandle = <0x62>; | |
| }; | |
| }; | |
| pmi8998-rpmh-regulators { | |
| compatible = "qcom,pmi8998-rpmh-regulators"; | |
| qcom,pmic-id = "b"; | |
| vdd-bob-supply = <0xd4>; | |
| bob { | |
| regulator-min-microvolt = <0x328980>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| regulator-initial-mode = <0x02>; | |
| regulator-allow-bypass; | |
| phandle = <0xd8>; | |
| }; | |
| }; | |
| pm8005-rpmh-regulators { | |
| compatible = "qcom,pm8005-rpmh-regulators"; | |
| qcom,pmic-id = "c"; | |
| vdd-s1-supply = <0xd4>; | |
| vdd-s2-supply = <0xd4>; | |
| vdd-s3-supply = <0xd4>; | |
| vdd-s4-supply = <0xd4>; | |
| smps3 { | |
| regulator-min-microvolt = <0x927c0>; | |
| regulator-max-microvolt = <0x927c0>; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@17a00000 { | |
| compatible = "arm,gic-v3"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| #interrupt-cells = <0x03>; | |
| interrupt-controller; | |
| reg = <0x00 0x17a00000 0x00 0x10000 0x00 0x17a60000 0x00 0x100000>; | |
| interrupts = <0x01 0x09 0x04>; | |
| phandle = <0x01>; | |
| msi-controller@17a40000 { | |
| compatible = "arm,gic-v3-its"; | |
| msi-controller; | |
| #msi-cells = <0x01>; | |
| reg = <0x00 0x17a40000 0x00 0x20000>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| dma-controller@17184000 { | |
| compatible = "qcom,bam-v1.7.0"; | |
| qcom,controlled-remotely; | |
| reg = <0x00 0x17184000 0x00 0x2a000>; | |
| num-channels = <0x1f>; | |
| interrupts = <0x00 0xa4 0x04>; | |
| #dma-cells = <0x01>; | |
| qcom,ee = <0x01>; | |
| qcom,num-ees = <0x02>; | |
| iommus = <0x23 0x1806 0x00>; | |
| phandle = <0xa5>; | |
| }; | |
| timer@17c90000 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| compatible = "arm,armv7-timer-mem"; | |
| reg = <0x00 0x17c90000 0x00 0x1000>; | |
| frame@17ca0000 { | |
| frame-number = <0x00>; | |
| interrupts = <0x00 0x07 0x04 0x00 0x06 0x04>; | |
| reg = <0x00 0x17ca0000 0x00 0x1000 0x00 0x17cb0000 0x00 0x1000>; | |
| }; | |
| frame@17cc0000 { | |
| frame-number = <0x01>; | |
| interrupts = <0x00 0x08 0x04>; | |
| reg = <0x00 0x17cc0000 0x00 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17cd0000 { | |
| frame-number = <0x02>; | |
| interrupts = <0x00 0x09 0x04>; | |
| reg = <0x00 0x17cd0000 0x00 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17ce0000 { | |
| frame-number = <0x03>; | |
| interrupts = <0x00 0x0a 0x04>; | |
| reg = <0x00 0x17ce0000 0x00 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17cf0000 { | |
| frame-number = <0x04>; | |
| interrupts = <0x00 0x0b 0x04>; | |
| reg = <0x00 0x17cf0000 0x00 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17d00000 { | |
| frame-number = <0x05>; | |
| interrupts = <0x00 0x0c 0x04>; | |
| reg = <0x00 0x17d00000 0x00 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17d10000 { | |
| frame-number = <0x06>; | |
| interrupts = <0x00 0x0d 0x04>; | |
| reg = <0x00 0x17d10000 0x00 0x1000>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| interconnect@17d41000 { | |
| compatible = "qcom,sdm845-osm-l3"; | |
| reg = <0x00 0x17d41000 0x00 0x1400>; | |
| clocks = <0x1f 0x00 0x2d 0xa5>; | |
| clock-names = "xo\0alternate"; | |
| #interconnect-cells = <0x01>; | |
| phandle = <0x09>; | |
| }; | |
| cpufreq@17d43000 { | |
| compatible = "qcom,cpufreq-hw"; | |
| reg = <0x00 0x17d43000 0x00 0x1400 0x00 0x17d45800 0x00 0x1400>; | |
| reg-names = "freq-domain0\0freq-domain1"; | |
| clocks = <0x1f 0x00 0x2d 0xa5>; | |
| clock-names = "xo\0alternate"; | |
| #freq-domain-cells = <0x01>; | |
| phandle = <0x05>; | |
| }; | |
| wifi@18800000 { | |
| compatible = "qcom,wcn3990-wifi"; | |
| status = "okay"; | |
| reg = <0x00 0x18800000 0x00 0x800000>; | |
| reg-names = "membase"; | |
| memory-region = <0xd9>; | |
| clock-names = "cxo_ref_clk_pin"; | |
| clocks = <0x1f 0x08>; | |
| interrupts = <0x00 0x19e 0x04 0x00 0x19f 0x04 0x00 0x1a0 0x04 0x00 0x1a1 0x04 0x00 0x1a2 0x04 0x00 0x1a3 0x04 0x00 0x1a4 0x04 0x00 0x1a5 0x04 0x00 0x1a6 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04>; | |
| iommus = <0x23 0x40 0x01>; | |
| vdd-0.8-cx-mx-supply = <0xda>; | |
| vdd-1.8-xo-supply = <0x4c>; | |
| vdd-1.3-rfa-supply = <0x4d>; | |
| vdd-3.3-ch0-supply = <0x4e>; | |
| qcom,snoc-host-cap-8bit-quirk; | |
| }; | |
| }; | |
| thermal-zones { | |
| cpu0-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x01>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xdc>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xdd>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xdc>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xdd>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu1-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x02>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xde>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xdf>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xde>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xdf>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu2-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x03>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe0>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe1>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xe0>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xe1>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu3-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x04>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe2>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe3>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xe2>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xe3>; | |
| cooling-device = <0x16 0xffffffff 0xffffffff 0x17 0xffffffff 0xffffffff 0x18 0xffffffff 0xffffffff 0x19 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu4-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x07>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe4>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe5>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xe4>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xe5>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu5-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x08>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe6>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe7>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xe6>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xe7>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu6-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x09>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe8>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xe9>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xe8>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xe9>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu7-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x0a>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xea>; | |
| }; | |
| trip-point1 { | |
| temperature = <0x17318>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0xeb>; | |
| }; | |
| cpu_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x3e8>; | |
| type = "critical"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xea>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xeb>; | |
| cooling-device = <0x1a 0xffffffff 0xffffffff 0x1b 0xffffffff 0xffffffff 0x1c 0xffffffff 0xffffffff 0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| aoss0-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x00>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| cluster0-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x05>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| cluster0_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x7d0>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| cluster1-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x06>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| cluster1_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x7d0>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| gpu-thermal-top { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x0b>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| gpu-thermal-bottom { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xdb 0x0c>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| aoss1-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x00>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| q6-modem-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x01>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| mem-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x02>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| wlan-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x03>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| q6-hvx-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x04>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| camera-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x05>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| video-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x06>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| modem-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xec 0x07>; | |
| trips { | |
| trip-point0 { | |
| temperature = <0x15f90>; | |
| hysteresis = <0x7d0>; | |
| type = "hot"; | |
| }; | |
| }; | |
| }; | |
| pm8998-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0xed>; | |
| trips { | |
| pm8998-alert0 { | |
| temperature = <0x19a28>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| }; | |
| pm8998-crit { | |
| temperature = <0x1e848>; | |
| hysteresis = <0x7d0>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gpio-keys { | |
| compatible = "gpio-keys"; | |
| label = "Volume keys"; | |
| autorepeat; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xee 0xef>; | |
| vol-down { | |
| label = "Volume down"; | |
| linux,code = <0x72>; | |
| gpios = <0xd0 0x05 0x01>; | |
| debounce-interval = <0x0f>; | |
| }; | |
| vol-up { | |
| label = "Volume up"; | |
| linux,code = <0x73>; | |
| gpios = <0xd0 0x06 0x01>; | |
| debounce-interval = <0x0f>; | |
| }; | |
| }; | |
| vph-pwr-regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vph_pwr"; | |
| regulator-min-microvolt = <0x387520>; | |
| regulator-max-microvolt = <0x387520>; | |
| phandle = <0xd4>; | |
| }; | |
| pm8998-smps4 { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vreg_s4a_1p8"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| vin-supply = <0xd4>; | |
| phandle = <0x4b>; | |
| }; | |
| ts-1p8-regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "ts_1p8_supply"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| gpio = <0x60 0x58 0x00>; | |
| enable-active-high; | |
| regulator-boot-on; | |
| phandle = <0x63>; | |
| }; | |
| }; |
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