Ram.scala

import chisel3._
import chisel3.util._
import chisel3.ExplicitCompileOptions.Strict
import chisel3.internal.naming.chiselName

@chiselName
class Ram[T <: Data](size: Int, elType: T, numPorts: Int = 2) extends Module {
  val io = IO(new Bundle {
    val port = Vec(numPorts, new Bundle {
      val req = Flipped(Valid(new Bundle {
        val addr = UInt(log2Ceil(size).W)
        val write = Valid(elType.cloneType)
      }))
      val resp = Valid(elType.cloneType)
    })
  })

  private val ram = SyncReadMem(size, elType).suggestName(name)

  io.port.foreach(port => {
    val mkPort = ram(port.req.bits.addr)
    mkPort.suggestName(name + "Port")
    port.resp.valid := RegNext(port.req.valid, 0.B)
    port.resp.bits := DontCare
    when(port.req.valid) {
      port.resp.bits := mkPort
      when(port.req.bits.write.valid) {
        mkPort := port.req.bits.write.bits
      }
    }
  })
}