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June 10, 2023 13:26
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| $ CL_WIMPY_MODE=1 LD_PRELOAD=/usr/lib64/libasan.so.8.0.0 AMD_DEBUG=cs,nir,llvm,asm MESA_SHADER_CACHE_DISABLE=1 RUSTICL_ENABLE=radeonsi run_local_mesa ../OpenCL-CTS/build/test_conformance/integer_ops/test_integer_ops integer_mad_sat | |
| Initializing random seed to 0. | |
| Requesting Default device based on command line for platform index 0 and device index 0 | |
| Compute Device Name = AMD Radeon RX 6700 XT (navi22, LLVM 15.0.6, DRM 3.52, 6.3.5-200.fc38.x86_64), Compute Device Vendor = AMD, Compute Device Version = OpenCL 3.0 , CL C Version = OpenCL C 1.2 | |
| Device latest conformance version passed: v0000-01-01-00 | |
| Supports single precision denormals: NO | |
| sizeof( void*) = 8 (host) | |
| sizeof( void*) = 8 (device) | |
| integer_mad_sat... | |
| shader: MESA_SHADER_KERNEL | |
| source_sha1: {0xb5cfec13, 0x8c7db6d4, 0xa5530025, 0xc4d0316c, 0xb3130a16} | |
| workgroup-size: 0, 0, 0 (variable) | |
| shared-size: 0 | |
| stage: 14 | |
| next_stage: 0 | |
| num_ubos: 1 | |
| system_values_read: 0x00000000'00002420'00000000 | |
| float_controls_execution_mode: 0x0011 | |
| subgroup_size: 0 | |
| divergence_analysis_run: true | |
| bit_sizes_int: 0x61 | |
| first_ubo_is_default_ubo: true | |
| flrp_lowered: true | |
| io_lowered: true | |
| writes_memory: true | |
| Unhandled stage 14 | |
| inputs: 0 | |
| outputs: 0 | |
| uniforms: 64 | |
| decl_var ubo INTERP_MODE_NONE uint8_t[64] kernel_input (0, 0, 0) | |
| decl_function __wrapped_sample_test (0 params) | |
| impl __wrapped_sample_test { | |
| block block_0: | |
| /* preds: */ | |
| vec1 64 div ssa_0 = load_const (0x0000000000000000 = 0.000000) | |
| vec1 32 div ssa_1 = load_const (0x00000000 = 0.000000) | |
| vec1 32 div ssa_2 = intrinsic load_scalar_arg_amd () (base=2, arg_upper_bound_u32_amd=0) | |
| vec1 32 div ssa_3 = load_const (0x00008000 = 0.000000) | |
| vec1 32 div ssa_4 = load_const (0x31016fac = 0.000000) | |
| vec1 32 div ssa_5 = load_const (0x00000400 = 0.000000) | |
| vec4 32 div ssa_6 = vec4 ssa_2, ssa_3, ssa_5, ssa_4 | |
| vec1 64 div ssa_7 = intrinsic load_ubo (ssa_6, ssa_1) (access=0, align_mul=256, align_offset=0, range_base=0, range=64) | |
| vec1 32 div ssa_8 = load_const (0x00000008 = 0.000000) | |
| vec1 64 div ssa_9 = intrinsic load_ubo (ssa_6, ssa_8) (access=0, align_mul=256, align_offset=8, range_base=0, range=64) | |
| vec1 32 div ssa_10 = load_const (0x00000010 = 0.000000) | |
| vec1 64 div ssa_11 = intrinsic load_ubo (ssa_6, ssa_10) (access=0, align_mul=256, align_offset=16, range_base=0, range=64) | |
| vec1 32 div ssa_12 = load_const (0x00000018 = 0.000000) | |
| vec1 64 div ssa_13 = intrinsic load_ubo (ssa_6, ssa_12) (access=0, align_mul=256, align_offset=24, range_base=0, range=64) | |
| vec1 32 div ssa_14 = load_const (0x00000020 = 0.000000) | |
| vec3 64 div ssa_15 = intrinsic load_ubo (ssa_6, ssa_14) (access=0, align_mul=256, align_offset=32, range_base=0, range=64) | |
| vec1 32 div ssa_16 = intrinsic load_scalar_arg_amd () (base=4, arg_upper_bound_u32_amd=0) | |
| vec1 32 div ssa_17 = load_const (0x000003ff = 0.000000) | |
| vec1 32 div ssa_18 = iand ssa_16, ssa_17 | |
| vec3 64 div ssa_19 = intrinsic load_workgroup_id () () | |
| vec3 32 div ssa_20 = intrinsic load_local_invocation_id () () | |
| vec1 64 div ssa_21 = u2u64 ssa_20.x | |
| vec1 32 div ssa_22 = unpack_64_2x32_split_x ssa_19.x | |
| vec1 32 div ssa_23 = unpack_64_2x32_split_y ssa_19.x | |
| vec1 32 div ssa_24 = umul_high ssa_22, ssa_18 | |
| vec1 32 div ssa_25 = imul ssa_22, ssa_18 | |
| vec1 32 div ssa_26 = imul ssa_23, ssa_18 | |
| vec1 32 div ssa_27 = iadd ssa_24, ssa_26 | |
| vec1 64 div ssa_28 = pack_64_2x32_split ssa_25, ssa_27 | |
| vec1 64 div ssa_29 = iadd ssa_28, ssa_21 | |
| vec1 64 div ssa_30 = iadd ssa_29, ssa_15.x | |
| vec1 32 div ssa_31 = u2u32 ssa_30 | |
| vec1 64 div ssa_32 = i2i64 ssa_31 | |
| vec1 32 div ssa_33 = load_const (0x00000007 = 0.000000) | |
| vec1 64 div ssa_34 = ishl ssa_32, ssa_33 | |
| vec1 64 div ssa_35 = iadd ssa_7, ssa_34 | |
| vec16 64 div ssa_36 = intrinsic load_global (ssa_35) (access=0, align_mul=128, align_offset=0) | |
| vec1 64 div ssa_37 = iadd ssa_9, ssa_34 | |
| vec16 64 div ssa_38 = intrinsic load_global (ssa_37) (access=0, align_mul=128, align_offset=0) | |
| vec1 64 div ssa_39 = iadd ssa_11, ssa_34 | |
| vec16 64 div ssa_40 = intrinsic load_global (ssa_39) (access=0, align_mul=128, align_offset=0) | |
| vec1 64 div ssa_41 = load_const (0xffffffffffffffff = -nan) | |
| vec1 32 div ssa_42 = unpack_64_2x32_split_x ssa_36.a | |
| vec1 32 div ssa_43 = unpack_64_2x32_split_y ssa_36.a | |
| vec1 32 div ssa_44 = unpack_64_2x32_split_x ssa_38.a | |
| vec1 32 div ssa_45 = unpack_64_2x32_split_y ssa_38.a | |
| vec1 32 div ssa_46 = umul_high ssa_42, ssa_44 | |
| vec1 32 div ssa_47 = imul ssa_42, ssa_44 | |
| vec1 64 div ssa_48 = pack_64_2x32_split ssa_47, ssa_46 | |
| vec1 64 div ssa_49 = ushr ssa_48, ssa_14 | |
| vec1 32 div ssa_50 = umul_high ssa_42, ssa_45 | |
| vec1 32 div ssa_51 = imul ssa_42, ssa_45 | |
| vec1 64 div ssa_52 = pack_64_2x32_split ssa_51, ssa_50 | |
| vec1 64 div ssa_53 = iadd ssa_52, ssa_49 | |
| vec1 32 div ssa_54 = u2u32 ssa_53 | |
| vec1 64 div ssa_55 = ushr ssa_53, ssa_14 | |
| vec1 32 div ssa_56 = umul_high ssa_42, ssa_1 | |
| vec1 64 div ssa_57 = pack_64_2x32_split ssa_1, ssa_56 | |
| vec1 64 div ssa_58 = iadd ssa_57, ssa_55 | |
| vec1 32 div ssa_59 = u2u32 ssa_58 | |
| vec1 64 div ssa_60 = ushr ssa_58, ssa_14 | |
| vec1 64 div ssa_61 = iadd ssa_57, ssa_60 | |
| vec1 32 div ssa_62 = u2u32 ssa_61 | |
| vec1 32 div ssa_63 = umul_high ssa_43, ssa_44 | |
| vec1 32 div ssa_64 = imul ssa_43, ssa_44 | |
| vec1 64 div ssa_65 = pack_64_2x32_split ssa_64, ssa_63 | |
| vec1 64 div ssa_66 = u2u64 ssa_54 | |
| vec1 64 div ssa_67 = iadd ssa_65, ssa_66 | |
| vec1 64 div ssa_68 = ushr ssa_67, ssa_14 | |
| vec1 32 div ssa_69 = umul_high ssa_43, ssa_45 | |
| vec1 32 div ssa_70 = imul ssa_43, ssa_45 | |
| vec1 64 div ssa_71 = pack_64_2x32_split ssa_70, ssa_69 | |
| vec1 64 div ssa_72 = u2u64 ssa_59 | |
| vec1 64 div ssa_73 = iadd ssa_71, ssa_72 | |
| vec1 64 div ssa_74 = iadd ssa_73, ssa_68 | |
| vec1 32 div ssa_75 = u2u32 ssa_74 | |
| vec1 64 div ssa_76 = ushr ssa_74, ssa_14 | |
| vec1 32 div ssa_77 = umul_high ssa_43, ssa_1 | |
| vec1 64 div ssa_78 = pack_64_2x32_split ssa_1, ssa_77 | |
| vec1 64 div ssa_79 = u2u64 ssa_62 | |
| vec1 64 div ssa_80 = iadd ssa_78, ssa_79 | |
| vec1 64 div ssa_81 = iadd ssa_80, ssa_76 | |
| vec1 32 div ssa_82 = u2u32 ssa_81 | |
| vec1 32 div ssa_83 = umul_high ssa_1, ssa_44 | |
| vec1 64 div ssa_84 = pack_64_2x32_split ssa_1, ssa_83 | |
| vec1 64 div ssa_85 = u2u64 ssa_75 | |
| vec1 64 div ssa_86 = iadd ssa_84, ssa_85 | |
| vec1 32 div ssa_87 = u2u32 ssa_86 | |
| vec1 64 div ssa_88 = ushr ssa_86, ssa_14 | |
| vec1 32 div ssa_89 = umul_high ssa_1, ssa_45 | |
| vec1 64 div ssa_90 = pack_64_2x32_split ssa_1, ssa_89 | |
| vec1 64 div ssa_91 = u2u64 ssa_82 | |
| vec1 64 div ssa_92 = iadd ssa_90, ssa_91 | |
| vec1 64 div ssa_93 = iadd ssa_92, ssa_88 | |
| vec1 32 div ssa_94 = u2u32 ssa_93 | |
| vec1 64 div ssa_95 = u2u64 ssa_94 | |
| vec1 64 div ssa_96 = iadd ssa_84, ssa_95 | |
| vec1 32 div ssa_97 = u2u32 ssa_96 | |
| vec1 64 div ssa_98 = pack_64_2x32_split ssa_87, ssa_97 | |
| vec1 1 div ssa_99 = ieq ssa_98, ssa_0 | |
| vec1 32 div ssa_100 = iadd ssa_51, ssa_64 | |
| vec1 32 div ssa_101 = iadd ssa_46, ssa_100 | |
| vec1 64 div ssa_102 = pack_64_2x32_split ssa_47, ssa_101 | |
| vec1 64 div ssa_103 = uadd_sat ssa_102, ssa_40.a | |
| vec1 64 div ssa_104 = bcsel ssa_99, ssa_103, ssa_41 | |
| vec1 32 div ssa_105 = unpack_64_2x32_split_x ssa_36.b | |
| vec1 32 div ssa_106 = unpack_64_2x32_split_y ssa_36.b | |
| vec1 32 div ssa_107 = unpack_64_2x32_split_x ssa_38.b | |
| vec1 32 div ssa_108 = unpack_64_2x32_split_y ssa_38.b | |
| vec1 32 div ssa_109 = umul_high ssa_105, ssa_107 | |
| vec1 32 div ssa_110 = imul ssa_105, ssa_107 | |
| vec1 64 div ssa_111 = pack_64_2x32_split ssa_110, ssa_109 | |
| vec1 64 div ssa_112 = ushr ssa_111, ssa_14 | |
| vec1 32 div ssa_113 = umul_high ssa_105, ssa_108 | |
| vec1 32 div ssa_114 = imul ssa_105, ssa_108 | |
| vec1 64 div ssa_115 = pack_64_2x32_split ssa_114, ssa_113 | |
| vec1 64 div ssa_116 = iadd ssa_115, ssa_112 | |
| vec1 32 div ssa_117 = u2u32 ssa_116 | |
| vec1 64 div ssa_118 = ushr ssa_116, ssa_14 | |
| vec1 32 div ssa_119 = umul_high ssa_105, ssa_1 | |
| vec1 64 div ssa_120 = pack_64_2x32_split ssa_1, ssa_119 | |
| vec1 64 div ssa_121 = iadd ssa_120, ssa_118 | |
| vec1 32 div ssa_122 = u2u32 ssa_121 | |
| vec1 64 div ssa_123 = ushr ssa_121, ssa_14 | |
| vec1 64 div ssa_124 = iadd ssa_120, ssa_123 | |
| vec1 32 div ssa_125 = u2u32 ssa_124 | |
| vec1 32 div ssa_126 = umul_high ssa_106, ssa_107 | |
| vec1 32 div ssa_127 = imul ssa_106, ssa_107 | |
| vec1 64 div ssa_128 = pack_64_2x32_split ssa_127, ssa_126 | |
| vec1 64 div ssa_129 = u2u64 ssa_117 | |
| vec1 64 div ssa_130 = iadd ssa_128, ssa_129 | |
| vec1 64 div ssa_131 = ushr ssa_130, ssa_14 | |
| vec1 32 div ssa_132 = umul_high ssa_106, ssa_108 | |
| vec1 32 div ssa_133 = imul ssa_106, ssa_108 | |
| vec1 64 div ssa_134 = pack_64_2x32_split ssa_133, ssa_132 | |
| vec1 64 div ssa_135 = u2u64 ssa_122 | |
| vec1 64 div ssa_136 = iadd ssa_134, ssa_135 | |
| vec1 64 div ssa_137 = iadd ssa_136, ssa_131 | |
| vec1 32 div ssa_138 = u2u32 ssa_137 | |
| vec1 64 div ssa_139 = ushr ssa_137, ssa_14 | |
| vec1 32 div ssa_140 = umul_high ssa_106, ssa_1 | |
| vec1 64 div ssa_141 = pack_64_2x32_split ssa_1, ssa_140 | |
| vec1 64 div ssa_142 = u2u64 ssa_125 | |
| vec1 64 div ssa_143 = iadd ssa_141, ssa_142 | |
| vec1 64 div ssa_144 = iadd ssa_143, ssa_139 | |
| vec1 32 div ssa_145 = u2u32 ssa_144 | |
| vec1 32 div ssa_146 = umul_high ssa_1, ssa_107 | |
| vec1 64 div ssa_147 = pack_64_2x32_split ssa_1, ssa_146 | |
| vec1 64 div ssa_148 = u2u64 ssa_138 | |
| vec1 64 div ssa_149 = iadd ssa_147, ssa_148 | |
| vec1 32 div ssa_150 = u2u32 ssa_149 | |
| vec1 64 div ssa_151 = ushr ssa_149, ssa_14 | |
| vec1 32 div ssa_152 = umul_high ssa_1, ssa_108 | |
| vec1 64 div ssa_153 = pack_64_2x32_split ssa_1, ssa_152 | |
| vec1 64 div ssa_154 = u2u64 ssa_145 | |
| vec1 64 div ssa_155 = iadd ssa_153, ssa_154 | |
| vec1 64 div ssa_156 = iadd ssa_155, ssa_151 | |
| vec1 32 div ssa_157 = u2u32 ssa_156 | |
| vec1 64 div ssa_158 = u2u64 ssa_157 | |
| vec1 64 div ssa_159 = iadd ssa_147, ssa_158 | |
| vec1 32 div ssa_160 = u2u32 ssa_159 | |
| vec1 64 div ssa_161 = pack_64_2x32_split ssa_150, ssa_160 | |
| vec1 1 div ssa_162 = ieq ssa_161, ssa_0 | |
| vec1 32 div ssa_163 = iadd ssa_114, ssa_127 | |
| vec1 32 div ssa_164 = iadd ssa_109, ssa_163 | |
| vec1 64 div ssa_165 = pack_64_2x32_split ssa_110, ssa_164 | |
| vec1 64 div ssa_166 = uadd_sat ssa_165, ssa_40.b | |
| vec1 64 div ssa_167 = bcsel ssa_162, ssa_166, ssa_41 | |
| vec1 32 div ssa_168 = unpack_64_2x32_split_x ssa_36.c | |
| vec1 32 div ssa_169 = unpack_64_2x32_split_y ssa_36.c | |
| vec1 32 div ssa_170 = unpack_64_2x32_split_x ssa_38.c | |
| vec1 32 div ssa_171 = unpack_64_2x32_split_y ssa_38.c | |
| vec1 32 div ssa_172 = umul_high ssa_168, ssa_170 | |
| vec1 32 div ssa_173 = imul ssa_168, ssa_170 | |
| vec1 64 div ssa_174 = pack_64_2x32_split ssa_173, ssa_172 | |
| vec1 64 div ssa_175 = ushr ssa_174, ssa_14 | |
| vec1 32 div ssa_176 = umul_high ssa_168, ssa_171 | |
| vec1 32 div ssa_177 = imul ssa_168, ssa_171 | |
| vec1 64 div ssa_178 = pack_64_2x32_split ssa_177, ssa_176 | |
| vec1 64 div ssa_179 = iadd ssa_178, ssa_175 | |
| vec1 32 div ssa_180 = u2u32 ssa_179 | |
| vec1 64 div ssa_181 = ushr ssa_179, ssa_14 | |
| vec1 32 div ssa_182 = umul_high ssa_168, ssa_1 | |
| vec1 64 div ssa_183 = pack_64_2x32_split ssa_1, ssa_182 | |
| vec1 64 div ssa_184 = iadd ssa_183, ssa_181 | |
| vec1 32 div ssa_185 = u2u32 ssa_184 | |
| vec1 64 div ssa_186 = ushr ssa_184, ssa_14 | |
| vec1 64 div ssa_187 = iadd ssa_183, ssa_186 | |
| vec1 32 div ssa_188 = u2u32 ssa_187 | |
| vec1 32 div ssa_189 = umul_high ssa_169, ssa_170 | |
| vec1 32 div ssa_190 = imul ssa_169, ssa_170 | |
| vec1 64 div ssa_191 = pack_64_2x32_split ssa_190, ssa_189 | |
| vec1 64 div ssa_192 = u2u64 ssa_180 | |
| vec1 64 div ssa_193 = iadd ssa_191, ssa_192 | |
| vec1 64 div ssa_194 = ushr ssa_193, ssa_14 | |
| vec1 32 div ssa_195 = umul_high ssa_169, ssa_171 | |
| vec1 32 div ssa_196 = imul ssa_169, ssa_171 | |
| vec1 64 div ssa_197 = pack_64_2x32_split ssa_196, ssa_195 | |
| vec1 64 div ssa_198 = u2u64 ssa_185 | |
| vec1 64 div ssa_199 = iadd ssa_197, ssa_198 | |
| vec1 64 div ssa_200 = iadd ssa_199, ssa_194 | |
| vec1 32 div ssa_201 = u2u32 ssa_200 | |
| vec1 64 div ssa_202 = ushr ssa_200, ssa_14 | |
| vec1 32 div ssa_203 = umul_high ssa_169, ssa_1 | |
| vec1 64 div ssa_204 = pack_64_2x32_split ssa_1, ssa_203 | |
| vec1 64 div ssa_205 = u2u64 ssa_188 | |
| vec1 64 div ssa_206 = iadd ssa_204, ssa_205 | |
| vec1 64 div ssa_207 = iadd ssa_206, ssa_202 | |
| vec1 32 div ssa_208 = u2u32 ssa_207 | |
| vec1 32 div ssa_209 = umul_high ssa_1, ssa_170 | |
| vec1 64 div ssa_210 = pack_64_2x32_split ssa_1, ssa_209 | |
| vec1 64 div ssa_211 = u2u64 ssa_201 | |
| vec1 64 div ssa_212 = iadd ssa_210, ssa_211 | |
| vec1 32 div ssa_213 = u2u32 ssa_212 | |
| vec1 64 div ssa_214 = ushr ssa_212, ssa_14 | |
| vec1 32 div ssa_215 = umul_high ssa_1, ssa_171 | |
| vec1 64 div ssa_216 = pack_64_2x32_split ssa_1, ssa_215 | |
| vec1 64 div ssa_217 = u2u64 ssa_208 | |
| vec1 64 div ssa_218 = iadd ssa_216, ssa_217 | |
| vec1 64 div ssa_219 = iadd ssa_218, ssa_214 | |
| vec1 32 div ssa_220 = u2u32 ssa_219 | |
| vec1 64 div ssa_221 = u2u64 ssa_220 | |
| vec1 64 div ssa_222 = iadd ssa_210, ssa_221 | |
| vec1 32 div ssa_223 = u2u32 ssa_222 | |
| vec1 64 div ssa_224 = pack_64_2x32_split ssa_213, ssa_223 | |
| vec1 1 div ssa_225 = ieq ssa_224, ssa_0 | |
| vec1 32 div ssa_226 = iadd ssa_177, ssa_190 | |
| vec1 32 div ssa_227 = iadd ssa_172, ssa_226 | |
| vec1 64 div ssa_228 = pack_64_2x32_split ssa_173, ssa_227 | |
| vec1 64 div ssa_229 = uadd_sat ssa_228, ssa_40.c | |
| vec1 64 div ssa_230 = bcsel ssa_225, ssa_229, ssa_41 | |
| vec1 32 div ssa_231 = unpack_64_2x32_split_x ssa_36.d | |
| vec1 32 div ssa_232 = unpack_64_2x32_split_y ssa_36.d | |
| vec1 32 div ssa_233 = unpack_64_2x32_split_x ssa_38.d | |
| vec1 32 div ssa_234 = unpack_64_2x32_split_y ssa_38.d | |
| vec1 32 div ssa_235 = umul_high ssa_231, ssa_233 | |
| vec1 32 div ssa_236 = imul ssa_231, ssa_233 | |
| vec1 64 div ssa_237 = pack_64_2x32_split ssa_236, ssa_235 | |
| vec1 64 div ssa_238 = ushr ssa_237, ssa_14 | |
| vec1 32 div ssa_239 = umul_high ssa_231, ssa_234 | |
| vec1 32 div ssa_240 = imul ssa_231, ssa_234 | |
| vec1 64 div ssa_241 = pack_64_2x32_split ssa_240, ssa_239 | |
| vec1 64 div ssa_242 = iadd ssa_241, ssa_238 | |
| vec1 32 div ssa_243 = u2u32 ssa_242 | |
| vec1 64 div ssa_244 = ushr ssa_242, ssa_14 | |
| vec1 32 div ssa_245 = umul_high ssa_231, ssa_1 | |
| vec1 64 div ssa_246 = pack_64_2x32_split ssa_1, ssa_245 | |
| vec1 64 div ssa_247 = iadd ssa_246, ssa_244 | |
| vec1 32 div ssa_248 = u2u32 ssa_247 | |
| vec1 64 div ssa_249 = ushr ssa_247, ssa_14 | |
| vec1 64 div ssa_250 = iadd ssa_246, ssa_249 | |
| vec1 32 div ssa_251 = u2u32 ssa_250 | |
| vec1 32 div ssa_252 = umul_high ssa_232, ssa_233 | |
| vec1 32 div ssa_253 = imul ssa_232, ssa_233 | |
| vec1 64 div ssa_254 = pack_64_2x32_split ssa_253, ssa_252 | |
| vec1 64 div ssa_255 = u2u64 ssa_243 | |
| vec1 64 div ssa_256 = iadd ssa_254, ssa_255 | |
| vec1 64 div ssa_257 = ushr ssa_256, ssa_14 | |
| vec1 32 div ssa_258 = umul_high ssa_232, ssa_234 | |
| vec1 32 div ssa_259 = imul ssa_232, ssa_234 | |
| vec1 64 div ssa_260 = pack_64_2x32_split ssa_259, ssa_258 | |
| vec1 64 div ssa_261 = u2u64 ssa_248 | |
| vec1 64 div ssa_262 = iadd ssa_260, ssa_261 | |
| vec1 64 div ssa_263 = iadd ssa_262, ssa_257 | |
| vec1 32 div ssa_264 = u2u32 ssa_263 | |
| vec1 64 div ssa_265 = ushr ssa_263, ssa_14 | |
| vec1 32 div ssa_266 = umul_high ssa_232, ssa_1 | |
| vec1 64 div ssa_267 = pack_64_2x32_split ssa_1, ssa_266 | |
| vec1 64 div ssa_268 = u2u64 ssa_251 | |
| vec1 64 div ssa_269 = iadd ssa_267, ssa_268 | |
| vec1 64 div ssa_270 = iadd ssa_269, ssa_265 | |
| vec1 32 div ssa_271 = u2u32 ssa_270 | |
| vec1 32 div ssa_272 = umul_high ssa_1, ssa_233 | |
| vec1 64 div ssa_273 = pack_64_2x32_split ssa_1, ssa_272 | |
| vec1 64 div ssa_274 = u2u64 ssa_264 | |
| vec1 64 div ssa_275 = iadd ssa_273, ssa_274 | |
| vec1 32 div ssa_276 = u2u32 ssa_275 | |
| vec1 64 div ssa_277 = ushr ssa_275, ssa_14 | |
| vec1 32 div ssa_278 = umul_high ssa_1, ssa_234 | |
| vec1 64 div ssa_279 = pack_64_2x32_split ssa_1, ssa_278 | |
| vec1 64 div ssa_280 = u2u64 ssa_271 | |
| vec1 64 div ssa_281 = iadd ssa_279, ssa_280 | |
| vec1 64 div ssa_282 = iadd ssa_281, ssa_277 | |
| vec1 32 div ssa_283 = u2u32 ssa_282 | |
| vec1 64 div ssa_284 = u2u64 ssa_283 | |
| vec1 64 div ssa_285 = iadd ssa_273, ssa_284 | |
| vec1 32 div ssa_286 = u2u32 ssa_285 | |
| vec1 64 div ssa_287 = pack_64_2x32_split ssa_276, ssa_286 | |
| vec1 1 div ssa_288 = ieq ssa_287, ssa_0 | |
| vec1 32 div ssa_289 = iadd ssa_240, ssa_253 | |
| vec1 32 div ssa_290 = iadd ssa_235, ssa_289 | |
| vec1 64 div ssa_291 = pack_64_2x32_split ssa_236, ssa_290 | |
| vec1 64 div ssa_292 = uadd_sat ssa_291, ssa_40.d | |
| vec1 64 div ssa_293 = bcsel ssa_288, ssa_292, ssa_41 | |
| vec1 32 div ssa_294 = unpack_64_2x32_split_x ssa_36.e | |
| vec1 32 div ssa_295 = unpack_64_2x32_split_y ssa_36.e | |
| vec1 32 div ssa_296 = unpack_64_2x32_split_x ssa_38.e | |
| vec1 32 div ssa_297 = unpack_64_2x32_split_y ssa_38.e | |
| vec1 32 div ssa_298 = umul_high ssa_294, ssa_296 | |
| vec1 32 div ssa_299 = imul ssa_294, ssa_296 | |
| vec1 64 div ssa_300 = pack_64_2x32_split ssa_299, ssa_298 | |
| vec1 64 div ssa_301 = ushr ssa_300, ssa_14 | |
| vec1 32 div ssa_302 = umul_high ssa_294, ssa_297 | |
| vec1 32 div ssa_303 = imul ssa_294, ssa_297 | |
| vec1 64 div ssa_304 = pack_64_2x32_split ssa_303, ssa_302 | |
| vec1 64 div ssa_305 = iadd ssa_304, ssa_301 | |
| vec1 32 div ssa_306 = u2u32 ssa_305 | |
| vec1 64 div ssa_307 = ushr ssa_305, ssa_14 | |
| vec1 32 div ssa_308 = umul_high ssa_294, ssa_1 | |
| vec1 64 div ssa_309 = pack_64_2x32_split ssa_1, ssa_308 | |
| vec1 64 div ssa_310 = iadd ssa_309, ssa_307 | |
| vec1 32 div ssa_311 = u2u32 ssa_310 | |
| vec1 64 div ssa_312 = ushr ssa_310, ssa_14 | |
| vec1 64 div ssa_313 = iadd ssa_309, ssa_312 | |
| vec1 32 div ssa_314 = u2u32 ssa_313 | |
| vec1 32 div ssa_315 = umul_high ssa_295, ssa_296 | |
| vec1 32 div ssa_316 = imul ssa_295, ssa_296 | |
| vec1 64 div ssa_317 = pack_64_2x32_split ssa_316, ssa_315 | |
| vec1 64 div ssa_318 = u2u64 ssa_306 | |
| vec1 64 div ssa_319 = iadd ssa_317, ssa_318 | |
| vec1 64 div ssa_320 = ushr ssa_319, ssa_14 | |
| vec1 32 div ssa_321 = umul_high ssa_295, ssa_297 | |
| vec1 32 div ssa_322 = imul ssa_295, ssa_297 | |
| vec1 64 div ssa_323 = pack_64_2x32_split ssa_322, ssa_321 | |
| vec1 64 div ssa_324 = u2u64 ssa_311 | |
| vec1 64 div ssa_325 = iadd ssa_323, ssa_324 | |
| vec1 64 div ssa_326 = iadd ssa_325, ssa_320 | |
| vec1 32 div ssa_327 = u2u32 ssa_326 | |
| vec1 64 div ssa_328 = ushr ssa_326, ssa_14 | |
| vec1 32 div ssa_329 = umul_high ssa_295, ssa_1 | |
| vec1 64 div ssa_330 = pack_64_2x32_split ssa_1, ssa_329 | |
| vec1 64 div ssa_331 = u2u64 ssa_314 | |
| vec1 64 div ssa_332 = iadd ssa_330, ssa_331 | |
| vec1 64 div ssa_333 = iadd ssa_332, ssa_328 | |
| vec1 32 div ssa_334 = u2u32 ssa_333 | |
| vec1 32 div ssa_335 = umul_high ssa_1, ssa_296 | |
| vec1 64 div ssa_336 = pack_64_2x32_split ssa_1, ssa_335 | |
| vec1 64 div ssa_337 = u2u64 ssa_327 | |
| vec1 64 div ssa_338 = iadd ssa_336, ssa_337 | |
| vec1 32 div ssa_339 = u2u32 ssa_338 | |
| vec1 64 div ssa_340 = ushr ssa_338, ssa_14 | |
| vec1 32 div ssa_341 = umul_high ssa_1, ssa_297 | |
| vec1 64 div ssa_342 = pack_64_2x32_split ssa_1, ssa_341 | |
| vec1 64 div ssa_343 = u2u64 ssa_334 | |
| vec1 64 div ssa_344 = iadd ssa_342, ssa_343 | |
| vec1 64 div ssa_345 = iadd ssa_344, ssa_340 | |
| vec1 32 div ssa_346 = u2u32 ssa_345 | |
| vec1 64 div ssa_347 = u2u64 ssa_346 | |
| vec1 64 div ssa_348 = iadd ssa_336, ssa_347 | |
| vec1 32 div ssa_349 = u2u32 ssa_348 | |
| vec1 64 div ssa_350 = pack_64_2x32_split ssa_339, ssa_349 | |
| vec1 1 div ssa_351 = ieq ssa_350, ssa_0 | |
| vec1 32 div ssa_352 = iadd ssa_303, ssa_316 | |
| vec1 32 div ssa_353 = iadd ssa_298, ssa_352 | |
| vec1 64 div ssa_354 = pack_64_2x32_split ssa_299, ssa_353 | |
| vec1 64 div ssa_355 = uadd_sat ssa_354, ssa_40.e | |
| vec1 64 div ssa_356 = bcsel ssa_351, ssa_355, ssa_41 | |
| vec1 32 div ssa_357 = unpack_64_2x32_split_x ssa_36.f | |
| vec1 32 div ssa_358 = unpack_64_2x32_split_y ssa_36.f | |
| vec1 32 div ssa_359 = unpack_64_2x32_split_x ssa_38.f | |
| vec1 32 div ssa_360 = unpack_64_2x32_split_y ssa_38.f | |
| vec1 32 div ssa_361 = umul_high ssa_357, ssa_359 | |
| vec1 32 div ssa_362 = imul ssa_357, ssa_359 | |
| vec1 64 div ssa_363 = pack_64_2x32_split ssa_362, ssa_361 | |
| vec1 64 div ssa_364 = ushr ssa_363, ssa_14 | |
| vec1 32 div ssa_365 = umul_high ssa_357, ssa_360 | |
| vec1 32 div ssa_366 = imul ssa_357, ssa_360 | |
| vec1 64 div ssa_367 = pack_64_2x32_split ssa_366, ssa_365 | |
| vec1 64 div ssa_368 = iadd ssa_367, ssa_364 | |
| vec1 32 div ssa_369 = u2u32 ssa_368 | |
| vec1 64 div ssa_370 = ushr ssa_368, ssa_14 | |
| vec1 32 div ssa_371 = umul_high ssa_357, ssa_1 | |
| vec1 64 div ssa_372 = pack_64_2x32_split ssa_1, ssa_371 | |
| vec1 64 div ssa_373 = iadd ssa_372, ssa_370 | |
| vec1 32 div ssa_374 = u2u32 ssa_373 | |
| vec1 64 div ssa_375 = ushr ssa_373, ssa_14 | |
| vec1 64 div ssa_376 = iadd ssa_372, ssa_375 | |
| vec1 32 div ssa_377 = u2u32 ssa_376 | |
| vec1 32 div ssa_378 = umul_high ssa_358, ssa_359 | |
| vec1 32 div ssa_379 = imul ssa_358, ssa_359 | |
| vec1 64 div ssa_380 = pack_64_2x32_split ssa_379, ssa_378 | |
| vec1 64 div ssa_381 = u2u64 ssa_369 | |
| vec1 64 div ssa_382 = iadd ssa_380, ssa_381 | |
| vec1 64 div ssa_383 = ushr ssa_382, ssa_14 | |
| vec1 32 div ssa_384 = umul_high ssa_358, ssa_360 | |
| vec1 32 div ssa_385 = imul ssa_358, ssa_360 | |
| vec1 64 div ssa_386 = pack_64_2x32_split ssa_385, ssa_384 | |
| vec1 64 div ssa_387 = u2u64 ssa_374 | |
| vec1 64 div ssa_388 = iadd ssa_386, ssa_387 | |
| vec1 64 div ssa_389 = iadd ssa_388, ssa_383 | |
| vec1 32 div ssa_390 = u2u32 ssa_389 | |
| vec1 64 div ssa_391 = ushr ssa_389, ssa_14 | |
| vec1 32 div ssa_392 = umul_high ssa_358, ssa_1 | |
| vec1 64 div ssa_393 = pack_64_2x32_split ssa_1, ssa_392 | |
| vec1 64 div ssa_394 = u2u64 ssa_377 | |
| vec1 64 div ssa_395 = iadd ssa_393, ssa_394 | |
| vec1 64 div ssa_396 = iadd ssa_395, ssa_391 | |
| vec1 32 div ssa_397 = u2u32 ssa_396 | |
| vec1 32 div ssa_398 = umul_high ssa_1, ssa_359 | |
| vec1 64 div ssa_399 = pack_64_2x32_split ssa_1, ssa_398 | |
| vec1 64 div ssa_400 = u2u64 ssa_390 | |
| vec1 64 div ssa_401 = iadd ssa_399, ssa_400 | |
| vec1 32 div ssa_402 = u2u32 ssa_401 | |
| vec1 64 div ssa_403 = ushr ssa_401, ssa_14 | |
| vec1 32 div ssa_404 = umul_high ssa_1, ssa_360 | |
| vec1 64 div ssa_405 = pack_64_2x32_split ssa_1, ssa_404 | |
| vec1 64 div ssa_406 = u2u64 ssa_397 | |
| vec1 64 div ssa_407 = iadd ssa_405, ssa_406 | |
| vec1 64 div ssa_408 = iadd ssa_407, ssa_403 | |
| vec1 32 div ssa_409 = u2u32 ssa_408 | |
| vec1 64 div ssa_410 = u2u64 ssa_409 | |
| vec1 64 div ssa_411 = iadd ssa_399, ssa_410 | |
| vec1 32 div ssa_412 = u2u32 ssa_411 | |
| vec1 64 div ssa_413 = pack_64_2x32_split ssa_402, ssa_412 | |
| vec1 1 div ssa_414 = ieq ssa_413, ssa_0 | |
| vec1 32 div ssa_415 = iadd ssa_366, ssa_379 | |
| vec1 32 div ssa_416 = iadd ssa_361, ssa_415 | |
| vec1 64 div ssa_417 = pack_64_2x32_split ssa_362, ssa_416 | |
| vec1 64 div ssa_418 = uadd_sat ssa_417, ssa_40.f | |
| vec1 64 div ssa_419 = bcsel ssa_414, ssa_418, ssa_41 | |
| vec1 32 div ssa_420 = unpack_64_2x32_split_x ssa_36.g | |
| vec1 32 div ssa_421 = unpack_64_2x32_split_y ssa_36.g | |
| vec1 32 div ssa_422 = unpack_64_2x32_split_x ssa_38.g | |
| vec1 32 div ssa_423 = unpack_64_2x32_split_y ssa_38.g | |
| vec1 32 div ssa_424 = umul_high ssa_420, ssa_422 | |
| vec1 32 div ssa_425 = imul ssa_420, ssa_422 | |
| vec1 64 div ssa_426 = pack_64_2x32_split ssa_425, ssa_424 | |
| vec1 64 div ssa_427 = ushr ssa_426, ssa_14 | |
| vec1 32 div ssa_428 = umul_high ssa_420, ssa_423 | |
| vec1 32 div ssa_429 = imul ssa_420, ssa_423 | |
| vec1 64 div ssa_430 = pack_64_2x32_split ssa_429, ssa_428 | |
| vec1 64 div ssa_431 = iadd ssa_430, ssa_427 | |
| vec1 32 div ssa_432 = u2u32 ssa_431 | |
| vec1 64 div ssa_433 = ushr ssa_431, ssa_14 | |
| vec1 32 div ssa_434 = umul_high ssa_420, ssa_1 | |
| vec1 64 div ssa_435 = pack_64_2x32_split ssa_1, ssa_434 | |
| vec1 64 div ssa_436 = iadd ssa_435, ssa_433 | |
| vec1 32 div ssa_437 = u2u32 ssa_436 | |
| vec1 64 div ssa_438 = ushr ssa_436, ssa_14 | |
| vec1 64 div ssa_439 = iadd ssa_435, ssa_438 | |
| vec1 32 div ssa_440 = u2u32 ssa_439 | |
| vec1 32 div ssa_441 = umul_high ssa_421, ssa_422 | |
| vec1 32 div ssa_442 = imul ssa_421, ssa_422 | |
| vec1 64 div ssa_443 = pack_64_2x32_split ssa_442, ssa_441 | |
| vec1 64 div ssa_444 = u2u64 ssa_432 | |
| vec1 64 div ssa_445 = iadd ssa_443, ssa_444 | |
| vec1 64 div ssa_446 = ushr ssa_445, ssa_14 | |
| vec1 32 div ssa_447 = umul_high ssa_421, ssa_423 | |
| vec1 32 div ssa_448 = imul ssa_421, ssa_423 | |
| vec1 64 div ssa_449 = pack_64_2x32_split ssa_448, ssa_447 | |
| vec1 64 div ssa_450 = u2u64 ssa_437 | |
| vec1 64 div ssa_451 = iadd ssa_449, ssa_450 | |
| vec1 64 div ssa_452 = iadd ssa_451, ssa_446 | |
| vec1 32 div ssa_453 = u2u32 ssa_452 | |
| vec1 64 div ssa_454 = ushr ssa_452, ssa_14 | |
| vec1 32 div ssa_455 = umul_high ssa_421, ssa_1 | |
| vec1 64 div ssa_456 = pack_64_2x32_split ssa_1, ssa_455 | |
| vec1 64 div ssa_457 = u2u64 ssa_440 | |
| vec1 64 div ssa_458 = iadd ssa_456, ssa_457 | |
| vec1 64 div ssa_459 = iadd ssa_458, ssa_454 | |
| vec1 32 div ssa_460 = u2u32 ssa_459 | |
| vec1 32 div ssa_461 = umul_high ssa_1, ssa_422 | |
| vec1 64 div ssa_462 = pack_64_2x32_split ssa_1, ssa_461 | |
| vec1 64 div ssa_463 = u2u64 ssa_453 | |
| vec1 64 div ssa_464 = iadd ssa_462, ssa_463 | |
| vec1 32 div ssa_465 = u2u32 ssa_464 | |
| vec1 64 div ssa_466 = ushr ssa_464, ssa_14 | |
| vec1 32 div ssa_467 = umul_high ssa_1, ssa_423 | |
| vec1 64 div ssa_468 = pack_64_2x32_split ssa_1, ssa_467 | |
| vec1 64 div ssa_469 = u2u64 ssa_460 | |
| vec1 64 div ssa_470 = iadd ssa_468, ssa_469 | |
| vec1 64 div ssa_471 = iadd ssa_470, ssa_466 | |
| vec1 32 div ssa_472 = u2u32 ssa_471 | |
| vec1 64 div ssa_473 = u2u64 ssa_472 | |
| vec1 64 div ssa_474 = iadd ssa_462, ssa_473 | |
| vec1 32 div ssa_475 = u2u32 ssa_474 | |
| vec1 64 div ssa_476 = pack_64_2x32_split ssa_465, ssa_475 | |
| vec1 1 div ssa_477 = ieq ssa_476, ssa_0 | |
| vec1 32 div ssa_478 = iadd ssa_429, ssa_442 | |
| vec1 32 div ssa_479 = iadd ssa_424, ssa_478 | |
| vec1 64 div ssa_480 = pack_64_2x32_split ssa_425, ssa_479 | |
| vec1 64 div ssa_481 = uadd_sat ssa_480, ssa_40.g | |
| vec1 64 div ssa_482 = bcsel ssa_477, ssa_481, ssa_41 | |
| vec1 32 div ssa_483 = unpack_64_2x32_split_x ssa_36.h | |
| vec1 32 div ssa_484 = unpack_64_2x32_split_y ssa_36.h | |
| vec1 32 div ssa_485 = unpack_64_2x32_split_x ssa_38.h | |
| vec1 32 div ssa_486 = unpack_64_2x32_split_y ssa_38.h | |
| vec1 32 div ssa_487 = umul_high ssa_483, ssa_485 | |
| vec1 32 div ssa_488 = imul ssa_483, ssa_485 | |
| vec1 64 div ssa_489 = pack_64_2x32_split ssa_488, ssa_487 | |
| vec1 64 div ssa_490 = ushr ssa_489, ssa_14 | |
| vec1 32 div ssa_491 = umul_high ssa_483, ssa_486 | |
| vec1 32 div ssa_492 = imul ssa_483, ssa_486 | |
| vec1 64 div ssa_493 = pack_64_2x32_split ssa_492, ssa_491 | |
| vec1 64 div ssa_494 = iadd ssa_493, ssa_490 | |
| vec1 32 div ssa_495 = u2u32 ssa_494 | |
| vec1 64 div ssa_496 = ushr ssa_494, ssa_14 | |
| vec1 32 div ssa_497 = umul_high ssa_483, ssa_1 | |
| vec1 64 div ssa_498 = pack_64_2x32_split ssa_1, ssa_497 | |
| vec1 64 div ssa_499 = iadd ssa_498, ssa_496 | |
| vec1 32 div ssa_500 = u2u32 ssa_499 | |
| vec1 64 div ssa_501 = ushr ssa_499, ssa_14 | |
| vec1 64 div ssa_502 = iadd ssa_498, ssa_501 | |
| vec1 32 div ssa_503 = u2u32 ssa_502 | |
| vec1 32 div ssa_504 = umul_high ssa_484, ssa_485 | |
| vec1 32 div ssa_505 = imul ssa_484, ssa_485 | |
| vec1 64 div ssa_506 = pack_64_2x32_split ssa_505, ssa_504 | |
| vec1 64 div ssa_507 = u2u64 ssa_495 | |
| vec1 64 div ssa_508 = iadd ssa_506, ssa_507 | |
| vec1 64 div ssa_509 = ushr ssa_508, ssa_14 | |
| vec1 32 div ssa_510 = umul_high ssa_484, ssa_486 | |
| vec1 32 div ssa_511 = imul ssa_484, ssa_486 | |
| vec1 64 div ssa_512 = pack_64_2x32_split ssa_511, ssa_510 | |
| vec1 64 div ssa_513 = u2u64 ssa_500 | |
| vec1 64 div ssa_514 = iadd ssa_512, ssa_513 | |
| vec1 64 div ssa_515 = iadd ssa_514, ssa_509 | |
| vec1 32 div ssa_516 = u2u32 ssa_515 | |
| vec1 64 div ssa_517 = ushr ssa_515, ssa_14 | |
| vec1 32 div ssa_518 = umul_high ssa_484, ssa_1 | |
| vec1 64 div ssa_519 = pack_64_2x32_split ssa_1, ssa_518 | |
| vec1 64 div ssa_520 = u2u64 ssa_503 | |
| vec1 64 div ssa_521 = iadd ssa_519, ssa_520 | |
| vec1 64 div ssa_522 = iadd ssa_521, ssa_517 | |
| vec1 32 div ssa_523 = u2u32 ssa_522 | |
| vec1 32 div ssa_524 = umul_high ssa_1, ssa_485 | |
| vec1 64 div ssa_525 = pack_64_2x32_split ssa_1, ssa_524 | |
| vec1 64 div ssa_526 = u2u64 ssa_516 | |
| vec1 64 div ssa_527 = iadd ssa_525, ssa_526 | |
| vec1 32 div ssa_528 = u2u32 ssa_527 | |
| vec1 64 div ssa_529 = ushr ssa_527, ssa_14 | |
| vec1 32 div ssa_530 = umul_high ssa_1, ssa_486 | |
| vec1 64 div ssa_531 = pack_64_2x32_split ssa_1, ssa_530 | |
| vec1 64 div ssa_532 = u2u64 ssa_523 | |
| vec1 64 div ssa_533 = iadd ssa_531, ssa_532 | |
| vec1 64 div ssa_534 = iadd ssa_533, ssa_529 | |
| vec1 32 div ssa_535 = u2u32 ssa_534 | |
| vec1 64 div ssa_536 = u2u64 ssa_535 | |
| vec1 64 div ssa_537 = iadd ssa_525, ssa_536 | |
| vec1 32 div ssa_538 = u2u32 ssa_537 | |
| vec1 64 div ssa_539 = pack_64_2x32_split ssa_528, ssa_538 | |
| vec1 1 div ssa_540 = ieq ssa_539, ssa_0 | |
| vec1 32 div ssa_541 = iadd ssa_492, ssa_505 | |
| vec1 32 div ssa_542 = iadd ssa_487, ssa_541 | |
| vec1 64 div ssa_543 = pack_64_2x32_split ssa_488, ssa_542 | |
| vec1 64 div ssa_544 = uadd_sat ssa_543, ssa_40.h | |
| vec1 64 div ssa_545 = bcsel ssa_540, ssa_544, ssa_41 | |
| vec1 32 div ssa_546 = unpack_64_2x32_split_x ssa_36.i | |
| vec1 32 div ssa_547 = unpack_64_2x32_split_y ssa_36.i | |
| vec1 32 div ssa_548 = unpack_64_2x32_split_x ssa_38.i | |
| vec1 32 div ssa_549 = unpack_64_2x32_split_y ssa_38.i | |
| vec1 32 div ssa_550 = umul_high ssa_546, ssa_548 | |
| vec1 32 div ssa_551 = imul ssa_546, ssa_548 | |
| vec1 64 div ssa_552 = pack_64_2x32_split ssa_551, ssa_550 | |
| vec1 64 div ssa_553 = ushr ssa_552, ssa_14 | |
| vec1 32 div ssa_554 = umul_high ssa_546, ssa_549 | |
| vec1 32 div ssa_555 = imul ssa_546, ssa_549 | |
| vec1 64 div ssa_556 = pack_64_2x32_split ssa_555, ssa_554 | |
| vec1 64 div ssa_557 = iadd ssa_556, ssa_553 | |
| vec1 32 div ssa_558 = u2u32 ssa_557 | |
| vec1 64 div ssa_559 = ushr ssa_557, ssa_14 | |
| vec1 32 div ssa_560 = umul_high ssa_546, ssa_1 | |
| vec1 64 div ssa_561 = pack_64_2x32_split ssa_1, ssa_560 | |
| vec1 64 div ssa_562 = iadd ssa_561, ssa_559 | |
| vec1 32 div ssa_563 = u2u32 ssa_562 | |
| vec1 64 div ssa_564 = ushr ssa_562, ssa_14 | |
| vec1 64 div ssa_565 = iadd ssa_561, ssa_564 | |
| vec1 32 div ssa_566 = u2u32 ssa_565 | |
| vec1 32 div ssa_567 = umul_high ssa_547, ssa_548 | |
| vec1 32 div ssa_568 = imul ssa_547, ssa_548 | |
| vec1 64 div ssa_569 = pack_64_2x32_split ssa_568, ssa_567 | |
| vec1 64 div ssa_570 = u2u64 ssa_558 | |
| vec1 64 div ssa_571 = iadd ssa_569, ssa_570 | |
| vec1 64 div ssa_572 = ushr ssa_571, ssa_14 | |
| vec1 32 div ssa_573 = umul_high ssa_547, ssa_549 | |
| vec1 32 div ssa_574 = imul ssa_547, ssa_549 | |
| vec1 64 div ssa_575 = pack_64_2x32_split ssa_574, ssa_573 | |
| vec1 64 div ssa_576 = u2u64 ssa_563 | |
| vec1 64 div ssa_577 = iadd ssa_575, ssa_576 | |
| vec1 64 div ssa_578 = iadd ssa_577, ssa_572 | |
| vec1 32 div ssa_579 = u2u32 ssa_578 | |
| vec1 64 div ssa_580 = ushr ssa_578, ssa_14 | |
| vec1 32 div ssa_581 = umul_high ssa_547, ssa_1 | |
| vec1 64 div ssa_582 = pack_64_2x32_split ssa_1, ssa_581 | |
| vec1 64 div ssa_583 = u2u64 ssa_566 | |
| vec1 64 div ssa_584 = iadd ssa_582, ssa_583 | |
| vec1 64 div ssa_585 = iadd ssa_584, ssa_580 | |
| vec1 32 div ssa_586 = u2u32 ssa_585 | |
| vec1 32 div ssa_587 = umul_high ssa_1, ssa_548 | |
| vec1 64 div ssa_588 = pack_64_2x32_split ssa_1, ssa_587 | |
| vec1 64 div ssa_589 = u2u64 ssa_579 | |
| vec1 64 div ssa_590 = iadd ssa_588, ssa_589 | |
| vec1 32 div ssa_591 = u2u32 ssa_590 | |
| vec1 64 div ssa_592 = ushr ssa_590, ssa_14 | |
| vec1 32 div ssa_593 = umul_high ssa_1, ssa_549 | |
| vec1 64 div ssa_594 = pack_64_2x32_split ssa_1, ssa_593 | |
| vec1 64 div ssa_595 = u2u64 ssa_586 | |
| vec1 64 div ssa_596 = iadd ssa_594, ssa_595 | |
| vec1 64 div ssa_597 = iadd ssa_596, ssa_592 | |
| vec1 32 div ssa_598 = u2u32 ssa_597 | |
| vec1 64 div ssa_599 = u2u64 ssa_598 | |
| vec1 64 div ssa_600 = iadd ssa_588, ssa_599 | |
| vec1 32 div ssa_601 = u2u32 ssa_600 | |
| vec1 64 div ssa_602 = pack_64_2x32_split ssa_591, ssa_601 | |
| vec1 1 div ssa_603 = ieq ssa_602, ssa_0 | |
| vec1 32 div ssa_604 = iadd ssa_555, ssa_568 | |
| vec1 32 div ssa_605 = iadd ssa_550, ssa_604 | |
| vec1 64 div ssa_606 = pack_64_2x32_split ssa_551, ssa_605 | |
| vec1 64 div ssa_607 = uadd_sat ssa_606, ssa_40.i | |
| vec1 64 div ssa_608 = bcsel ssa_603, ssa_607, ssa_41 | |
| vec1 32 div ssa_609 = unpack_64_2x32_split_x ssa_36.j | |
| vec1 32 div ssa_610 = unpack_64_2x32_split_y ssa_36.j | |
| vec1 32 div ssa_611 = unpack_64_2x32_split_x ssa_38.j | |
| vec1 32 div ssa_612 = unpack_64_2x32_split_y ssa_38.j | |
| vec1 32 div ssa_613 = umul_high ssa_609, ssa_611 | |
| vec1 32 div ssa_614 = imul ssa_609, ssa_611 | |
| vec1 64 div ssa_615 = pack_64_2x32_split ssa_614, ssa_613 | |
| vec1 64 div ssa_616 = ushr ssa_615, ssa_14 | |
| vec1 32 div ssa_617 = umul_high ssa_609, ssa_612 | |
| vec1 32 div ssa_618 = imul ssa_609, ssa_612 | |
| vec1 64 div ssa_619 = pack_64_2x32_split ssa_618, ssa_617 | |
| vec1 64 div ssa_620 = iadd ssa_619, ssa_616 | |
| vec1 32 div ssa_621 = u2u32 ssa_620 | |
| vec1 64 div ssa_622 = ushr ssa_620, ssa_14 | |
| vec1 32 div ssa_623 = umul_high ssa_609, ssa_1 | |
| vec1 64 div ssa_624 = pack_64_2x32_split ssa_1, ssa_623 | |
| vec1 64 div ssa_625 = iadd ssa_624, ssa_622 | |
| vec1 32 div ssa_626 = u2u32 ssa_625 | |
| vec1 64 div ssa_627 = ushr ssa_625, ssa_14 | |
| vec1 64 div ssa_628 = iadd ssa_624, ssa_627 | |
| vec1 32 div ssa_629 = u2u32 ssa_628 | |
| vec1 32 div ssa_630 = umul_high ssa_610, ssa_611 | |
| vec1 32 div ssa_631 = imul ssa_610, ssa_611 | |
| vec1 64 div ssa_632 = pack_64_2x32_split ssa_631, ssa_630 | |
| vec1 64 div ssa_633 = u2u64 ssa_621 | |
| vec1 64 div ssa_634 = iadd ssa_632, ssa_633 | |
| vec1 64 div ssa_635 = ushr ssa_634, ssa_14 | |
| vec1 32 div ssa_636 = umul_high ssa_610, ssa_612 | |
| vec1 32 div ssa_637 = imul ssa_610, ssa_612 | |
| vec1 64 div ssa_638 = pack_64_2x32_split ssa_637, ssa_636 | |
| vec1 64 div ssa_639 = u2u64 ssa_626 | |
| vec1 64 div ssa_640 = iadd ssa_638, ssa_639 | |
| vec1 64 div ssa_641 = iadd ssa_640, ssa_635 | |
| vec1 32 div ssa_642 = u2u32 ssa_641 | |
| vec1 64 div ssa_643 = ushr ssa_641, ssa_14 | |
| vec1 32 div ssa_644 = umul_high ssa_610, ssa_1 | |
| vec1 64 div ssa_645 = pack_64_2x32_split ssa_1, ssa_644 | |
| vec1 64 div ssa_646 = u2u64 ssa_629 | |
| vec1 64 div ssa_647 = iadd ssa_645, ssa_646 | |
| vec1 64 div ssa_648 = iadd ssa_647, ssa_643 | |
| vec1 32 div ssa_649 = u2u32 ssa_648 | |
| vec1 32 div ssa_650 = umul_high ssa_1, ssa_611 | |
| vec1 64 div ssa_651 = pack_64_2x32_split ssa_1, ssa_650 | |
| vec1 64 div ssa_652 = u2u64 ssa_642 | |
| vec1 64 div ssa_653 = iadd ssa_651, ssa_652 | |
| vec1 32 div ssa_654 = u2u32 ssa_653 | |
| vec1 64 div ssa_655 = ushr ssa_653, ssa_14 | |
| vec1 32 div ssa_656 = umul_high ssa_1, ssa_612 | |
| vec1 64 div ssa_657 = pack_64_2x32_split ssa_1, ssa_656 | |
| vec1 64 div ssa_658 = u2u64 ssa_649 | |
| vec1 64 div ssa_659 = iadd ssa_657, ssa_658 | |
| vec1 64 div ssa_660 = iadd ssa_659, ssa_655 | |
| vec1 32 div ssa_661 = u2u32 ssa_660 | |
| vec1 64 div ssa_662 = u2u64 ssa_661 | |
| vec1 64 div ssa_663 = iadd ssa_651, ssa_662 | |
| vec1 32 div ssa_664 = u2u32 ssa_663 | |
| vec1 64 div ssa_665 = pack_64_2x32_split ssa_654, ssa_664 | |
| vec1 1 div ssa_666 = ieq ssa_665, ssa_0 | |
| vec1 32 div ssa_667 = iadd ssa_618, ssa_631 | |
| vec1 32 div ssa_668 = iadd ssa_613, ssa_667 | |
| vec1 64 div ssa_669 = pack_64_2x32_split ssa_614, ssa_668 | |
| vec1 64 div ssa_670 = uadd_sat ssa_669, ssa_40.j | |
| vec1 64 div ssa_671 = bcsel ssa_666, ssa_670, ssa_41 | |
| vec1 32 div ssa_672 = unpack_64_2x32_split_x ssa_36.k | |
| vec1 32 div ssa_673 = unpack_64_2x32_split_y ssa_36.k | |
| vec1 32 div ssa_674 = unpack_64_2x32_split_x ssa_38.k | |
| vec1 32 div ssa_675 = unpack_64_2x32_split_y ssa_38.k | |
| vec1 32 div ssa_676 = umul_high ssa_672, ssa_674 | |
| vec1 32 div ssa_677 = imul ssa_672, ssa_674 | |
| vec1 64 div ssa_678 = pack_64_2x32_split ssa_677, ssa_676 | |
| vec1 64 div ssa_679 = ushr ssa_678, ssa_14 | |
| vec1 32 div ssa_680 = umul_high ssa_672, ssa_675 | |
| vec1 32 div ssa_681 = imul ssa_672, ssa_675 | |
| vec1 64 div ssa_682 = pack_64_2x32_split ssa_681, ssa_680 | |
| vec1 64 div ssa_683 = iadd ssa_682, ssa_679 | |
| vec1 32 div ssa_684 = u2u32 ssa_683 | |
| vec1 64 div ssa_685 = ushr ssa_683, ssa_14 | |
| vec1 32 div ssa_686 = umul_high ssa_672, ssa_1 | |
| vec1 64 div ssa_687 = pack_64_2x32_split ssa_1, ssa_686 | |
| vec1 64 div ssa_688 = iadd ssa_687, ssa_685 | |
| vec1 32 div ssa_689 = u2u32 ssa_688 | |
| vec1 64 div ssa_690 = ushr ssa_688, ssa_14 | |
| vec1 64 div ssa_691 = iadd ssa_687, ssa_690 | |
| vec1 32 div ssa_692 = u2u32 ssa_691 | |
| vec1 32 div ssa_693 = umul_high ssa_673, ssa_674 | |
| vec1 32 div ssa_694 = imul ssa_673, ssa_674 | |
| vec1 64 div ssa_695 = pack_64_2x32_split ssa_694, ssa_693 | |
| vec1 64 div ssa_696 = u2u64 ssa_684 | |
| vec1 64 div ssa_697 = iadd ssa_695, ssa_696 | |
| vec1 64 div ssa_698 = ushr ssa_697, ssa_14 | |
| vec1 32 div ssa_699 = umul_high ssa_673, ssa_675 | |
| vec1 32 div ssa_700 = imul ssa_673, ssa_675 | |
| vec1 64 div ssa_701 = pack_64_2x32_split ssa_700, ssa_699 | |
| vec1 64 div ssa_702 = u2u64 ssa_689 | |
| vec1 64 div ssa_703 = iadd ssa_701, ssa_702 | |
| vec1 64 div ssa_704 = iadd ssa_703, ssa_698 | |
| vec1 32 div ssa_705 = u2u32 ssa_704 | |
| vec1 64 div ssa_706 = ushr ssa_704, ssa_14 | |
| vec1 32 div ssa_707 = umul_high ssa_673, ssa_1 | |
| vec1 64 div ssa_708 = pack_64_2x32_split ssa_1, ssa_707 | |
| vec1 64 div ssa_709 = u2u64 ssa_692 | |
| vec1 64 div ssa_710 = iadd ssa_708, ssa_709 | |
| vec1 64 div ssa_711 = iadd ssa_710, ssa_706 | |
| vec1 32 div ssa_712 = u2u32 ssa_711 | |
| vec1 32 div ssa_713 = umul_high ssa_1, ssa_674 | |
| vec1 64 div ssa_714 = pack_64_2x32_split ssa_1, ssa_713 | |
| vec1 64 div ssa_715 = u2u64 ssa_705 | |
| vec1 64 div ssa_716 = iadd ssa_714, ssa_715 | |
| vec1 32 div ssa_717 = u2u32 ssa_716 | |
| vec1 64 div ssa_718 = ushr ssa_716, ssa_14 | |
| vec1 32 div ssa_719 = umul_high ssa_1, ssa_675 | |
| vec1 64 div ssa_720 = pack_64_2x32_split ssa_1, ssa_719 | |
| vec1 64 div ssa_721 = u2u64 ssa_712 | |
| vec1 64 div ssa_722 = iadd ssa_720, ssa_721 | |
| vec1 64 div ssa_723 = iadd ssa_722, ssa_718 | |
| vec1 32 div ssa_724 = u2u32 ssa_723 | |
| vec1 64 div ssa_725 = u2u64 ssa_724 | |
| vec1 64 div ssa_726 = iadd ssa_714, ssa_725 | |
| vec1 32 div ssa_727 = u2u32 ssa_726 | |
| vec1 64 div ssa_728 = pack_64_2x32_split ssa_717, ssa_727 | |
| vec1 1 div ssa_729 = ieq ssa_728, ssa_0 | |
| vec1 32 div ssa_730 = iadd ssa_681, ssa_694 | |
| vec1 32 div ssa_731 = iadd ssa_676, ssa_730 | |
| vec1 64 div ssa_732 = pack_64_2x32_split ssa_677, ssa_731 | |
| vec1 64 div ssa_733 = uadd_sat ssa_732, ssa_40.k | |
| vec1 64 div ssa_734 = bcsel ssa_729, ssa_733, ssa_41 | |
| vec1 32 div ssa_735 = unpack_64_2x32_split_x ssa_36.l | |
| vec1 32 div ssa_736 = unpack_64_2x32_split_y ssa_36.l | |
| vec1 32 div ssa_737 = unpack_64_2x32_split_x ssa_38.l | |
| vec1 32 div ssa_738 = unpack_64_2x32_split_y ssa_38.l | |
| vec1 32 div ssa_739 = umul_high ssa_735, ssa_737 | |
| vec1 32 div ssa_740 = imul ssa_735, ssa_737 | |
| vec1 64 div ssa_741 = pack_64_2x32_split ssa_740, ssa_739 | |
| vec1 64 div ssa_742 = ushr ssa_741, ssa_14 | |
| vec1 32 div ssa_743 = umul_high ssa_735, ssa_738 | |
| vec1 32 div ssa_744 = imul ssa_735, ssa_738 | |
| vec1 64 div ssa_745 = pack_64_2x32_split ssa_744, ssa_743 | |
| vec1 64 div ssa_746 = iadd ssa_745, ssa_742 | |
| vec1 32 div ssa_747 = u2u32 ssa_746 | |
| vec1 64 div ssa_748 = ushr ssa_746, ssa_14 | |
| vec1 32 div ssa_749 = umul_high ssa_735, ssa_1 | |
| vec1 64 div ssa_750 = pack_64_2x32_split ssa_1, ssa_749 | |
| vec1 64 div ssa_751 = iadd ssa_750, ssa_748 | |
| vec1 32 div ssa_752 = u2u32 ssa_751 | |
| vec1 64 div ssa_753 = ushr ssa_751, ssa_14 | |
| vec1 64 div ssa_754 = iadd ssa_750, ssa_753 | |
| vec1 32 div ssa_755 = u2u32 ssa_754 | |
| vec1 32 div ssa_756 = umul_high ssa_736, ssa_737 | |
| vec1 32 div ssa_757 = imul ssa_736, ssa_737 | |
| vec1 64 div ssa_758 = pack_64_2x32_split ssa_757, ssa_756 | |
| vec1 64 div ssa_759 = u2u64 ssa_747 | |
| vec1 64 div ssa_760 = iadd ssa_758, ssa_759 | |
| vec1 64 div ssa_761 = ushr ssa_760, ssa_14 | |
| vec1 32 div ssa_762 = umul_high ssa_736, ssa_738 | |
| vec1 32 div ssa_763 = imul ssa_736, ssa_738 | |
| vec1 64 div ssa_764 = pack_64_2x32_split ssa_763, ssa_762 | |
| vec1 64 div ssa_765 = u2u64 ssa_752 | |
| vec1 64 div ssa_766 = iadd ssa_764, ssa_765 | |
| vec1 64 div ssa_767 = iadd ssa_766, ssa_761 | |
| vec1 32 div ssa_768 = u2u32 ssa_767 | |
| vec1 64 div ssa_769 = ushr ssa_767, ssa_14 | |
| vec1 32 div ssa_770 = umul_high ssa_736, ssa_1 | |
| vec1 64 div ssa_771 = pack_64_2x32_split ssa_1, ssa_770 | |
| vec1 64 div ssa_772 = u2u64 ssa_755 | |
| vec1 64 div ssa_773 = iadd ssa_771, ssa_772 | |
| vec1 64 div ssa_774 = iadd ssa_773, ssa_769 | |
| vec1 32 div ssa_775 = u2u32 ssa_774 | |
| vec1 32 div ssa_776 = umul_high ssa_1, ssa_737 | |
| vec1 64 div ssa_777 = pack_64_2x32_split ssa_1, ssa_776 | |
| vec1 64 div ssa_778 = u2u64 ssa_768 | |
| vec1 64 div ssa_779 = iadd ssa_777, ssa_778 | |
| vec1 32 div ssa_780 = u2u32 ssa_779 | |
| vec1 64 div ssa_781 = ushr ssa_779, ssa_14 | |
| vec1 32 div ssa_782 = umul_high ssa_1, ssa_738 | |
| vec1 64 div ssa_783 = pack_64_2x32_split ssa_1, ssa_782 | |
| vec1 64 div ssa_784 = u2u64 ssa_775 | |
| vec1 64 div ssa_785 = iadd ssa_783, ssa_784 | |
| vec1 64 div ssa_786 = iadd ssa_785, ssa_781 | |
| vec1 32 div ssa_787 = u2u32 ssa_786 | |
| vec1 64 div ssa_788 = u2u64 ssa_787 | |
| vec1 64 div ssa_789 = iadd ssa_777, ssa_788 | |
| vec1 32 div ssa_790 = u2u32 ssa_789 | |
| vec1 64 div ssa_791 = pack_64_2x32_split ssa_780, ssa_790 | |
| vec1 1 div ssa_792 = ieq ssa_791, ssa_0 | |
| vec1 32 div ssa_793 = iadd ssa_744, ssa_757 | |
| vec1 32 div ssa_794 = iadd ssa_739, ssa_793 | |
| vec1 64 div ssa_795 = pack_64_2x32_split ssa_740, ssa_794 | |
| vec1 64 div ssa_796 = uadd_sat ssa_795, ssa_40.l | |
| vec1 64 div ssa_797 = bcsel ssa_792, ssa_796, ssa_41 | |
| vec1 32 div ssa_798 = unpack_64_2x32_split_x ssa_36.m | |
| vec1 32 div ssa_799 = unpack_64_2x32_split_y ssa_36.m | |
| vec1 32 div ssa_800 = unpack_64_2x32_split_x ssa_38.m | |
| vec1 32 div ssa_801 = unpack_64_2x32_split_y ssa_38.m | |
| vec1 32 div ssa_802 = umul_high ssa_798, ssa_800 | |
| vec1 32 div ssa_803 = imul ssa_798, ssa_800 | |
| vec1 64 div ssa_804 = pack_64_2x32_split ssa_803, ssa_802 | |
| vec1 64 div ssa_805 = ushr ssa_804, ssa_14 | |
| vec1 32 div ssa_806 = umul_high ssa_798, ssa_801 | |
| vec1 32 div ssa_807 = imul ssa_798, ssa_801 | |
| vec1 64 div ssa_808 = pack_64_2x32_split ssa_807, ssa_806 | |
| vec1 64 div ssa_809 = iadd ssa_808, ssa_805 | |
| vec1 32 div ssa_810 = u2u32 ssa_809 | |
| vec1 64 div ssa_811 = ushr ssa_809, ssa_14 | |
| vec1 32 div ssa_812 = umul_high ssa_798, ssa_1 | |
| vec1 64 div ssa_813 = pack_64_2x32_split ssa_1, ssa_812 | |
| vec1 64 div ssa_814 = iadd ssa_813, ssa_811 | |
| vec1 32 div ssa_815 = u2u32 ssa_814 | |
| vec1 64 div ssa_816 = ushr ssa_814, ssa_14 | |
| vec1 64 div ssa_817 = iadd ssa_813, ssa_816 | |
| vec1 32 div ssa_818 = u2u32 ssa_817 | |
| vec1 32 div ssa_819 = umul_high ssa_799, ssa_800 | |
| vec1 32 div ssa_820 = imul ssa_799, ssa_800 | |
| vec1 64 div ssa_821 = pack_64_2x32_split ssa_820, ssa_819 | |
| vec1 64 div ssa_822 = u2u64 ssa_810 | |
| vec1 64 div ssa_823 = iadd ssa_821, ssa_822 | |
| vec1 64 div ssa_824 = ushr ssa_823, ssa_14 | |
| vec1 32 div ssa_825 = umul_high ssa_799, ssa_801 | |
| vec1 32 div ssa_826 = imul ssa_799, ssa_801 | |
| vec1 64 div ssa_827 = pack_64_2x32_split ssa_826, ssa_825 | |
| vec1 64 div ssa_828 = u2u64 ssa_815 | |
| vec1 64 div ssa_829 = iadd ssa_827, ssa_828 | |
| vec1 64 div ssa_830 = iadd ssa_829, ssa_824 | |
| vec1 32 div ssa_831 = u2u32 ssa_830 | |
| vec1 64 div ssa_832 = ushr ssa_830, ssa_14 | |
| vec1 32 div ssa_833 = umul_high ssa_799, ssa_1 | |
| vec1 64 div ssa_834 = pack_64_2x32_split ssa_1, ssa_833 | |
| vec1 64 div ssa_835 = u2u64 ssa_818 | |
| vec1 64 div ssa_836 = iadd ssa_834, ssa_835 | |
| vec1 64 div ssa_837 = iadd ssa_836, ssa_832 | |
| vec1 32 div ssa_838 = u2u32 ssa_837 | |
| vec1 32 div ssa_839 = umul_high ssa_1, ssa_800 | |
| vec1 64 div ssa_840 = pack_64_2x32_split ssa_1, ssa_839 | |
| vec1 64 div ssa_841 = u2u64 ssa_831 | |
| vec1 64 div ssa_842 = iadd ssa_840, ssa_841 | |
| vec1 32 div ssa_843 = u2u32 ssa_842 | |
| vec1 64 div ssa_844 = ushr ssa_842, ssa_14 | |
| vec1 32 div ssa_845 = umul_high ssa_1, ssa_801 | |
| vec1 64 div ssa_846 = pack_64_2x32_split ssa_1, ssa_845 | |
| vec1 64 div ssa_847 = u2u64 ssa_838 | |
| vec1 64 div ssa_848 = iadd ssa_846, ssa_847 | |
| vec1 64 div ssa_849 = iadd ssa_848, ssa_844 | |
| vec1 32 div ssa_850 = u2u32 ssa_849 | |
| vec1 64 div ssa_851 = u2u64 ssa_850 | |
| vec1 64 div ssa_852 = iadd ssa_840, ssa_851 | |
| vec1 32 div ssa_853 = u2u32 ssa_852 | |
| vec1 64 div ssa_854 = pack_64_2x32_split ssa_843, ssa_853 | |
| vec1 1 div ssa_855 = ieq ssa_854, ssa_0 | |
| vec1 32 div ssa_856 = iadd ssa_807, ssa_820 | |
| vec1 32 div ssa_857 = iadd ssa_802, ssa_856 | |
| vec1 64 div ssa_858 = pack_64_2x32_split ssa_803, ssa_857 | |
| vec1 64 div ssa_859 = uadd_sat ssa_858, ssa_40.m | |
| vec1 64 div ssa_860 = bcsel ssa_855, ssa_859, ssa_41 | |
| vec1 32 div ssa_861 = unpack_64_2x32_split_x ssa_36.n | |
| vec1 32 div ssa_862 = unpack_64_2x32_split_y ssa_36.n | |
| vec1 32 div ssa_863 = unpack_64_2x32_split_x ssa_38.n | |
| vec1 32 div ssa_864 = unpack_64_2x32_split_y ssa_38.n | |
| vec1 32 div ssa_865 = umul_high ssa_861, ssa_863 | |
| vec1 32 div ssa_866 = imul ssa_861, ssa_863 | |
| vec1 64 div ssa_867 = pack_64_2x32_split ssa_866, ssa_865 | |
| vec1 64 div ssa_868 = ushr ssa_867, ssa_14 | |
| vec1 32 div ssa_869 = umul_high ssa_861, ssa_864 | |
| vec1 32 div ssa_870 = imul ssa_861, ssa_864 | |
| vec1 64 div ssa_871 = pack_64_2x32_split ssa_870, ssa_869 | |
| vec1 64 div ssa_872 = iadd ssa_871, ssa_868 | |
| vec1 32 div ssa_873 = u2u32 ssa_872 | |
| vec1 64 div ssa_874 = ushr ssa_872, ssa_14 | |
| vec1 32 div ssa_875 = umul_high ssa_861, ssa_1 | |
| vec1 64 div ssa_876 = pack_64_2x32_split ssa_1, ssa_875 | |
| vec1 64 div ssa_877 = iadd ssa_876, ssa_874 | |
| vec1 32 div ssa_878 = u2u32 ssa_877 | |
| vec1 64 div ssa_879 = ushr ssa_877, ssa_14 | |
| vec1 64 div ssa_880 = iadd ssa_876, ssa_879 | |
| vec1 32 div ssa_881 = u2u32 ssa_880 | |
| vec1 32 div ssa_882 = umul_high ssa_862, ssa_863 | |
| vec1 32 div ssa_883 = imul ssa_862, ssa_863 | |
| vec1 64 div ssa_884 = pack_64_2x32_split ssa_883, ssa_882 | |
| vec1 64 div ssa_885 = u2u64 ssa_873 | |
| vec1 64 div ssa_886 = iadd ssa_884, ssa_885 | |
| vec1 64 div ssa_887 = ushr ssa_886, ssa_14 | |
| vec1 32 div ssa_888 = umul_high ssa_862, ssa_864 | |
| vec1 32 div ssa_889 = imul ssa_862, ssa_864 | |
| vec1 64 div ssa_890 = pack_64_2x32_split ssa_889, ssa_888 | |
| vec1 64 div ssa_891 = u2u64 ssa_878 | |
| vec1 64 div ssa_892 = iadd ssa_890, ssa_891 | |
| vec1 64 div ssa_893 = iadd ssa_892, ssa_887 | |
| vec1 32 div ssa_894 = u2u32 ssa_893 | |
| vec1 64 div ssa_895 = ushr ssa_893, ssa_14 | |
| vec1 32 div ssa_896 = umul_high ssa_862, ssa_1 | |
| vec1 64 div ssa_897 = pack_64_2x32_split ssa_1, ssa_896 | |
| vec1 64 div ssa_898 = u2u64 ssa_881 | |
| vec1 64 div ssa_899 = iadd ssa_897, ssa_898 | |
| vec1 64 div ssa_900 = iadd ssa_899, ssa_895 | |
| vec1 32 div ssa_901 = u2u32 ssa_900 | |
| vec1 32 div ssa_902 = umul_high ssa_1, ssa_863 | |
| vec1 64 div ssa_903 = pack_64_2x32_split ssa_1, ssa_902 | |
| vec1 64 div ssa_904 = u2u64 ssa_894 | |
| vec1 64 div ssa_905 = iadd ssa_903, ssa_904 | |
| vec1 32 div ssa_906 = u2u32 ssa_905 | |
| vec1 64 div ssa_907 = ushr ssa_905, ssa_14 | |
| vec1 32 div ssa_908 = umul_high ssa_1, ssa_864 | |
| vec1 64 div ssa_909 = pack_64_2x32_split ssa_1, ssa_908 | |
| vec1 64 div ssa_910 = u2u64 ssa_901 | |
| vec1 64 div ssa_911 = iadd ssa_909, ssa_910 | |
| vec1 64 div ssa_912 = iadd ssa_911, ssa_907 | |
| vec1 32 div ssa_913 = u2u32 ssa_912 | |
| vec1 64 div ssa_914 = u2u64 ssa_913 | |
| vec1 64 div ssa_915 = iadd ssa_903, ssa_914 | |
| vec1 32 div ssa_916 = u2u32 ssa_915 | |
| vec1 64 div ssa_917 = pack_64_2x32_split ssa_906, ssa_916 | |
| vec1 1 div ssa_918 = ieq ssa_917, ssa_0 | |
| vec1 32 div ssa_919 = iadd ssa_870, ssa_883 | |
| vec1 32 div ssa_920 = iadd ssa_865, ssa_919 | |
| vec1 64 div ssa_921 = pack_64_2x32_split ssa_866, ssa_920 | |
| vec1 64 div ssa_922 = uadd_sat ssa_921, ssa_40.n | |
| vec1 64 div ssa_923 = bcsel ssa_918, ssa_922, ssa_41 | |
| vec1 32 div ssa_924 = unpack_64_2x32_split_x ssa_36.o | |
| vec1 32 div ssa_925 = unpack_64_2x32_split_y ssa_36.o | |
| vec1 32 div ssa_926 = unpack_64_2x32_split_x ssa_38.o | |
| vec1 32 div ssa_927 = unpack_64_2x32_split_y ssa_38.o | |
| vec1 32 div ssa_928 = umul_high ssa_924, ssa_926 | |
| vec1 32 div ssa_929 = imul ssa_924, ssa_926 | |
| vec1 64 div ssa_930 = pack_64_2x32_split ssa_929, ssa_928 | |
| vec1 64 div ssa_931 = ushr ssa_930, ssa_14 | |
| vec1 32 div ssa_932 = umul_high ssa_924, ssa_927 | |
| vec1 32 div ssa_933 = imul ssa_924, ssa_927 | |
| vec1 64 div ssa_934 = pack_64_2x32_split ssa_933, ssa_932 | |
| vec1 64 div ssa_935 = iadd ssa_934, ssa_931 | |
| vec1 32 div ssa_936 = u2u32 ssa_935 | |
| vec1 64 div ssa_937 = ushr ssa_935, ssa_14 | |
| vec1 32 div ssa_938 = umul_high ssa_924, ssa_1 | |
| vec1 64 div ssa_939 = pack_64_2x32_split ssa_1, ssa_938 | |
| vec1 64 div ssa_940 = iadd ssa_939, ssa_937 | |
| vec1 32 div ssa_941 = u2u32 ssa_940 | |
| vec1 64 div ssa_942 = ushr ssa_940, ssa_14 | |
| vec1 64 div ssa_943 = iadd ssa_939, ssa_942 | |
| vec1 32 div ssa_944 = u2u32 ssa_943 | |
| vec1 32 div ssa_945 = umul_high ssa_925, ssa_926 | |
| vec1 32 div ssa_946 = imul ssa_925, ssa_926 | |
| vec1 64 div ssa_947 = pack_64_2x32_split ssa_946, ssa_945 | |
| vec1 64 div ssa_948 = u2u64 ssa_936 | |
| vec1 64 div ssa_949 = iadd ssa_947, ssa_948 | |
| vec1 64 div ssa_950 = ushr ssa_949, ssa_14 | |
| vec1 32 div ssa_951 = umul_high ssa_925, ssa_927 | |
| vec1 32 div ssa_952 = imul ssa_925, ssa_927 | |
| vec1 64 div ssa_953 = pack_64_2x32_split ssa_952, ssa_951 | |
| vec1 64 div ssa_954 = u2u64 ssa_941 | |
| vec1 64 div ssa_955 = iadd ssa_953, ssa_954 | |
| vec1 64 div ssa_956 = iadd ssa_955, ssa_950 | |
| vec1 32 div ssa_957 = u2u32 ssa_956 | |
| vec1 64 div ssa_958 = ushr ssa_956, ssa_14 | |
| vec1 32 div ssa_959 = umul_high ssa_925, ssa_1 | |
| vec1 64 div ssa_960 = pack_64_2x32_split ssa_1, ssa_959 | |
| vec1 64 div ssa_961 = u2u64 ssa_944 | |
| vec1 64 div ssa_962 = iadd ssa_960, ssa_961 | |
| vec1 64 div ssa_963 = iadd ssa_962, ssa_958 | |
| vec1 32 div ssa_964 = u2u32 ssa_963 | |
| vec1 32 div ssa_965 = umul_high ssa_1, ssa_926 | |
| vec1 64 div ssa_966 = pack_64_2x32_split ssa_1, ssa_965 | |
| vec1 64 div ssa_967 = u2u64 ssa_957 | |
| vec1 64 div ssa_968 = iadd ssa_966, ssa_967 | |
| vec1 32 div ssa_969 = u2u32 ssa_968 | |
| vec1 64 div ssa_970 = ushr ssa_968, ssa_14 | |
| vec1 32 div ssa_971 = umul_high ssa_1, ssa_927 | |
| vec1 64 div ssa_972 = pack_64_2x32_split ssa_1, ssa_971 | |
| vec1 64 div ssa_973 = u2u64 ssa_964 | |
| vec1 64 div ssa_974 = iadd ssa_972, ssa_973 | |
| vec1 64 div ssa_975 = iadd ssa_974, ssa_970 | |
| vec1 32 div ssa_976 = u2u32 ssa_975 | |
| vec1 64 div ssa_977 = u2u64 ssa_976 | |
| vec1 64 div ssa_978 = iadd ssa_966, ssa_977 | |
| vec1 32 div ssa_979 = u2u32 ssa_978 | |
| vec1 64 div ssa_980 = pack_64_2x32_split ssa_969, ssa_979 | |
| vec1 1 div ssa_981 = ieq ssa_980, ssa_0 | |
| vec1 32 div ssa_982 = iadd ssa_933, ssa_946 | |
| vec1 32 div ssa_983 = iadd ssa_928, ssa_982 | |
| vec1 64 div ssa_984 = pack_64_2x32_split ssa_929, ssa_983 | |
| vec1 64 div ssa_985 = uadd_sat ssa_984, ssa_40.o | |
| vec1 64 div ssa_986 = bcsel ssa_981, ssa_985, ssa_41 | |
| vec1 32 div ssa_987 = unpack_64_2x32_split_x ssa_36.p | |
| vec1 32 div ssa_988 = unpack_64_2x32_split_y ssa_36.p | |
| vec1 32 div ssa_989 = unpack_64_2x32_split_x ssa_38.p | |
| vec1 32 div ssa_990 = unpack_64_2x32_split_y ssa_38.p | |
| vec1 32 div ssa_991 = umul_high ssa_987, ssa_989 | |
| vec1 32 div ssa_992 = imul ssa_987, ssa_989 | |
| vec1 64 div ssa_993 = pack_64_2x32_split ssa_992, ssa_991 | |
| vec1 64 div ssa_994 = ushr ssa_993, ssa_14 | |
| vec1 32 div ssa_995 = umul_high ssa_987, ssa_990 | |
| vec1 32 div ssa_996 = imul ssa_987, ssa_990 | |
| vec1 64 div ssa_997 = pack_64_2x32_split ssa_996, ssa_995 | |
| vec1 64 div ssa_998 = iadd ssa_997, ssa_994 | |
| vec1 32 div ssa_999 = u2u32 ssa_998 | |
| vec1 64 div ssa_1000 = ushr ssa_998, ssa_14 | |
| vec1 32 div ssa_1001 = umul_high ssa_987, ssa_1 | |
| vec1 64 div ssa_1002 = pack_64_2x32_split ssa_1, ssa_1001 | |
| vec1 64 div ssa_1003 = iadd ssa_1002, ssa_1000 | |
| vec1 32 div ssa_1004 = u2u32 ssa_1003 | |
| vec1 64 div ssa_1005 = ushr ssa_1003, ssa_14 | |
| vec1 64 div ssa_1006 = iadd ssa_1002, ssa_1005 | |
| vec1 32 div ssa_1007 = u2u32 ssa_1006 | |
| vec1 32 div ssa_1008 = umul_high ssa_988, ssa_989 | |
| vec1 32 div ssa_1009 = imul ssa_988, ssa_989 | |
| vec1 64 div ssa_1010 = pack_64_2x32_split ssa_1009, ssa_1008 | |
| vec1 64 div ssa_1011 = u2u64 ssa_999 | |
| vec1 64 div ssa_1012 = iadd ssa_1010, ssa_1011 | |
| vec1 64 div ssa_1013 = ushr ssa_1012, ssa_14 | |
| vec1 32 div ssa_1014 = umul_high ssa_988, ssa_990 | |
| vec1 32 div ssa_1015 = imul ssa_988, ssa_990 | |
| vec1 64 div ssa_1016 = pack_64_2x32_split ssa_1015, ssa_1014 | |
| vec1 64 div ssa_1017 = u2u64 ssa_1004 | |
| vec1 64 div ssa_1018 = iadd ssa_1016, ssa_1017 | |
| vec1 64 div ssa_1019 = iadd ssa_1018, ssa_1013 | |
| vec1 32 div ssa_1020 = u2u32 ssa_1019 | |
| vec1 64 div ssa_1021 = ushr ssa_1019, ssa_14 | |
| vec1 32 div ssa_1022 = umul_high ssa_988, ssa_1 | |
| vec1 64 div ssa_1023 = pack_64_2x32_split ssa_1, ssa_1022 | |
| vec1 64 div ssa_1024 = u2u64 ssa_1007 | |
| vec1 64 div ssa_1025 = iadd ssa_1023, ssa_1024 | |
| vec1 64 div ssa_1026 = iadd ssa_1025, ssa_1021 | |
| vec1 32 div ssa_1027 = u2u32 ssa_1026 | |
| vec1 32 div ssa_1028 = umul_high ssa_1, ssa_989 | |
| vec1 64 div ssa_1029 = pack_64_2x32_split ssa_1, ssa_1028 | |
| vec1 64 div ssa_1030 = u2u64 ssa_1020 | |
| vec1 64 div ssa_1031 = iadd ssa_1029, ssa_1030 | |
| vec1 32 div ssa_1032 = u2u32 ssa_1031 | |
| vec1 64 div ssa_1033 = ushr ssa_1031, ssa_14 | |
| vec1 32 div ssa_1034 = umul_high ssa_1, ssa_990 | |
| vec1 64 div ssa_1035 = pack_64_2x32_split ssa_1, ssa_1034 | |
| vec1 64 div ssa_1036 = u2u64 ssa_1027 | |
| vec1 64 div ssa_1037 = iadd ssa_1035, ssa_1036 | |
| vec1 64 div ssa_1038 = iadd ssa_1037, ssa_1033 | |
| vec1 32 div ssa_1039 = u2u32 ssa_1038 | |
| vec1 64 div ssa_1040 = u2u64 ssa_1039 | |
| vec1 64 div ssa_1041 = iadd ssa_1029, ssa_1040 | |
| vec1 32 div ssa_1042 = u2u32 ssa_1041 | |
| vec1 64 div ssa_1043 = pack_64_2x32_split ssa_1032, ssa_1042 | |
| vec1 1 div ssa_1044 = ieq ssa_1043, ssa_0 | |
| vec1 32 div ssa_1045 = iadd ssa_996, ssa_1009 | |
| vec1 32 div ssa_1046 = iadd ssa_991, ssa_1045 | |
| vec1 64 div ssa_1047 = pack_64_2x32_split ssa_992, ssa_1046 | |
| vec1 64 div ssa_1048 = uadd_sat ssa_1047, ssa_40.p | |
| vec1 64 div ssa_1049 = bcsel ssa_1044, ssa_1048, ssa_41 | |
| vec16 64 div ssa_1050 = vec16 ssa_104, ssa_167, ssa_230, ssa_293, ssa_356, ssa_419, ssa_482, ssa_545, ssa_608, ssa_671, ssa_734, ssa_797, ssa_860, ssa_923, ssa_986, ssa_1049 | |
| vec1 64 div ssa_1051 = iadd ssa_13, ssa_34 | |
| intrinsic store_global (ssa_1050, ssa_1051) (wrmask=abcdefghijklmnop, access=0, align_mul=128, align_offset=0) | |
| /* succs: block_1 */ | |
| block block_1: | |
| } | |
| radeonsi: Compiling shader 1 | |
| Compute Shader LLVM IR: | |
| ; ModuleID = 'mesa-shader' | |
| source_filename = "mesa-shader" | |
| target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7" | |
| target triple = "amdgcn--" | |
| @compute_lds = external addrspace(3) global [0 x i8], align 65536 | |
| define amdgpu_cs void @main(ptr addrspace(6) inreg noalias align 4 dereferenceable(18446744073709551615) %0, ptr addrspace(6) inreg noalias align 4 dereferenceable(18446744073709551615) %1, ptr addrspace(6) inreg noalias align 4 dereferenceable(18446744073709551615) %2, ptr addrspace(6) inreg noalias align 4 dereferenceable(18446744073709551615) %3, i32 inreg %4, i32 inreg %5, <3 x i32> %6) #0 { | |
| main_body: | |
| %7 = ptrtoint ptr addrspace(6) %2 to i32 | |
| %8 = insertelement <4 x i32> <i32 poison, i32 32768, i32 1024, i32 822177708>, i32 %7, i64 0 | |
| %9 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 0, i32 0) #3, !invariant.load !0 | |
| %10 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 4, i32 0) #3, !invariant.load !0 | |
| %11 = insertelement <2 x float> undef, float %9, i64 0 | |
| %12 = insertelement <2 x float> %11, float %10, i64 1 | |
| %13 = bitcast <2 x float> %12 to i64 | |
| %14 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 8, i32 0) #3, !invariant.load !0 | |
| %15 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 12, i32 0) #3, !invariant.load !0 | |
| %16 = insertelement <2 x float> undef, float %14, i64 0 | |
| %17 = insertelement <2 x float> %16, float %15, i64 1 | |
| %18 = bitcast <2 x float> %17 to i64 | |
| %19 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 16, i32 0) #3, !invariant.load !0 | |
| %20 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 20, i32 0) #3, !invariant.load !0 | |
| %21 = insertelement <2 x float> undef, float %19, i64 0 | |
| %22 = insertelement <2 x float> %21, float %20, i64 1 | |
| %23 = bitcast <2 x float> %22 to i64 | |
| %24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 24, i32 0) #3, !invariant.load !0 | |
| %25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 28, i32 0) #3, !invariant.load !0 | |
| %26 = insertelement <2 x float> undef, float %24, i64 0 | |
| %27 = insertelement <2 x float> %26, float %25, i64 1 | |
| %28 = bitcast <2 x float> %27 to i64 | |
| %29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 32, i32 0) #3, !invariant.load !0 | |
| %30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %8, i32 36, i32 0) #3, !invariant.load !0 | |
| %31 = insertelement <6 x float> undef, float %29, i64 0 | |
| %32 = insertelement <6 x float> %31, float %30, i64 1 | |
| %33 = bitcast <6 x float> %32 to <3 x i64> | |
| %34 = and i32 %4, 1023 | |
| %35 = extractelement <3 x i32> %6, i64 0 | |
| %36 = zext i32 %35 to i64 | |
| %37 = zext i32 %5 to i64 | |
| %38 = zext i32 %34 to i64 | |
| %39 = mul nuw nsw i64 %37, %38 | |
| %40 = lshr i64 %39, 32 | |
| %41 = trunc i64 %40 to i32 | |
| %42 = mul i32 %34, %5 | |
| %43 = insertelement <2 x i32> undef, i32 %42, i64 0 | |
| %44 = insertelement <2 x i32> %43, i32 %41, i64 1 | |
| %45 = bitcast <2 x i32> %44 to i64 | |
| %46 = add nuw i64 %45, %36 | |
| %47 = extractelement <3 x i64> %33, i64 0 | |
| %48 = add i64 %46, %47 | |
| %sext = shl i64 %48, 32 | |
| %49 = ashr exact i64 %sext, 25 | |
| %50 = add i64 %49, %13 | |
| %51 = inttoptr i64 %50 to ptr addrspace(1) | |
| %52 = load <16 x i64>, ptr addrspace(1) %51, align 128 | |
| %53 = add i64 %49, %18 | |
| %54 = inttoptr i64 %53 to ptr addrspace(1) | |
| %55 = load <16 x i64>, ptr addrspace(1) %54, align 128 | |
| %56 = add i64 %49, %23 | |
| %57 = inttoptr i64 %56 to ptr addrspace(1) | |
| %58 = load <16 x i64>, ptr addrspace(1) %57, align 128 | |
| %59 = extractelement <16 x i64> %52, i64 0 | |
| %60 = trunc i64 %59 to i32 | |
| %extelt.offset = lshr i64 %59, 32 | |
| %61 = trunc i64 %extelt.offset to i32 | |
| %62 = extractelement <16 x i64> %55, i64 0 | |
| %63 = trunc i64 %62 to i32 | |
| %extelt.offset2 = lshr i64 %62, 32 | |
| %64 = trunc i64 %extelt.offset2 to i32 | |
| %65 = and i64 %59, 4294967295 | |
| %66 = and i64 %62, 4294967295 | |
| %67 = mul nuw i64 %65, %66 | |
| %68 = lshr i64 %67, 32 | |
| %69 = trunc i64 %68 to i32 | |
| %70 = mul i32 %60, %63 | |
| %71 = insertelement <2 x i32> undef, i32 %70, i64 0 | |
| %72 = insertelement <2 x i32> %71, i32 %69, i64 1 | |
| %73 = bitcast <2 x i32> %72 to i64 | |
| %74 = lshr i64 %73, 32 | |
| %75 = mul nuw i64 %65, %extelt.offset2 | |
| %76 = lshr i64 %75, 32 | |
| %77 = trunc i64 %76 to i32 | |
| %78 = mul i32 %60, %64 | |
| %79 = insertelement <2 x i32> undef, i32 %78, i64 0 | |
| %80 = insertelement <2 x i32> %79, i32 %77, i64 1 | |
| %81 = bitcast <2 x i32> %80 to i64 | |
| %82 = add i64 %74, %81 | |
| %83 = lshr i64 %82, 32 | |
| %84 = mul nuw i64 %extelt.offset, %66 | |
| %85 = lshr i64 %84, 32 | |
| %86 = trunc i64 %85 to i32 | |
| %87 = mul i32 %61, %63 | |
| %88 = insertelement <2 x i32> undef, i32 %87, i64 0 | |
| %89 = insertelement <2 x i32> %88, i32 %86, i64 1 | |
| %90 = bitcast <2 x i32> %89 to i64 | |
| %91 = and i64 %82, 4294967295 | |
| %92 = add i64 %91, %90 | |
| %93 = lshr i64 %92, 32 | |
| %94 = mul nuw i64 %extelt.offset, %extelt.offset2 | |
| %95 = lshr i64 %94, 32 | |
| %96 = trunc i64 %95 to i32 | |
| %97 = mul i32 %61, %64 | |
| %98 = insertelement <2 x i32> undef, i32 %97, i64 0 | |
| %99 = insertelement <2 x i32> %98, i32 %96, i64 1 | |
| %100 = bitcast <2 x i32> %99 to i64 | |
| %101 = add i64 %83, %100 | |
| %102 = add i64 %101, %93 | |
| %103 = trunc i64 %102 to i32 | |
| %104 = lshr i64 %102, 32 | |
| %105 = trunc i64 %104 to i32 | |
| %106 = insertelement <2 x i32> undef, i32 %103, i64 0 | |
| %107 = insertelement <2 x i32> %106, i32 %105, i64 1 | |
| %108 = bitcast <2 x i32> %107 to i64 | |
| %109 = icmp eq i64 %108, 0 | |
| %110 = add i32 %78, %87 | |
| %111 = add i32 %110, %69 | |
| %112 = insertelement <2 x i32> %71, i32 %111, i64 1 | |
| %113 = bitcast <2 x i32> %112 to i64 | |
| %114 = extractelement <16 x i64> %58, i64 0 | |
| %115 = call i64 @llvm.uadd.sat.i64(i64 %113, i64 %114) #3 | |
| %116 = select i1 %109, i64 %115, i64 -1 | |
| %117 = extractelement <16 x i64> %52, i64 1 | |
| %118 = trunc i64 %117 to i32 | |
| %extelt.offset4 = lshr i64 %117, 32 | |
| %119 = trunc i64 %extelt.offset4 to i32 | |
| %120 = extractelement <16 x i64> %55, i64 1 | |
| %121 = trunc i64 %120 to i32 | |
| %extelt.offset6 = lshr i64 %120, 32 | |
| %122 = trunc i64 %extelt.offset6 to i32 | |
| %123 = and i64 %117, 4294967295 | |
| %124 = and i64 %120, 4294967295 | |
| %125 = mul nuw i64 %123, %124 | |
| %126 = lshr i64 %125, 32 | |
| %127 = trunc i64 %126 to i32 | |
| %128 = mul i32 %118, %121 | |
| %129 = insertelement <2 x i32> undef, i32 %128, i64 0 | |
| %130 = insertelement <2 x i32> %129, i32 %127, i64 1 | |
| %131 = bitcast <2 x i32> %130 to i64 | |
| %132 = lshr i64 %131, 32 | |
| %133 = mul nuw i64 %123, %extelt.offset6 | |
| %134 = lshr i64 %133, 32 | |
| %135 = trunc i64 %134 to i32 | |
| %136 = mul i32 %118, %122 | |
| %137 = insertelement <2 x i32> undef, i32 %136, i64 0 | |
| %138 = insertelement <2 x i32> %137, i32 %135, i64 1 | |
| %139 = bitcast <2 x i32> %138 to i64 | |
| %140 = add i64 %132, %139 | |
| %141 = lshr i64 %140, 32 | |
| %142 = mul nuw i64 %extelt.offset4, %124 | |
| %143 = lshr i64 %142, 32 | |
| %144 = trunc i64 %143 to i32 | |
| %145 = mul i32 %119, %121 | |
| %146 = insertelement <2 x i32> undef, i32 %145, i64 0 | |
| %147 = insertelement <2 x i32> %146, i32 %144, i64 1 | |
| %148 = bitcast <2 x i32> %147 to i64 | |
| %149 = and i64 %140, 4294967295 | |
| %150 = add i64 %149, %148 | |
| %151 = lshr i64 %150, 32 | |
| %152 = mul nuw i64 %extelt.offset4, %extelt.offset6 | |
| %153 = lshr i64 %152, 32 | |
| %154 = trunc i64 %153 to i32 | |
| %155 = mul i32 %119, %122 | |
| %156 = insertelement <2 x i32> undef, i32 %155, i64 0 | |
| %157 = insertelement <2 x i32> %156, i32 %154, i64 1 | |
| %158 = bitcast <2 x i32> %157 to i64 | |
| %159 = add i64 %141, %158 | |
| %160 = add i64 %159, %151 | |
| %161 = trunc i64 %160 to i32 | |
| %162 = lshr i64 %160, 32 | |
| %163 = trunc i64 %162 to i32 | |
| %164 = insertelement <2 x i32> undef, i32 %161, i64 0 | |
| %165 = insertelement <2 x i32> %164, i32 %163, i64 1 | |
| %166 = bitcast <2 x i32> %165 to i64 | |
| %167 = icmp eq i64 %166, 0 | |
| %168 = add i32 %136, %145 | |
| %169 = add i32 %168, %127 | |
| %170 = insertelement <2 x i32> %129, i32 %169, i64 1 | |
| %171 = bitcast <2 x i32> %170 to i64 | |
| %172 = extractelement <16 x i64> %58, i64 1 | |
| %173 = call i64 @llvm.uadd.sat.i64(i64 %171, i64 %172) #3 | |
| %174 = select i1 %167, i64 %173, i64 -1 | |
| %175 = extractelement <16 x i64> %52, i64 2 | |
| %176 = trunc i64 %175 to i32 | |
| %extelt.offset8 = lshr i64 %175, 32 | |
| %177 = trunc i64 %extelt.offset8 to i32 | |
| %178 = extractelement <16 x i64> %55, i64 2 | |
| %179 = trunc i64 %178 to i32 | |
| %extelt.offset10 = lshr i64 %178, 32 | |
| %180 = trunc i64 %extelt.offset10 to i32 | |
| %181 = and i64 %175, 4294967295 | |
| %182 = and i64 %178, 4294967295 | |
| %183 = mul nuw i64 %181, %182 | |
| %184 = lshr i64 %183, 32 | |
| %185 = trunc i64 %184 to i32 | |
| %186 = mul i32 %176, %179 | |
| %187 = insertelement <2 x i32> undef, i32 %186, i64 0 | |
| %188 = insertelement <2 x i32> %187, i32 %185, i64 1 | |
| %189 = bitcast <2 x i32> %188 to i64 | |
| %190 = lshr i64 %189, 32 | |
| %191 = mul nuw i64 %181, %extelt.offset10 | |
| %192 = lshr i64 %191, 32 | |
| %193 = trunc i64 %192 to i32 | |
| %194 = mul i32 %176, %180 | |
| %195 = insertelement <2 x i32> undef, i32 %194, i64 0 | |
| %196 = insertelement <2 x i32> %195, i32 %193, i64 1 | |
| %197 = bitcast <2 x i32> %196 to i64 | |
| %198 = add i64 %190, %197 | |
| %199 = lshr i64 %198, 32 | |
| %200 = mul nuw i64 %extelt.offset8, %182 | |
| %201 = lshr i64 %200, 32 | |
| %202 = trunc i64 %201 to i32 | |
| %203 = mul i32 %177, %179 | |
| %204 = insertelement <2 x i32> undef, i32 %203, i64 0 | |
| %205 = insertelement <2 x i32> %204, i32 %202, i64 1 | |
| %206 = bitcast <2 x i32> %205 to i64 | |
| %207 = and i64 %198, 4294967295 | |
| %208 = add i64 %207, %206 | |
| %209 = lshr i64 %208, 32 | |
| %210 = mul nuw i64 %extelt.offset8, %extelt.offset10 | |
| %211 = lshr i64 %210, 32 | |
| %212 = trunc i64 %211 to i32 | |
| %213 = mul i32 %177, %180 | |
| %214 = insertelement <2 x i32> undef, i32 %213, i64 0 | |
| %215 = insertelement <2 x i32> %214, i32 %212, i64 1 | |
| %216 = bitcast <2 x i32> %215 to i64 | |
| %217 = add i64 %199, %216 | |
| %218 = add i64 %217, %209 | |
| %219 = trunc i64 %218 to i32 | |
| %220 = lshr i64 %218, 32 | |
| %221 = trunc i64 %220 to i32 | |
| %222 = insertelement <2 x i32> undef, i32 %219, i64 0 | |
| %223 = insertelement <2 x i32> %222, i32 %221, i64 1 | |
| %224 = bitcast <2 x i32> %223 to i64 | |
| %225 = icmp eq i64 %224, 0 | |
| %226 = add i32 %194, %203 | |
| %227 = add i32 %226, %185 | |
| %228 = insertelement <2 x i32> %187, i32 %227, i64 1 | |
| %229 = bitcast <2 x i32> %228 to i64 | |
| %230 = extractelement <16 x i64> %58, i64 2 | |
| %231 = call i64 @llvm.uadd.sat.i64(i64 %229, i64 %230) #3 | |
| %232 = select i1 %225, i64 %231, i64 -1 | |
| %233 = extractelement <16 x i64> %52, i64 3 | |
| %234 = trunc i64 %233 to i32 | |
| %extelt.offset12 = lshr i64 %233, 32 | |
| %235 = trunc i64 %extelt.offset12 to i32 | |
| %236 = extractelement <16 x i64> %55, i64 3 | |
| %237 = trunc i64 %236 to i32 | |
| %extelt.offset14 = lshr i64 %236, 32 | |
| %238 = trunc i64 %extelt.offset14 to i32 | |
| %239 = and i64 %233, 4294967295 | |
| %240 = and i64 %236, 4294967295 | |
| %241 = mul nuw i64 %239, %240 | |
| %242 = lshr i64 %241, 32 | |
| %243 = trunc i64 %242 to i32 | |
| %244 = mul i32 %234, %237 | |
| %245 = insertelement <2 x i32> undef, i32 %244, i64 0 | |
| %246 = insertelement <2 x i32> %245, i32 %243, i64 1 | |
| %247 = bitcast <2 x i32> %246 to i64 | |
| %248 = lshr i64 %247, 32 | |
| %249 = mul nuw i64 %239, %extelt.offset14 | |
| %250 = lshr i64 %249, 32 | |
| %251 = trunc i64 %250 to i32 | |
| %252 = mul i32 %234, %238 | |
| %253 = insertelement <2 x i32> undef, i32 %252, i64 0 | |
| %254 = insertelement <2 x i32> %253, i32 %251, i64 1 | |
| %255 = bitcast <2 x i32> %254 to i64 | |
| %256 = add i64 %248, %255 | |
| %257 = lshr i64 %256, 32 | |
| %258 = mul nuw i64 %extelt.offset12, %240 | |
| %259 = lshr i64 %258, 32 | |
| %260 = trunc i64 %259 to i32 | |
| %261 = mul i32 %235, %237 | |
| %262 = insertelement <2 x i32> undef, i32 %261, i64 0 | |
| %263 = insertelement <2 x i32> %262, i32 %260, i64 1 | |
| %264 = bitcast <2 x i32> %263 to i64 | |
| %265 = and i64 %256, 4294967295 | |
| %266 = add i64 %265, %264 | |
| %267 = lshr i64 %266, 32 | |
| %268 = mul nuw i64 %extelt.offset12, %extelt.offset14 | |
| %269 = lshr i64 %268, 32 | |
| %270 = trunc i64 %269 to i32 | |
| %271 = mul i32 %235, %238 | |
| %272 = insertelement <2 x i32> undef, i32 %271, i64 0 | |
| %273 = insertelement <2 x i32> %272, i32 %270, i64 1 | |
| %274 = bitcast <2 x i32> %273 to i64 | |
| %275 = add i64 %257, %274 | |
| %276 = add i64 %275, %267 | |
| %277 = trunc i64 %276 to i32 | |
| %278 = lshr i64 %276, 32 | |
| %279 = trunc i64 %278 to i32 | |
| %280 = insertelement <2 x i32> undef, i32 %277, i64 0 | |
| %281 = insertelement <2 x i32> %280, i32 %279, i64 1 | |
| %282 = bitcast <2 x i32> %281 to i64 | |
| %283 = icmp eq i64 %282, 0 | |
| %284 = add i32 %252, %261 | |
| %285 = add i32 %284, %243 | |
| %286 = insertelement <2 x i32> %245, i32 %285, i64 1 | |
| %287 = bitcast <2 x i32> %286 to i64 | |
| %288 = extractelement <16 x i64> %58, i64 3 | |
| %289 = call i64 @llvm.uadd.sat.i64(i64 %287, i64 %288) #3 | |
| %290 = select i1 %283, i64 %289, i64 -1 | |
| %291 = extractelement <16 x i64> %52, i64 4 | |
| %292 = trunc i64 %291 to i32 | |
| %extelt.offset16 = lshr i64 %291, 32 | |
| %293 = trunc i64 %extelt.offset16 to i32 | |
| %294 = extractelement <16 x i64> %55, i64 4 | |
| %295 = trunc i64 %294 to i32 | |
| %extelt.offset18 = lshr i64 %294, 32 | |
| %296 = trunc i64 %extelt.offset18 to i32 | |
| %297 = and i64 %291, 4294967295 | |
| %298 = and i64 %294, 4294967295 | |
| %299 = mul nuw i64 %297, %298 | |
| %300 = lshr i64 %299, 32 | |
| %301 = trunc i64 %300 to i32 | |
| %302 = mul i32 %292, %295 | |
| %303 = insertelement <2 x i32> undef, i32 %302, i64 0 | |
| %304 = insertelement <2 x i32> %303, i32 %301, i64 1 | |
| %305 = bitcast <2 x i32> %304 to i64 | |
| %306 = lshr i64 %305, 32 | |
| %307 = mul nuw i64 %297, %extelt.offset18 | |
| %308 = lshr i64 %307, 32 | |
| %309 = trunc i64 %308 to i32 | |
| %310 = mul i32 %292, %296 | |
| %311 = insertelement <2 x i32> undef, i32 %310, i64 0 | |
| %312 = insertelement <2 x i32> %311, i32 %309, i64 1 | |
| %313 = bitcast <2 x i32> %312 to i64 | |
| %314 = add i64 %306, %313 | |
| %315 = lshr i64 %314, 32 | |
| %316 = mul nuw i64 %extelt.offset16, %298 | |
| %317 = lshr i64 %316, 32 | |
| %318 = trunc i64 %317 to i32 | |
| %319 = mul i32 %293, %295 | |
| %320 = insertelement <2 x i32> undef, i32 %319, i64 0 | |
| %321 = insertelement <2 x i32> %320, i32 %318, i64 1 | |
| %322 = bitcast <2 x i32> %321 to i64 | |
| %323 = and i64 %314, 4294967295 | |
| %324 = add i64 %323, %322 | |
| %325 = lshr i64 %324, 32 | |
| %326 = mul nuw i64 %extelt.offset16, %extelt.offset18 | |
| %327 = lshr i64 %326, 32 | |
| %328 = trunc i64 %327 to i32 | |
| %329 = mul i32 %293, %296 | |
| %330 = insertelement <2 x i32> undef, i32 %329, i64 0 | |
| %331 = insertelement <2 x i32> %330, i32 %328, i64 1 | |
| %332 = bitcast <2 x i32> %331 to i64 | |
| %333 = add i64 %315, %332 | |
| %334 = add i64 %333, %325 | |
| %335 = trunc i64 %334 to i32 | |
| %336 = lshr i64 %334, 32 | |
| %337 = trunc i64 %336 to i32 | |
| %338 = insertelement <2 x i32> undef, i32 %335, i64 0 | |
| %339 = insertelement <2 x i32> %338, i32 %337, i64 1 | |
| %340 = bitcast <2 x i32> %339 to i64 | |
| %341 = icmp eq i64 %340, 0 | |
| %342 = add i32 %310, %319 | |
| %343 = add i32 %342, %301 | |
| %344 = insertelement <2 x i32> %303, i32 %343, i64 1 | |
| %345 = bitcast <2 x i32> %344 to i64 | |
| %346 = extractelement <16 x i64> %58, i64 4 | |
| %347 = call i64 @llvm.uadd.sat.i64(i64 %345, i64 %346) #3 | |
| %348 = select i1 %341, i64 %347, i64 -1 | |
| %349 = extractelement <16 x i64> %52, i64 5 | |
| %350 = trunc i64 %349 to i32 | |
| %extelt.offset20 = lshr i64 %349, 32 | |
| %351 = trunc i64 %extelt.offset20 to i32 | |
| %352 = extractelement <16 x i64> %55, i64 5 | |
| %353 = trunc i64 %352 to i32 | |
| %extelt.offset22 = lshr i64 %352, 32 | |
| %354 = trunc i64 %extelt.offset22 to i32 | |
| %355 = and i64 %349, 4294967295 | |
| %356 = and i64 %352, 4294967295 | |
| %357 = mul nuw i64 %355, %356 | |
| %358 = lshr i64 %357, 32 | |
| %359 = trunc i64 %358 to i32 | |
| %360 = mul i32 %350, %353 | |
| %361 = insertelement <2 x i32> undef, i32 %360, i64 0 | |
| %362 = insertelement <2 x i32> %361, i32 %359, i64 1 | |
| %363 = bitcast <2 x i32> %362 to i64 | |
| %364 = lshr i64 %363, 32 | |
| %365 = mul nuw i64 %355, %extelt.offset22 | |
| %366 = lshr i64 %365, 32 | |
| %367 = trunc i64 %366 to i32 | |
| %368 = mul i32 %350, %354 | |
| %369 = insertelement <2 x i32> undef, i32 %368, i64 0 | |
| %370 = insertelement <2 x i32> %369, i32 %367, i64 1 | |
| %371 = bitcast <2 x i32> %370 to i64 | |
| %372 = add i64 %364, %371 | |
| %373 = lshr i64 %372, 32 | |
| %374 = mul nuw i64 %extelt.offset20, %356 | |
| %375 = lshr i64 %374, 32 | |
| %376 = trunc i64 %375 to i32 | |
| %377 = mul i32 %351, %353 | |
| %378 = insertelement <2 x i32> undef, i32 %377, i64 0 | |
| %379 = insertelement <2 x i32> %378, i32 %376, i64 1 | |
| %380 = bitcast <2 x i32> %379 to i64 | |
| %381 = and i64 %372, 4294967295 | |
| %382 = add i64 %381, %380 | |
| %383 = lshr i64 %382, 32 | |
| %384 = mul nuw i64 %extelt.offset20, %extelt.offset22 | |
| %385 = lshr i64 %384, 32 | |
| %386 = trunc i64 %385 to i32 | |
| %387 = mul i32 %351, %354 | |
| %388 = insertelement <2 x i32> undef, i32 %387, i64 0 | |
| %389 = insertelement <2 x i32> %388, i32 %386, i64 1 | |
| %390 = bitcast <2 x i32> %389 to i64 | |
| %391 = add i64 %373, %390 | |
| %392 = add i64 %391, %383 | |
| %393 = trunc i64 %392 to i32 | |
| %394 = lshr i64 %392, 32 | |
| %395 = trunc i64 %394 to i32 | |
| %396 = insertelement <2 x i32> undef, i32 %393, i64 0 | |
| %397 = insertelement <2 x i32> %396, i32 %395, i64 1 | |
| %398 = bitcast <2 x i32> %397 to i64 | |
| %399 = icmp eq i64 %398, 0 | |
| %400 = add i32 %368, %377 | |
| %401 = add i32 %400, %359 | |
| %402 = insertelement <2 x i32> %361, i32 %401, i64 1 | |
| %403 = bitcast <2 x i32> %402 to i64 | |
| %404 = extractelement <16 x i64> %58, i64 5 | |
| %405 = call i64 @llvm.uadd.sat.i64(i64 %403, i64 %404) #3 | |
| %406 = select i1 %399, i64 %405, i64 -1 | |
| %407 = extractelement <16 x i64> %52, i64 6 | |
| %408 = trunc i64 %407 to i32 | |
| %extelt.offset24 = lshr i64 %407, 32 | |
| %409 = trunc i64 %extelt.offset24 to i32 | |
| %410 = extractelement <16 x i64> %55, i64 6 | |
| %411 = trunc i64 %410 to i32 | |
| %extelt.offset26 = lshr i64 %410, 32 | |
| %412 = trunc i64 %extelt.offset26 to i32 | |
| %413 = and i64 %407, 4294967295 | |
| %414 = and i64 %410, 4294967295 | |
| %415 = mul nuw i64 %413, %414 | |
| %416 = lshr i64 %415, 32 | |
| %417 = trunc i64 %416 to i32 | |
| %418 = mul i32 %408, %411 | |
| %419 = insertelement <2 x i32> undef, i32 %418, i64 0 | |
| %420 = insertelement <2 x i32> %419, i32 %417, i64 1 | |
| %421 = bitcast <2 x i32> %420 to i64 | |
| %422 = lshr i64 %421, 32 | |
| %423 = mul nuw i64 %413, %extelt.offset26 | |
| %424 = lshr i64 %423, 32 | |
| %425 = trunc i64 %424 to i32 | |
| %426 = mul i32 %408, %412 | |
| %427 = insertelement <2 x i32> undef, i32 %426, i64 0 | |
| %428 = insertelement <2 x i32> %427, i32 %425, i64 1 | |
| %429 = bitcast <2 x i32> %428 to i64 | |
| %430 = add i64 %422, %429 | |
| %431 = lshr i64 %430, 32 | |
| %432 = mul nuw i64 %extelt.offset24, %414 | |
| %433 = lshr i64 %432, 32 | |
| %434 = trunc i64 %433 to i32 | |
| %435 = mul i32 %409, %411 | |
| %436 = insertelement <2 x i32> undef, i32 %435, i64 0 | |
| %437 = insertelement <2 x i32> %436, i32 %434, i64 1 | |
| %438 = bitcast <2 x i32> %437 to i64 | |
| %439 = and i64 %430, 4294967295 | |
| %440 = add i64 %439, %438 | |
| %441 = lshr i64 %440, 32 | |
| %442 = mul nuw i64 %extelt.offset24, %extelt.offset26 | |
| %443 = lshr i64 %442, 32 | |
| %444 = trunc i64 %443 to i32 | |
| %445 = mul i32 %409, %412 | |
| %446 = insertelement <2 x i32> undef, i32 %445, i64 0 | |
| %447 = insertelement <2 x i32> %446, i32 %444, i64 1 | |
| %448 = bitcast <2 x i32> %447 to i64 | |
| %449 = add i64 %431, %448 | |
| %450 = add i64 %449, %441 | |
| %451 = trunc i64 %450 to i32 | |
| %452 = lshr i64 %450, 32 | |
| %453 = trunc i64 %452 to i32 | |
| %454 = insertelement <2 x i32> undef, i32 %451, i64 0 | |
| %455 = insertelement <2 x i32> %454, i32 %453, i64 1 | |
| %456 = bitcast <2 x i32> %455 to i64 | |
| %457 = icmp eq i64 %456, 0 | |
| %458 = add i32 %426, %435 | |
| %459 = add i32 %458, %417 | |
| %460 = insertelement <2 x i32> %419, i32 %459, i64 1 | |
| %461 = bitcast <2 x i32> %460 to i64 | |
| %462 = extractelement <16 x i64> %58, i64 6 | |
| %463 = call i64 @llvm.uadd.sat.i64(i64 %461, i64 %462) #3 | |
| %464 = select i1 %457, i64 %463, i64 -1 | |
| %465 = extractelement <16 x i64> %52, i64 7 | |
| %466 = trunc i64 %465 to i32 | |
| %extelt.offset28 = lshr i64 %465, 32 | |
| %467 = trunc i64 %extelt.offset28 to i32 | |
| %468 = extractelement <16 x i64> %55, i64 7 | |
| %469 = trunc i64 %468 to i32 | |
| %extelt.offset30 = lshr i64 %468, 32 | |
| %470 = trunc i64 %extelt.offset30 to i32 | |
| %471 = and i64 %465, 4294967295 | |
| %472 = and i64 %468, 4294967295 | |
| %473 = mul nuw i64 %471, %472 | |
| %474 = lshr i64 %473, 32 | |
| %475 = trunc i64 %474 to i32 | |
| %476 = mul i32 %466, %469 | |
| %477 = insertelement <2 x i32> undef, i32 %476, i64 0 | |
| %478 = insertelement <2 x i32> %477, i32 %475, i64 1 | |
| %479 = bitcast <2 x i32> %478 to i64 | |
| %480 = lshr i64 %479, 32 | |
| %481 = mul nuw i64 %471, %extelt.offset30 | |
| %482 = lshr i64 %481, 32 | |
| %483 = trunc i64 %482 to i32 | |
| %484 = mul i32 %466, %470 | |
| %485 = insertelement <2 x i32> undef, i32 %484, i64 0 | |
| %486 = insertelement <2 x i32> %485, i32 %483, i64 1 | |
| %487 = bitcast <2 x i32> %486 to i64 | |
| %488 = add i64 %480, %487 | |
| %489 = lshr i64 %488, 32 | |
| %490 = mul nuw i64 %extelt.offset28, %472 | |
| %491 = lshr i64 %490, 32 | |
| %492 = trunc i64 %491 to i32 | |
| %493 = mul i32 %467, %469 | |
| %494 = insertelement <2 x i32> undef, i32 %493, i64 0 | |
| %495 = insertelement <2 x i32> %494, i32 %492, i64 1 | |
| %496 = bitcast <2 x i32> %495 to i64 | |
| %497 = and i64 %488, 4294967295 | |
| %498 = add i64 %497, %496 | |
| %499 = lshr i64 %498, 32 | |
| %500 = mul nuw i64 %extelt.offset28, %extelt.offset30 | |
| %501 = lshr i64 %500, 32 | |
| %502 = trunc i64 %501 to i32 | |
| %503 = mul i32 %467, %470 | |
| %504 = insertelement <2 x i32> undef, i32 %503, i64 0 | |
| %505 = insertelement <2 x i32> %504, i32 %502, i64 1 | |
| %506 = bitcast <2 x i32> %505 to i64 | |
| %507 = add i64 %489, %506 | |
| %508 = add i64 %507, %499 | |
| %509 = trunc i64 %508 to i32 | |
| %510 = lshr i64 %508, 32 | |
| %511 = trunc i64 %510 to i32 | |
| %512 = insertelement <2 x i32> undef, i32 %509, i64 0 | |
| %513 = insertelement <2 x i32> %512, i32 %511, i64 1 | |
| %514 = bitcast <2 x i32> %513 to i64 | |
| %515 = icmp eq i64 %514, 0 | |
| %516 = add i32 %484, %493 | |
| %517 = add i32 %516, %475 | |
| %518 = insertelement <2 x i32> %477, i32 %517, i64 1 | |
| %519 = bitcast <2 x i32> %518 to i64 | |
| %520 = extractelement <16 x i64> %58, i64 7 | |
| %521 = call i64 @llvm.uadd.sat.i64(i64 %519, i64 %520) #3 | |
| %522 = select i1 %515, i64 %521, i64 -1 | |
| %523 = extractelement <16 x i64> %52, i64 8 | |
| %524 = trunc i64 %523 to i32 | |
| %extelt.offset32 = lshr i64 %523, 32 | |
| %525 = trunc i64 %extelt.offset32 to i32 | |
| %526 = extractelement <16 x i64> %55, i64 8 | |
| %527 = trunc i64 %526 to i32 | |
| %extelt.offset34 = lshr i64 %526, 32 | |
| %528 = trunc i64 %extelt.offset34 to i32 | |
| %529 = and i64 %523, 4294967295 | |
| %530 = and i64 %526, 4294967295 | |
| %531 = mul nuw i64 %529, %530 | |
| %532 = lshr i64 %531, 32 | |
| %533 = trunc i64 %532 to i32 | |
| %534 = mul i32 %524, %527 | |
| %535 = insertelement <2 x i32> undef, i32 %534, i64 0 | |
| %536 = insertelement <2 x i32> %535, i32 %533, i64 1 | |
| %537 = bitcast <2 x i32> %536 to i64 | |
| %538 = lshr i64 %537, 32 | |
| %539 = mul nuw i64 %529, %extelt.offset34 | |
| %540 = lshr i64 %539, 32 | |
| %541 = trunc i64 %540 to i32 | |
| %542 = mul i32 %524, %528 | |
| %543 = insertelement <2 x i32> undef, i32 %542, i64 0 | |
| %544 = insertelement <2 x i32> %543, i32 %541, i64 1 | |
| %545 = bitcast <2 x i32> %544 to i64 | |
| %546 = add i64 %538, %545 | |
| %547 = lshr i64 %546, 32 | |
| %548 = mul nuw i64 %extelt.offset32, %530 | |
| %549 = lshr i64 %548, 32 | |
| %550 = trunc i64 %549 to i32 | |
| %551 = mul i32 %525, %527 | |
| %552 = insertelement <2 x i32> undef, i32 %551, i64 0 | |
| %553 = insertelement <2 x i32> %552, i32 %550, i64 1 | |
| %554 = bitcast <2 x i32> %553 to i64 | |
| %555 = and i64 %546, 4294967295 | |
| %556 = add i64 %555, %554 | |
| %557 = lshr i64 %556, 32 | |
| %558 = mul nuw i64 %extelt.offset32, %extelt.offset34 | |
| %559 = lshr i64 %558, 32 | |
| %560 = trunc i64 %559 to i32 | |
| %561 = mul i32 %525, %528 | |
| %562 = insertelement <2 x i32> undef, i32 %561, i64 0 | |
| %563 = insertelement <2 x i32> %562, i32 %560, i64 1 | |
| %564 = bitcast <2 x i32> %563 to i64 | |
| %565 = add i64 %547, %564 | |
| %566 = add i64 %565, %557 | |
| %567 = trunc i64 %566 to i32 | |
| %568 = lshr i64 %566, 32 | |
| %569 = trunc i64 %568 to i32 | |
| %570 = insertelement <2 x i32> undef, i32 %567, i64 0 | |
| %571 = insertelement <2 x i32> %570, i32 %569, i64 1 | |
| %572 = bitcast <2 x i32> %571 to i64 | |
| %573 = icmp eq i64 %572, 0 | |
| %574 = add i32 %542, %551 | |
| %575 = add i32 %574, %533 | |
| %576 = insertelement <2 x i32> %535, i32 %575, i64 1 | |
| %577 = bitcast <2 x i32> %576 to i64 | |
| %578 = extractelement <16 x i64> %58, i64 8 | |
| %579 = call i64 @llvm.uadd.sat.i64(i64 %577, i64 %578) #3 | |
| %580 = select i1 %573, i64 %579, i64 -1 | |
| %581 = extractelement <16 x i64> %52, i64 9 | |
| %582 = trunc i64 %581 to i32 | |
| %extelt.offset36 = lshr i64 %581, 32 | |
| %583 = trunc i64 %extelt.offset36 to i32 | |
| %584 = extractelement <16 x i64> %55, i64 9 | |
| %585 = trunc i64 %584 to i32 | |
| %extelt.offset38 = lshr i64 %584, 32 | |
| %586 = trunc i64 %extelt.offset38 to i32 | |
| %587 = and i64 %581, 4294967295 | |
| %588 = and i64 %584, 4294967295 | |
| %589 = mul nuw i64 %587, %588 | |
| %590 = lshr i64 %589, 32 | |
| %591 = trunc i64 %590 to i32 | |
| %592 = mul i32 %582, %585 | |
| %593 = insertelement <2 x i32> undef, i32 %592, i64 0 | |
| %594 = insertelement <2 x i32> %593, i32 %591, i64 1 | |
| %595 = bitcast <2 x i32> %594 to i64 | |
| %596 = lshr i64 %595, 32 | |
| %597 = mul nuw i64 %587, %extelt.offset38 | |
| %598 = lshr i64 %597, 32 | |
| %599 = trunc i64 %598 to i32 | |
| %600 = mul i32 %582, %586 | |
| %601 = insertelement <2 x i32> undef, i32 %600, i64 0 | |
| %602 = insertelement <2 x i32> %601, i32 %599, i64 1 | |
| %603 = bitcast <2 x i32> %602 to i64 | |
| %604 = add i64 %596, %603 | |
| %605 = lshr i64 %604, 32 | |
| %606 = mul nuw i64 %extelt.offset36, %588 | |
| %607 = lshr i64 %606, 32 | |
| %608 = trunc i64 %607 to i32 | |
| %609 = mul i32 %583, %585 | |
| %610 = insertelement <2 x i32> undef, i32 %609, i64 0 | |
| %611 = insertelement <2 x i32> %610, i32 %608, i64 1 | |
| %612 = bitcast <2 x i32> %611 to i64 | |
| %613 = and i64 %604, 4294967295 | |
| %614 = add i64 %613, %612 | |
| %615 = lshr i64 %614, 32 | |
| %616 = mul nuw i64 %extelt.offset36, %extelt.offset38 | |
| %617 = lshr i64 %616, 32 | |
| %618 = trunc i64 %617 to i32 | |
| %619 = mul i32 %583, %586 | |
| %620 = insertelement <2 x i32> undef, i32 %619, i64 0 | |
| %621 = insertelement <2 x i32> %620, i32 %618, i64 1 | |
| %622 = bitcast <2 x i32> %621 to i64 | |
| %623 = add i64 %605, %622 | |
| %624 = add i64 %623, %615 | |
| %625 = trunc i64 %624 to i32 | |
| %626 = lshr i64 %624, 32 | |
| %627 = trunc i64 %626 to i32 | |
| %628 = insertelement <2 x i32> undef, i32 %625, i64 0 | |
| %629 = insertelement <2 x i32> %628, i32 %627, i64 1 | |
| %630 = bitcast <2 x i32> %629 to i64 | |
| %631 = icmp eq i64 %630, 0 | |
| %632 = add i32 %600, %609 | |
| %633 = add i32 %632, %591 | |
| %634 = insertelement <2 x i32> %593, i32 %633, i64 1 | |
| %635 = bitcast <2 x i32> %634 to i64 | |
| %636 = extractelement <16 x i64> %58, i64 9 | |
| %637 = call i64 @llvm.uadd.sat.i64(i64 %635, i64 %636) #3 | |
| %638 = select i1 %631, i64 %637, i64 -1 | |
| %639 = extractelement <16 x i64> %52, i64 10 | |
| %640 = trunc i64 %639 to i32 | |
| %extelt.offset40 = lshr i64 %639, 32 | |
| %641 = trunc i64 %extelt.offset40 to i32 | |
| %642 = extractelement <16 x i64> %55, i64 10 | |
| %643 = trunc i64 %642 to i32 | |
| %extelt.offset42 = lshr i64 %642, 32 | |
| %644 = trunc i64 %extelt.offset42 to i32 | |
| %645 = and i64 %639, 4294967295 | |
| %646 = and i64 %642, 4294967295 | |
| %647 = mul nuw i64 %645, %646 | |
| %648 = lshr i64 %647, 32 | |
| %649 = trunc i64 %648 to i32 | |
| %650 = mul i32 %640, %643 | |
| %651 = insertelement <2 x i32> undef, i32 %650, i64 0 | |
| %652 = insertelement <2 x i32> %651, i32 %649, i64 1 | |
| %653 = bitcast <2 x i32> %652 to i64 | |
| %654 = lshr i64 %653, 32 | |
| %655 = mul nuw i64 %645, %extelt.offset42 | |
| %656 = lshr i64 %655, 32 | |
| %657 = trunc i64 %656 to i32 | |
| %658 = mul i32 %640, %644 | |
| %659 = insertelement <2 x i32> undef, i32 %658, i64 0 | |
| %660 = insertelement <2 x i32> %659, i32 %657, i64 1 | |
| %661 = bitcast <2 x i32> %660 to i64 | |
| %662 = add i64 %654, %661 | |
| %663 = lshr i64 %662, 32 | |
| %664 = mul nuw i64 %extelt.offset40, %646 | |
| %665 = lshr i64 %664, 32 | |
| %666 = trunc i64 %665 to i32 | |
| %667 = mul i32 %641, %643 | |
| %668 = insertelement <2 x i32> undef, i32 %667, i64 0 | |
| %669 = insertelement <2 x i32> %668, i32 %666, i64 1 | |
| %670 = bitcast <2 x i32> %669 to i64 | |
| %671 = and i64 %662, 4294967295 | |
| %672 = add i64 %671, %670 | |
| %673 = lshr i64 %672, 32 | |
| %674 = mul nuw i64 %extelt.offset40, %extelt.offset42 | |
| %675 = lshr i64 %674, 32 | |
| %676 = trunc i64 %675 to i32 | |
| %677 = mul i32 %641, %644 | |
| %678 = insertelement <2 x i32> undef, i32 %677, i64 0 | |
| %679 = insertelement <2 x i32> %678, i32 %676, i64 1 | |
| %680 = bitcast <2 x i32> %679 to i64 | |
| %681 = add i64 %663, %680 | |
| %682 = add i64 %681, %673 | |
| %683 = trunc i64 %682 to i32 | |
| %684 = lshr i64 %682, 32 | |
| %685 = trunc i64 %684 to i32 | |
| %686 = insertelement <2 x i32> undef, i32 %683, i64 0 | |
| %687 = insertelement <2 x i32> %686, i32 %685, i64 1 | |
| %688 = bitcast <2 x i32> %687 to i64 | |
| %689 = icmp eq i64 %688, 0 | |
| %690 = add i32 %658, %667 | |
| %691 = add i32 %690, %649 | |
| %692 = insertelement <2 x i32> %651, i32 %691, i64 1 | |
| %693 = bitcast <2 x i32> %692 to i64 | |
| %694 = extractelement <16 x i64> %58, i64 10 | |
| %695 = call i64 @llvm.uadd.sat.i64(i64 %693, i64 %694) #3 | |
| %696 = select i1 %689, i64 %695, i64 -1 | |
| %697 = extractelement <16 x i64> %52, i64 11 | |
| %698 = trunc i64 %697 to i32 | |
| %extelt.offset44 = lshr i64 %697, 32 | |
| %699 = trunc i64 %extelt.offset44 to i32 | |
| %700 = extractelement <16 x i64> %55, i64 11 | |
| %701 = trunc i64 %700 to i32 | |
| %extelt.offset46 = lshr i64 %700, 32 | |
| %702 = trunc i64 %extelt.offset46 to i32 | |
| %703 = and i64 %697, 4294967295 | |
| %704 = and i64 %700, 4294967295 | |
| %705 = mul nuw i64 %703, %704 | |
| %706 = lshr i64 %705, 32 | |
| %707 = trunc i64 %706 to i32 | |
| %708 = mul i32 %698, %701 | |
| %709 = insertelement <2 x i32> undef, i32 %708, i64 0 | |
| %710 = insertelement <2 x i32> %709, i32 %707, i64 1 | |
| %711 = bitcast <2 x i32> %710 to i64 | |
| %712 = lshr i64 %711, 32 | |
| %713 = mul nuw i64 %703, %extelt.offset46 | |
| %714 = lshr i64 %713, 32 | |
| %715 = trunc i64 %714 to i32 | |
| %716 = mul i32 %698, %702 | |
| %717 = insertelement <2 x i32> undef, i32 %716, i64 0 | |
| %718 = insertelement <2 x i32> %717, i32 %715, i64 1 | |
| %719 = bitcast <2 x i32> %718 to i64 | |
| %720 = add i64 %712, %719 | |
| %721 = lshr i64 %720, 32 | |
| %722 = mul nuw i64 %extelt.offset44, %704 | |
| %723 = lshr i64 %722, 32 | |
| %724 = trunc i64 %723 to i32 | |
| %725 = mul i32 %699, %701 | |
| %726 = insertelement <2 x i32> undef, i32 %725, i64 0 | |
| %727 = insertelement <2 x i32> %726, i32 %724, i64 1 | |
| %728 = bitcast <2 x i32> %727 to i64 | |
| %729 = and i64 %720, 4294967295 | |
| %730 = add i64 %729, %728 | |
| %731 = lshr i64 %730, 32 | |
| %732 = mul nuw i64 %extelt.offset44, %extelt.offset46 | |
| %733 = lshr i64 %732, 32 | |
| %734 = trunc i64 %733 to i32 | |
| %735 = mul i32 %699, %702 | |
| %736 = insertelement <2 x i32> undef, i32 %735, i64 0 | |
| %737 = insertelement <2 x i32> %736, i32 %734, i64 1 | |
| %738 = bitcast <2 x i32> %737 to i64 | |
| %739 = add i64 %721, %738 | |
| %740 = add i64 %739, %731 | |
| %741 = trunc i64 %740 to i32 | |
| %742 = lshr i64 %740, 32 | |
| %743 = trunc i64 %742 to i32 | |
| %744 = insertelement <2 x i32> undef, i32 %741, i64 0 | |
| %745 = insertelement <2 x i32> %744, i32 %743, i64 1 | |
| %746 = bitcast <2 x i32> %745 to i64 | |
| %747 = icmp eq i64 %746, 0 | |
| %748 = add i32 %716, %725 | |
| %749 = add i32 %748, %707 | |
| %750 = insertelement <2 x i32> %709, i32 %749, i64 1 | |
| %751 = bitcast <2 x i32> %750 to i64 | |
| %752 = extractelement <16 x i64> %58, i64 11 | |
| %753 = call i64 @llvm.uadd.sat.i64(i64 %751, i64 %752) #3 | |
| %754 = select i1 %747, i64 %753, i64 -1 | |
| %755 = extractelement <16 x i64> %52, i64 12 | |
| %756 = trunc i64 %755 to i32 | |
| %extelt.offset48 = lshr i64 %755, 32 | |
| %757 = trunc i64 %extelt.offset48 to i32 | |
| %758 = extractelement <16 x i64> %55, i64 12 | |
| %759 = trunc i64 %758 to i32 | |
| %extelt.offset50 = lshr i64 %758, 32 | |
| %760 = trunc i64 %extelt.offset50 to i32 | |
| %761 = and i64 %755, 4294967295 | |
| %762 = and i64 %758, 4294967295 | |
| %763 = mul nuw i64 %761, %762 | |
| %764 = lshr i64 %763, 32 | |
| %765 = trunc i64 %764 to i32 | |
| %766 = mul i32 %756, %759 | |
| %767 = insertelement <2 x i32> undef, i32 %766, i64 0 | |
| %768 = insertelement <2 x i32> %767, i32 %765, i64 1 | |
| %769 = bitcast <2 x i32> %768 to i64 | |
| %770 = lshr i64 %769, 32 | |
| %771 = mul nuw i64 %761, %extelt.offset50 | |
| %772 = lshr i64 %771, 32 | |
| %773 = trunc i64 %772 to i32 | |
| %774 = mul i32 %756, %760 | |
| %775 = insertelement <2 x i32> undef, i32 %774, i64 0 | |
| %776 = insertelement <2 x i32> %775, i32 %773, i64 1 | |
| %777 = bitcast <2 x i32> %776 to i64 | |
| %778 = add i64 %770, %777 | |
| %779 = lshr i64 %778, 32 | |
| %780 = mul nuw i64 %extelt.offset48, %762 | |
| %781 = lshr i64 %780, 32 | |
| %782 = trunc i64 %781 to i32 | |
| %783 = mul i32 %757, %759 | |
| %784 = insertelement <2 x i32> undef, i32 %783, i64 0 | |
| %785 = insertelement <2 x i32> %784, i32 %782, i64 1 | |
| %786 = bitcast <2 x i32> %785 to i64 | |
| %787 = and i64 %778, 4294967295 | |
| %788 = add i64 %787, %786 | |
| %789 = lshr i64 %788, 32 | |
| %790 = mul nuw i64 %extelt.offset48, %extelt.offset50 | |
| %791 = lshr i64 %790, 32 | |
| %792 = trunc i64 %791 to i32 | |
| %793 = mul i32 %757, %760 | |
| %794 = insertelement <2 x i32> undef, i32 %793, i64 0 | |
| %795 = insertelement <2 x i32> %794, i32 %792, i64 1 | |
| %796 = bitcast <2 x i32> %795 to i64 | |
| %797 = add i64 %779, %796 | |
| %798 = add i64 %797, %789 | |
| %799 = trunc i64 %798 to i32 | |
| %800 = lshr i64 %798, 32 | |
| %801 = trunc i64 %800 to i32 | |
| %802 = insertelement <2 x i32> undef, i32 %799, i64 0 | |
| %803 = insertelement <2 x i32> %802, i32 %801, i64 1 | |
| %804 = bitcast <2 x i32> %803 to i64 | |
| %805 = icmp eq i64 %804, 0 | |
| %806 = add i32 %774, %783 | |
| %807 = add i32 %806, %765 | |
| %808 = insertelement <2 x i32> %767, i32 %807, i64 1 | |
| %809 = bitcast <2 x i32> %808 to i64 | |
| %810 = extractelement <16 x i64> %58, i64 12 | |
| %811 = call i64 @llvm.uadd.sat.i64(i64 %809, i64 %810) #3 | |
| %812 = select i1 %805, i64 %811, i64 -1 | |
| %813 = extractelement <16 x i64> %52, i64 13 | |
| %814 = trunc i64 %813 to i32 | |
| %extelt.offset52 = lshr i64 %813, 32 | |
| %815 = trunc i64 %extelt.offset52 to i32 | |
| %816 = extractelement <16 x i64> %55, i64 13 | |
| %817 = trunc i64 %816 to i32 | |
| %extelt.offset54 = lshr i64 %816, 32 | |
| %818 = trunc i64 %extelt.offset54 to i32 | |
| %819 = and i64 %813, 4294967295 | |
| %820 = and i64 %816, 4294967295 | |
| %821 = mul nuw i64 %819, %820 | |
| %822 = lshr i64 %821, 32 | |
| %823 = trunc i64 %822 to i32 | |
| %824 = mul i32 %814, %817 | |
| %825 = insertelement <2 x i32> undef, i32 %824, i64 0 | |
| %826 = insertelement <2 x i32> %825, i32 %823, i64 1 | |
| %827 = bitcast <2 x i32> %826 to i64 | |
| %828 = lshr i64 %827, 32 | |
| %829 = mul nuw i64 %819, %extelt.offset54 | |
| %830 = lshr i64 %829, 32 | |
| %831 = trunc i64 %830 to i32 | |
| %832 = mul i32 %814, %818 | |
| %833 = insertelement <2 x i32> undef, i32 %832, i64 0 | |
| %834 = insertelement <2 x i32> %833, i32 %831, i64 1 | |
| %835 = bitcast <2 x i32> %834 to i64 | |
| %836 = add i64 %828, %835 | |
| %837 = lshr i64 %836, 32 | |
| %838 = mul nuw i64 %extelt.offset52, %820 | |
| %839 = lshr i64 %838, 32 | |
| %840 = trunc i64 %839 to i32 | |
| %841 = mul i32 %815, %817 | |
| %842 = insertelement <2 x i32> undef, i32 %841, i64 0 | |
| %843 = insertelement <2 x i32> %842, i32 %840, i64 1 | |
| %844 = bitcast <2 x i32> %843 to i64 | |
| %845 = and i64 %836, 4294967295 | |
| %846 = add i64 %845, %844 | |
| %847 = lshr i64 %846, 32 | |
| %848 = mul nuw i64 %extelt.offset52, %extelt.offset54 | |
| %849 = lshr i64 %848, 32 | |
| %850 = trunc i64 %849 to i32 | |
| %851 = mul i32 %815, %818 | |
| %852 = insertelement <2 x i32> undef, i32 %851, i64 0 | |
| %853 = insertelement <2 x i32> %852, i32 %850, i64 1 | |
| %854 = bitcast <2 x i32> %853 to i64 | |
| %855 = add i64 %837, %854 | |
| %856 = add i64 %855, %847 | |
| %857 = trunc i64 %856 to i32 | |
| %858 = lshr i64 %856, 32 | |
| %859 = trunc i64 %858 to i32 | |
| %860 = insertelement <2 x i32> undef, i32 %857, i64 0 | |
| %861 = insertelement <2 x i32> %860, i32 %859, i64 1 | |
| %862 = bitcast <2 x i32> %861 to i64 | |
| %863 = icmp eq i64 %862, 0 | |
| %864 = add i32 %832, %841 | |
| %865 = add i32 %864, %823 | |
| %866 = insertelement <2 x i32> %825, i32 %865, i64 1 | |
| %867 = bitcast <2 x i32> %866 to i64 | |
| %868 = extractelement <16 x i64> %58, i64 13 | |
| %869 = call i64 @llvm.uadd.sat.i64(i64 %867, i64 %868) #3 | |
| %870 = select i1 %863, i64 %869, i64 -1 | |
| %871 = extractelement <16 x i64> %52, i64 14 | |
| %872 = trunc i64 %871 to i32 | |
| %extelt.offset56 = lshr i64 %871, 32 | |
| %873 = trunc i64 %extelt.offset56 to i32 | |
| %874 = extractelement <16 x i64> %55, i64 14 | |
| %875 = trunc i64 %874 to i32 | |
| %extelt.offset58 = lshr i64 %874, 32 | |
| %876 = trunc i64 %extelt.offset58 to i32 | |
| %877 = and i64 %871, 4294967295 | |
| %878 = and i64 %874, 4294967295 | |
| %879 = mul nuw i64 %877, %878 | |
| %880 = lshr i64 %879, 32 | |
| %881 = trunc i64 %880 to i32 | |
| %882 = mul i32 %872, %875 | |
| %883 = insertelement <2 x i32> undef, i32 %882, i64 0 | |
| %884 = insertelement <2 x i32> %883, i32 %881, i64 1 | |
| %885 = bitcast <2 x i32> %884 to i64 | |
| %886 = lshr i64 %885, 32 | |
| %887 = mul nuw i64 %877, %extelt.offset58 | |
| %888 = lshr i64 %887, 32 | |
| %889 = trunc i64 %888 to i32 | |
| %890 = mul i32 %872, %876 | |
| %891 = insertelement <2 x i32> undef, i32 %890, i64 0 | |
| %892 = insertelement <2 x i32> %891, i32 %889, i64 1 | |
| %893 = bitcast <2 x i32> %892 to i64 | |
| %894 = add i64 %886, %893 | |
| %895 = lshr i64 %894, 32 | |
| %896 = mul nuw i64 %extelt.offset56, %878 | |
| %897 = lshr i64 %896, 32 | |
| %898 = trunc i64 %897 to i32 | |
| %899 = mul i32 %873, %875 | |
| %900 = insertelement <2 x i32> undef, i32 %899, i64 0 | |
| %901 = insertelement <2 x i32> %900, i32 %898, i64 1 | |
| %902 = bitcast <2 x i32> %901 to i64 | |
| %903 = and i64 %894, 4294967295 | |
| %904 = add i64 %903, %902 | |
| %905 = lshr i64 %904, 32 | |
| %906 = mul nuw i64 %extelt.offset56, %extelt.offset58 | |
| %907 = lshr i64 %906, 32 | |
| %908 = trunc i64 %907 to i32 | |
| %909 = mul i32 %873, %876 | |
| %910 = insertelement <2 x i32> undef, i32 %909, i64 0 | |
| %911 = insertelement <2 x i32> %910, i32 %908, i64 1 | |
| %912 = bitcast <2 x i32> %911 to i64 | |
| %913 = add i64 %895, %912 | |
| %914 = add i64 %913, %905 | |
| %915 = trunc i64 %914 to i32 | |
| %916 = lshr i64 %914, 32 | |
| %917 = trunc i64 %916 to i32 | |
| %918 = insertelement <2 x i32> undef, i32 %915, i64 0 | |
| %919 = insertelement <2 x i32> %918, i32 %917, i64 1 | |
| %920 = bitcast <2 x i32> %919 to i64 | |
| %921 = icmp eq i64 %920, 0 | |
| %922 = add i32 %890, %899 | |
| %923 = add i32 %922, %881 | |
| %924 = insertelement <2 x i32> %883, i32 %923, i64 1 | |
| %925 = bitcast <2 x i32> %924 to i64 | |
| %926 = extractelement <16 x i64> %58, i64 14 | |
| %927 = call i64 @llvm.uadd.sat.i64(i64 %925, i64 %926) #3 | |
| %928 = select i1 %921, i64 %927, i64 -1 | |
| %929 = extractelement <16 x i64> %52, i64 15 | |
| %930 = trunc i64 %929 to i32 | |
| %extelt.offset60 = lshr i64 %929, 32 | |
| %931 = trunc i64 %extelt.offset60 to i32 | |
| %932 = extractelement <16 x i64> %55, i64 15 | |
| %933 = trunc i64 %932 to i32 | |
| %extelt.offset62 = lshr i64 %932, 32 | |
| %934 = trunc i64 %extelt.offset62 to i32 | |
| %935 = and i64 %929, 4294967295 | |
| %936 = and i64 %932, 4294967295 | |
| %937 = mul nuw i64 %935, %936 | |
| %938 = lshr i64 %937, 32 | |
| %939 = trunc i64 %938 to i32 | |
| %940 = mul i32 %930, %933 | |
| %941 = insertelement <2 x i32> undef, i32 %940, i64 0 | |
| %942 = insertelement <2 x i32> %941, i32 %939, i64 1 | |
| %943 = bitcast <2 x i32> %942 to i64 | |
| %944 = lshr i64 %943, 32 | |
| %945 = mul nuw i64 %935, %extelt.offset62 | |
| %946 = lshr i64 %945, 32 | |
| %947 = trunc i64 %946 to i32 | |
| %948 = mul i32 %930, %934 | |
| %949 = insertelement <2 x i32> undef, i32 %948, i64 0 | |
| %950 = insertelement <2 x i32> %949, i32 %947, i64 1 | |
| %951 = bitcast <2 x i32> %950 to i64 | |
| %952 = add i64 %944, %951 | |
| %953 = lshr i64 %952, 32 | |
| %954 = mul nuw i64 %extelt.offset60, %936 | |
| %955 = lshr i64 %954, 32 | |
| %956 = trunc i64 %955 to i32 | |
| %957 = mul i32 %931, %933 | |
| %958 = insertelement <2 x i32> undef, i32 %957, i64 0 | |
| %959 = insertelement <2 x i32> %958, i32 %956, i64 1 | |
| %960 = bitcast <2 x i32> %959 to i64 | |
| %961 = and i64 %952, 4294967295 | |
| %962 = add i64 %961, %960 | |
| %963 = lshr i64 %962, 32 | |
| %964 = mul nuw i64 %extelt.offset60, %extelt.offset62 | |
| %965 = lshr i64 %964, 32 | |
| %966 = trunc i64 %965 to i32 | |
| %967 = mul i32 %931, %934 | |
| %968 = insertelement <2 x i32> undef, i32 %967, i64 0 | |
| %969 = insertelement <2 x i32> %968, i32 %966, i64 1 | |
| %970 = bitcast <2 x i32> %969 to i64 | |
| %971 = add i64 %953, %970 | |
| %972 = add i64 %971, %963 | |
| %973 = trunc i64 %972 to i32 | |
| %974 = lshr i64 %972, 32 | |
| %975 = trunc i64 %974 to i32 | |
| %976 = insertelement <2 x i32> undef, i32 %973, i64 0 | |
| %977 = insertelement <2 x i32> %976, i32 %975, i64 1 | |
| %978 = bitcast <2 x i32> %977 to i64 | |
| %979 = icmp eq i64 %978, 0 | |
| %980 = add i32 %948, %957 | |
| %981 = add i32 %980, %939 | |
| %982 = insertelement <2 x i32> %941, i32 %981, i64 1 | |
| %983 = bitcast <2 x i32> %982 to i64 | |
| %984 = extractelement <16 x i64> %58, i64 15 | |
| %985 = call i64 @llvm.uadd.sat.i64(i64 %983, i64 %984) #3 | |
| %986 = select i1 %979, i64 %985, i64 -1 | |
| %987 = insertelement <16 x i64> undef, i64 %116, i64 0 | |
| %988 = insertelement <16 x i64> %987, i64 %174, i64 1 | |
| %989 = insertelement <16 x i64> %988, i64 %232, i64 2 | |
| %990 = insertelement <16 x i64> %989, i64 %290, i64 3 | |
| %991 = insertelement <16 x i64> %990, i64 %348, i64 4 | |
| %992 = insertelement <16 x i64> %991, i64 %406, i64 5 | |
| %993 = insertelement <16 x i64> %992, i64 %464, i64 6 | |
| %994 = insertelement <16 x i64> %993, i64 %522, i64 7 | |
| %995 = insertelement <16 x i64> %994, i64 %580, i64 8 | |
| %996 = insertelement <16 x i64> %995, i64 %638, i64 9 | |
| %997 = insertelement <16 x i64> %996, i64 %696, i64 10 | |
| %998 = insertelement <16 x i64> %997, i64 %754, i64 11 | |
| %999 = insertelement <16 x i64> %998, i64 %812, i64 12 | |
| %1000 = insertelement <16 x i64> %999, i64 %870, i64 13 | |
| %1001 = insertelement <16 x i64> %1000, i64 %928, i64 14 | |
| %1002 = insertelement <16 x i64> %1001, i64 %986, i64 15 | |
| %1003 = add i64 %49, %28 | |
| %1004 = inttoptr i64 %1003 to ptr addrspace(1) | |
| store <16 x i64> %1002, ptr addrspace(1) %1004, align 128 | |
| ret void | |
| } | |
| ; Function Attrs: nounwind readnone willreturn | |
| declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32 immarg) #1 | |
| ; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn | |
| declare i64 @llvm.uadd.sat.i64(i64, i64) #2 | |
| attributes #0 = { "amdgpu-32bit-address-high-bits"="0xffff8000" "amdgpu-flat-work-group-size"="512,512" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="+DumpCode,+wavefrontsize64,-wavefrontsize32" } | |
| attributes #1 = { nounwind readnone willreturn } | |
| attributes #2 = { nocallback nofree nosync nounwind readnone speculatable willreturn } | |
| attributes #3 = { nounwind } | |
| !0 = !{} | |
| SHADER KEY | |
| source_sha1 = {0xb5cfec13, 0x8c7db6d4, 0xa5530025, 0xc4d0316c, 0xb3130a16} | |
| opt.prefer_mono = 0 | |
| opt.inline_uniforms = 0 | |
| Compute Shader: | |
| Shader main disassembly: | |
| main: | |
| BB0_0: | |
| s_mov_b32 s0, s2 ; BE800302 | |
| s_mov_b32 s3, 0x31016fac ; BE8303FF 31016FAC | |
| s_movk_i32 s2, 0x400 ; B0020400 | |
| s_mov_b32 s1, 0x8000 ; BE8103FF 00008000 | |
| s_clause 0x1 ; BFA10001 | |
| s_buffer_load_dword s6, s[0:3], 0x20 ; F4200180 FA000020 | |
| s_buffer_load_dwordx8 s[40:47], s[0:3], 0x0 ; F42C0A00 FA000000 | |
| s_and_b32 s0, s4, 0x3ff ; 8700FF04 000003FF | |
| v_mov_b32_e32 v1, 0 ; 7E020280 | |
| s_mul_i32 s0, s0, s5 ; 93000500 | |
| s_waitcnt lgkmcnt(0) ; BF8CC07F | |
| v_add3_u32 v2, s6, s0, v0 ; D76D0002 04000006 | |
| v_ashrrev_i64 v[4:5], 25, v[1:2] ; D7010004 00020299 | |
| v_add_co_u32 v62, vcc, v4, s40 ; D70F6A3E 00005104 | |
| v_add_co_u32 v64, s[0:1], v4, s42 ; D70F0040 00005504 | |
| v_add_co_ci_u32_e32 v63, vcc, s41, v5, vcc ; 507E0A29 | |
| v_add_co_ci_u32_e64 v65, vcc, s43, v5, s[0:1] ; D5286A41 00020A2B | |
| global_load_dwordx4 v[6:9], v[62:63], off ; DC388000 067D003E | |
| global_load_dwordx4 v[10:13], v[64:65], off ; DC388000 0A7D0040 | |
| global_load_dwordx4 v[14:17], v[62:63], off offset:16 ; DC388010 0E7D003E | |
| global_load_dwordx4 v[18:21], v[64:65], off offset:16 ; DC388010 127D0040 | |
| global_load_dwordx4 v[22:25], v[62:63], off offset:32 ; DC388020 167D003E | |
| global_load_dwordx4 v[26:29], v[64:65], off offset:32 ; DC388020 1A7D0040 | |
| global_load_dwordx4 v[30:33], v[62:63], off offset:48 ; DC388030 1E7D003E | |
| global_load_dwordx4 v[34:37], v[64:65], off offset:48 ; DC388030 227D0040 | |
| global_load_dwordx4 v[38:41], v[62:63], off offset:64 ; DC388040 267D003E | |
| global_load_dwordx4 v[42:45], v[64:65], off offset:64 ; DC388040 2A7D0040 | |
| v_add_co_u32 v66, vcc, v4, s44 ; D70F6A42 00005904 | |
| v_add_co_ci_u32_e32 v67, vcc, s45, v5, vcc ; 50860A2D | |
| s_clause 0x1 ; BFA10001 | |
| global_load_dwordx4 v[46:49], v[66:67], off ; DC388000 2E7D0042 | |
| global_load_dwordx4 v[50:53], v[66:67], off offset:16 ; DC388010 327D0042 | |
| global_load_dwordx4 v[0:3], v[62:63], off offset:80 ; DC388050 007D003E | |
| s_clause 0x1 ; BFA10001 | |
| global_load_dwordx4 v[54:57], v[66:67], off offset:48 ; DC388030 367D0042 | |
| global_load_dwordx4 v[58:61], v[66:67], off offset:32 ; DC388020 3A7D0042 | |
| s_waitcnt vmcnt(13) ; BF8C3F7D | |
| v_mul_hi_u32 v69, v6, v10 ; D56A0045 00021506 | |
| v_mul_lo_u32 v68, v6, v10 ; D5690044 00021506 | |
| v_mul_hi_u32 v86, v6, v11 ; D56A0056 00021706 | |
| v_mul_lo_u32 v71, v6, v11 ; D5690047 00021706 | |
| v_mul_hi_u32 v87, v7, v10 ; D56A0057 00021507 | |
| v_mul_lo_u32 v85, v7, v10 ; D5690055 00021507 | |
| v_mul_hi_u32 v88, v7, v11 ; D56A0058 00021707 | |
| v_mul_lo_u32 v89, v7, v11 ; D5690059 00021707 | |
| v_mul_hi_u32 v10, v8, v12 ; D56A000A 00021908 | |
| v_mul_lo_u32 v11, v8, v13 ; D569000B 00021B08 | |
| v_mul_lo_u32 v92, v9, v12 ; D569005C 00021909 | |
| v_mul_lo_u32 v70, v8, v12 ; D5690046 00021908 | |
| v_mul_hi_u32 v90, v8, v13 ; D56A005A 00021B08 | |
| v_mul_hi_u32 v91, v9, v12 ; D56A005B 00021909 | |
| v_mul_hi_u32 v93, v9, v13 ; D56A005D 00021B09 | |
| v_mul_lo_u32 v94, v9, v13 ; D569005E 00021B09 | |
| s_waitcnt vmcnt(11) ; BF8C3F7B | |
| v_mul_hi_u32 v75, v14, v18 ; D56A004B 0002250E | |
| v_mul_lo_u32 v72, v14, v18 ; D5690048 0002250E | |
| v_mul_hi_u32 v96, v15, v18 ; D56A0060 0002250F | |
| v_mul_lo_u32 v97, v15, v18 ; D5690061 0002250F | |
| s_waitcnt vmcnt(9) ; BF8C3F79 | |
| v_mul_hi_u32 v105, v22, v27 ; D56A0069 00023716 | |
| v_mul_lo_u32 v18, v22, v27 ; D5690012 00023716 | |
| v_mul_hi_u32 v107, v23, v27 ; D56A006B 00023717 | |
| v_mul_lo_u32 v108, v23, v27 ; D569006C 00023717 | |
| v_mul_hi_u32 v110, v25, v28 ; D56A006E 00023919 | |
| v_mul_lo_u32 v111, v25, v28 ; D569006F 00023919 | |
| v_mul_hi_u32 v112, v25, v29 ; D56A0070 00023B19 | |
| v_mul_lo_u32 v113, v25, v29 ; D5690071 00023B19 | |
| v_add_co_u32 v25, vcc, v69, v71 ; D70F6A19 00028F45 | |
| v_add3_u32 v69, v71, v85, v69 ; D76D0045 0516AB47 | |
| v_add_co_u32 v27, s[0:1], v10, v11 ; D70F001B 0002170A | |
| v_add3_u32 v71, v11, v92, v10 ; D76D0047 042AB90B | |
| global_load_dwordx4 v[10:13], v[66:67], off offset:64 ; DC388040 0A7D0042 | |
| global_load_dwordx4 v[6:9], v[64:65], off offset:80 ; DC388050 067D0040 | |
| v_mul_hi_u32 v95, v14, v19 ; D56A005F 0002270E | |
| v_mul_lo_u32 v14, v14, v19 ; D569000E 0002270E | |
| v_mul_hi_u32 v98, v15, v19 ; D56A0062 0002270F | |
| v_mul_lo_u32 v99, v15, v19 ; D5690063 0002270F | |
| v_mul_hi_u32 v15, v16, v20 ; D56A000F 00022910 | |
| v_mul_lo_u32 v74, v16, v20 ; D569004A 00022910 | |
| v_mul_hi_u32 v100, v16, v21 ; D56A0064 00022B10 | |
| v_mul_lo_u32 v16, v16, v21 ; D5690010 00022B10 | |
| v_mul_hi_u32 v101, v17, v20 ; D56A0065 00022911 | |
| v_mul_lo_u32 v102, v17, v20 ; D5690066 00022911 | |
| v_mul_hi_u32 v103, v17, v21 ; D56A0067 00022B11 | |
| v_mul_lo_u32 v104, v17, v21 ; D5690068 00022B11 | |
| v_mul_hi_u32 v17, v22, v26 ; D56A0011 00023516 | |
| v_mul_lo_u32 v76, v22, v26 ; D569004C 00023516 | |
| v_mul_hi_u32 v106, v23, v26 ; D56A006A 00023517 | |
| v_mul_lo_u32 v26, v23, v26 ; D569001A 00023517 | |
| v_mul_hi_u32 v19, v24, v28 ; D56A0013 00023918 | |
| v_mul_lo_u32 v78, v24, v28 ; D569004E 00023918 | |
| v_mul_hi_u32 v109, v24, v29 ; D56A006D 00023B18 | |
| v_mul_lo_u32 v20, v24, v29 ; D5690014 00023B18 | |
| s_waitcnt vmcnt(9) ; BF8C3F79 | |
| v_mul_hi_u32 v21, v30, v34 ; D56A0015 0002451E | |
| v_mul_lo_u32 v80, v30, v34 ; D5690050 0002451E | |
| v_mul_hi_u32 v114, v30, v35 ; D56A0072 0002471E | |
| v_mul_lo_u32 v22, v30, v35 ; D5690016 0002471E | |
| v_add3_u32 v73, v14, v97, v75 ; D76D0049 052EC30E | |
| v_add_co_u32 v28, s[2:3], v75, v14 ; D70F021C 00021D4B | |
| v_add_co_u32 v29, s[4:5], v15, v16 ; D70F041D 0002210F | |
| v_add3_u32 v75, v16, v102, v15 ; D76D004B 043ECD10 | |
| v_add3_u32 v77, v18, v26, v17 ; D76D004D 04463512 | |
| v_add_co_u32 v30, s[8:9], v17, v18 ; D70F081E 00022511 | |
| global_load_dwordx4 v[14:17], v[66:67], off offset:80 ; DC388050 0E7D0042 | |
| v_mul_hi_u32 v115, v31, v34 ; D56A0073 0002451F | |
| v_mul_lo_u32 v34, v31, v34 ; D5690022 0002451F | |
| v_mul_hi_u32 v23, v32, v36 ; D56A0017 00024920 | |
| v_mul_lo_u32 v24, v32, v37 ; D5690018 00024B20 | |
| v_mul_lo_u32 v120, v33, v36 ; D5690078 00024921 | |
| s_waitcnt vmcnt(8) ; BF8C3F78 | |
| v_mul_hi_u32 v123, v38, v42 ; D56A007B 00025526 | |
| v_mul_lo_u32 v84, v38, v42 ; D5690054 00025526 | |
| v_mul_hi_u32 v126, v39, v42 ; D56A007E 00025527 | |
| v_mul_lo_u32 v127, v39, v42 ; D569007F 00025527 | |
| v_mul_hi_u32 v130, v40, v44 ; D56A0082 00025928 | |
| v_mul_hi_u32 v133, v41, v44 ; D56A0085 00025929 | |
| v_mul_lo_u32 v134, v41, v44 ; D5690086 00025929 | |
| v_mul_lo_u32 v42, v40, v44 ; D569002A 00025928 | |
| s_waitcnt vmcnt(7) ; BF8C3F77 | |
| v_add_co_u32 v44, s[6:7], v68, v46 ; D70F062C 00025D44 | |
| v_add_co_u32 v46, s[12:13], v70, v48 ; D70F0C2E 00026146 | |
| s_waitcnt vmcnt(6) ; BF8C3F76 | |
| v_add_co_u32 v48, s[14:15], v72, v50 ; D70F0E30 00026548 | |
| v_add_co_u32 v50, s[18:19], v74, v52 ; D70F1232 0002694A | |
| v_mul_hi_u32 v131, v40, v45 ; D56A0083 00025B28 | |
| v_mul_lo_u32 v132, v40, v45 ; D5690084 00025B28 | |
| v_mul_hi_u32 v135, v41, v45 ; D56A0087 00025B29 | |
| v_mul_lo_u32 v136, v41, v45 ; D5690088 00025B29 | |
| v_add_co_ci_u32_e64 v45, s[6:7], v69, v47, s[6:7] ; D528062D 001A5F45 | |
| v_add_co_ci_u32_e64 v47, s[6:7], v71, v49, s[12:13] ; D528062F 00326347 | |
| v_add_co_ci_u32_e64 v49, s[14:15], v73, v51, s[14:15] ; D5280E31 003A6749 | |
| v_add_co_ci_u32_e64 v51, s[14:15], v75, v53, s[18:19] ; D5280E33 004A6B4B | |
| v_mul_hi_u32 v116, v31, v35 ; D56A0074 0002471F | |
| v_mul_lo_u32 v117, v31, v35 ; D5690075 0002471F | |
| v_add3_u32 v81, v22, v34, v21 ; D76D0051 04564516 | |
| v_add_co_u32 v35, s[6:7], v21, v22 ; D70F0623 00022D15 | |
| v_add_co_u32 v18, s[16:17], v25, v85 ; D70F1012 0002AB19 | |
| v_add_co_u32 v22, s[14:15], v27, v92 ; D70F0E16 0002B91B | |
| v_add_co_u32 v22, s[20:21], v28, v97 ; D70F1416 0002C31C | |
| v_mul_hi_u32 v124, v38, v43 ; D56A007C 00025726 | |
| v_mul_lo_u32 v125, v38, v43 ; D569007D 00025726 | |
| v_add_co_u32 v31, s[10:11], v19, v20 ; D70F0A1F 00022913 | |
| v_add3_u32 v79, v20, v111, v19 ; D76D004F 044EDF14 | |
| v_add_co_u32 v38, s[12:13], v23, v24 ; D70F0C26 00023117 | |
| v_add3_u32 v83, v24, v120, v23 ; D76D0053 045EF118 | |
| global_load_dwordx4 v[22:25], v[64:65], off offset:96 ; DC388060 167D0040 | |
| global_load_dwordx4 v[18:21], v[62:63], off offset:96 ; DC388060 127D003E | |
| s_waitcnt vmcnt(5) ; BF8C3F75 | |
| v_add_co_u32 v52, s[18:19], v76, v58 ; D70F1234 0002754C | |
| v_add_co_u32 v58, s[22:23], v78, v60 ; D70F163A 0002794E | |
| v_add_co_ci_u32_e64 v53, s[18:19], v77, v59, s[18:19] ; D5281235 004A774D | |
| v_add_co_ci_u32_e64 v59, s[18:19], v79, v61, s[22:23] ; D528123B 005A7B4F | |
| v_add_co_u32 v27, s[18:19], v29, v102 ; D70F121B 0002CD1D | |
| v_add_co_u32 v26, s[24:25], v30, v26 ; D70F181A 0002351E | |
| global_load_dwordx4 v[26:29], v[66:67], off offset:96 ; DC388060 1A7D0042 | |
| v_mul_lo_u32 v82, v32, v36 ; D5690052 00024920 | |
| v_add_co_u32 v54, s[22:23], v80, v54 ; D70F1636 00026D50 | |
| v_add_co_ci_u32_e64 v55, s[22:23], v81, v55, s[22:23] ; D5281637 005A6F51 | |
| v_mul_hi_u32 v118, v32, v37 ; D56A0076 00024B20 | |
| v_mul_hi_u32 v119, v33, v36 ; D56A0077 00024921 | |
| v_mul_hi_u32 v121, v33, v37 ; D56A0079 00024B21 | |
| v_add_co_u32 v56, s[26:27], v82, v56 ; D70F1A38 00027152 | |
| v_add_co_ci_u32_e64 v57, s[22:23], v83, v57, s[26:27] ; D5281639 006A7353 | |
| v_add_co_u32 v30, s[22:23], v31, v111 ; D70F161E 0002DF1F | |
| v_add_co_u32 v34, s[26:27], v35, v34 ; D70F1A22 00024523 | |
| v_mul_lo_u32 v122, v33, v37 ; D569007A 00024B21 | |
| global_load_dwordx4 v[30:33], v[62:63], off offset:112 ; DC388070 1E7D003E | |
| global_load_dwordx4 v[34:37], v[64:65], off offset:112 ; DC388070 227D0040 | |
| v_add_co_u32 v38, s[28:29], v38, v120 ; D70F1C26 0002F126 | |
| v_mul_hi_u32 v128, v39, v43 ; D56A0080 00025727 | |
| v_mul_lo_u32 v129, v39, v43 ; D5690081 00025727 | |
| global_load_dwordx4 v[38:41], v[66:67], off offset:112 ; DC388070 267D0042 | |
| v_add_co_u32 v60, s[30:31], v123, v125 ; D70F1E3C 0002FB7B | |
| v_add_co_u32 v61, s[34:35], v130, v132 ; D70F223D 00030982 | |
| v_add3_u32 v43, v132, v134, v130 ; D76D002B 060B0D84 | |
| v_add_co_u32 v60, s[36:37], v60, v127 ; D70F243C 0002FF3C | |
| v_add_co_u32 v60, s[40:41], v61, v134 ; D70F283C 00030D3D | |
| v_add3_u32 v85, v125, v127, v123 ; D76D0055 05EEFF7D | |
| s_waitcnt vmcnt(8) ; BF8C3F78 | |
| v_add_co_u32 v60, s[42:43], v42, v12 ; D70F2A3C 0002192A | |
| v_add_co_ci_u32_e32 v12, vcc, 0, v86, vcc ; 5018AC80 | |
| v_add_co_ci_u32_e64 v62, vcc, 0, v90, s[0:1] ; D5286A3E 0002B480 | |
| v_add_co_ci_u32_e64 v65, vcc, 0, v105, s[8:9] ; D5286A41 0022D280 | |
| v_add_co_ci_u32_e64 v63, vcc, 0, v95, s[2:3] ; D5286A3F 000ABE80 | |
| v_add_co_u32 v10, s[38:39], v84, v10 ; D70F260A 00021554 | |
| v_add_co_ci_u32_e64 v64, vcc, 0, v100, s[4:5] ; D5286A40 0012C880 | |
| v_add_co_ci_u32_e64 v67, vcc, 0, v114, s[6:7] ; D5286A43 001AE480 | |
| v_add_co_ci_u32_e64 v90, vcc, 0, v124, s[30:31] ; D5286A5A 007AF880 | |
| v_add_co_ci_u32_e64 v95, vcc, 0, v131, s[34:35] ; D5286A5F 008B0680 | |
| v_add_co_ci_u32_e64 v61, vcc, v43, v13, s[42:43] ; D5286A3D 00AA1B2B | |
| v_add_co_ci_u32_e64 v13, vcc, 0, v87, s[16:17] ; D5286A0D 0042AE80 | |
| v_add_co_ci_u32_e64 v87, s[0:1], 0, v91, s[14:15] ; D5280057 003AB680 | |
| v_add_co_ci_u32_e64 v66, vcc, 0, v109, s[10:11] ; D5286A42 002ADA80 | |
| v_add_co_ci_u32_e64 v86, vcc, 0, v118, s[12:13] ; D5286A56 0032EC80 | |
| v_add_co_ci_u32_e64 v11, vcc, v85, v11, s[38:39] ; D5286A0B 009A1755 | |
| v_add_co_u32 v62, s[0:1], v62, v94 ; D70F003E 0002BD3E | |
| v_add_co_ci_u32_e64 v94, s[6:7], 0, v106, s[24:25] ; D528065E 0062D480 | |
| v_add_co_u32 v12, vcc, v12, v89 ; D70F6A0C 0002B30C | |
| v_add_co_ci_u32_e64 v89, s[2:3], 0, v96, s[20:21] ; D5280259 0052C080 | |
| v_add_co_u32 v65, s[6:7], v65, v108 ; D70F0641 0002D941 | |
| v_add_co_u32 v63, s[2:3], v63, v99 ; D70F023F 0002C73F | |
| v_add_co_ci_u32_e64 v91, s[4:5], 0, v101, s[18:19] ; D528045B 004ACA80 | |
| v_add_co_ci_u32_e64 v99, s[10:11], 0, v115, s[26:27] ; D5280A63 006AE680 | |
| v_add_co_u32 v64, s[4:5], v64, v104 ; D70F0440 0002D140 | |
| v_add_co_u32 v67, s[10:11], v67, v117 ; D70F0A43 0002EB43 | |
| v_add_co_ci_u32_e64 v101, s[14:15], 0, v126, s[36:37] ; D5280E65 0092FC80 | |
| v_add_co_ci_u32_e64 v102, s[16:17], 0, v133, s[40:41] ; D5281066 00A30A80 | |
| v_add_co_ci_u32_e32 v88, vcc, 0, v88, vcc ; 50B0B080 | |
| v_add_co_ci_u32_e64 v93, vcc, 0, v93, s[0:1] ; D5286A5D 0002BA80 | |
| v_add_co_ci_u32_e64 v104, vcc, 0, v107, s[6:7] ; D5286A68 001AD680 | |
| v_add_co_ci_u32_e64 v96, s[8:9], 0, v110, s[22:23] ; D5280860 005ADC80 | |
| v_add_co_u32 v90, s[14:15], v90, v129 ; D70F0E5A 0003035A | |
| v_add_co_u32 v95, s[16:17], v95, v136 ; D70F105F 0003115F | |
| v_add_co_u32 v97, s[8:9], v66, v113 ; D70F0861 0002E342 | |
| v_add_co_ci_u32_e64 v103, vcc, 0, v103, s[4:5] ; D5286A67 0012CE80 | |
| v_add_co_ci_u32_e64 v106, vcc, 0, v116, s[10:11] ; D5286A6A 002AE880 | |
| v_add_co_ci_u32_e64 v108, vcc, 0, v128, s[14:15] ; D5286A6C 003B0080 | |
| v_add_co_ci_u32_e64 v109, vcc, 0, v135, s[16:17] ; D5286A6D 00430E80 | |
| v_cmp_lt_u64_e64 s[16:17], v[60:61], v[42:43] ; D4E10010 0002553C | |
| v_add_co_u32 v12, s[18:19], v12, v13 ; D70F120C 00021B0C | |
| v_add_co_u32 v42, s[20:21], v62, v87 ; D70F142A 0002AF3E | |
| v_add_co_u32 v66, s[26:27], v65, v94 ; D70F1A42 0002BD41 | |
| v_add_co_ci_u32_e64 v100, s[12:13], 0, v119, s[28:29] ; D5280C64 0072EE80 | |
| v_add_co_ci_u32_e64 v98, vcc, 0, v98, s[2:3] ; D5286A62 000AC480 | |
| v_add_co_ci_u32_e64 v105, vcc, 0, v112, s[8:9] ; D5286A69 0022E080 | |
| v_cmp_lt_u64_e64 s[2:3], v[48:49], v[72:73] ; D4E10002 00029130 | |
| v_cmp_lt_u64_e64 s[8:9], v[58:59], v[78:79] ; D4E10008 00029D3A | |
| v_add_co_u32 v86, s[12:13], v86, v122 ; D70F0C56 0002F556 | |
| v_cmp_lt_u64_e64 s[0:1], v[46:47], v[70:71] ; D4E10000 00028D2E | |
| v_cmp_lt_u64_e64 s[6:7], v[52:53], v[76:77] ; D4E10006 00029934 | |
| v_add_co_u32 v70, s[30:31], v67, v99 ; D70F1E46 0002C743 | |
| v_add_co_ci_u32_e64 v13, s[18:19], 0, v88, s[18:19] ; D528120D 004AB080 | |
| v_add_co_ci_u32_e64 v43, s[18:19], 0, v93, s[20:21] ; D528122B 0052BA80 | |
| v_add_co_ci_u32_e64 v67, s[18:19], 0, v104, s[26:27] ; D5281243 006AD080 | |
| v_cmp_lt_u64_e64 s[4:5], v[50:51], v[74:75] ; D4E10004 00029532 | |
| v_add_co_u32 v64, s[24:25], v64, v91 ; D70F1840 0002B740 | |
| v_add_co_u32 v74, s[36:37], v90, v101 ; D70F244A 0002CB5A | |
| v_add_co_ci_u32_e64 v107, vcc, 0, v121, s[12:13] ; D5286A6B 0032F280 | |
| v_cmp_lt_u64_e64 s[12:13], v[56:57], v[82:83] ; D4E1000C 0002A538 | |
| v_cmp_lt_u64_e64 s[14:15], v[10:11], v[84:85] ; D4E1000E 0002A90A | |
| v_cmp_lt_u64_e32 vcc, v[44:45], v[68:69] ; 7DC2892C | |
| v_cmp_lt_u64_e64 s[10:11], v[54:55], v[80:81] ; D4E1000A 0002A136 | |
| v_add_co_u32 v62, s[22:23], v63, v89 ; D70F163E 0002B33F | |
| v_add_co_u32 v68, s[28:29], v97, v96 ; D70F1C44 0002C161 | |
| v_add_co_ci_u32_e64 v65, s[18:19], 0, v103, s[24:25] ; D5281241 0062CE80 | |
| v_add_co_ci_u32_e64 v71, s[18:19], 0, v106, s[30:31] ; D5281247 007AD480 | |
| v_add_co_ci_u32_e64 v75, s[18:19], 0, v108, s[36:37] ; D528124B 0092D880 | |
| v_add_co_ci_u32_e64 v63, s[18:19], 0, v98, s[22:23] ; D528123F 005AC480 | |
| v_add_co_ci_u32_e64 v69, s[18:19], 0, v105, s[28:29] ; D5281245 0072D280 | |
| v_cndmask_b32_e64 v48, v48, -1, s[2:3] ; D5010030 00098330 | |
| v_cndmask_b32_e64 v49, v49, -1, s[2:3] ; D5010031 00098331 | |
| v_cndmask_b32_e64 v58, v58, -1, s[8:9] ; D501003A 0021833A | |
| v_cndmask_b32_e64 v59, v59, -1, s[8:9] ; D501003B 0021833B | |
| v_cmp_eq_u64_e64 s[2:3], 0, v[42:43] ; D4E20002 00025480 | |
| v_cmp_eq_u64_e64 s[8:9], 0, v[66:67] ; D4E20008 00028480 | |
| v_add_co_u32 v72, s[34:35], v86, v100 ; D70F2248 0002C956 | |
| v_cndmask_b32_e64 v46, v46, -1, s[0:1] ; D501002E 0001832E | |
| v_cndmask_b32_e64 v52, v52, -1, s[6:7] ; D5010034 00198334 | |
| v_add_co_ci_u32_e64 v73, s[18:19], 0, v107, s[34:35] ; D5281249 008AD680 | |
| v_cndmask_b32_e64 v47, v47, -1, s[0:1] ; D501002F 0001832F | |
| v_cndmask_b32_e64 v53, v53, -1, s[6:7] ; D5010035 00198335 | |
| v_cndmask_b32_e64 v78, v56, -1, s[12:13] ; D501004E 00318338 | |
| v_cndmask_b32_e64 v56, v57, -1, s[12:13] ; D5010038 00318339 | |
| v_cndmask_b32_e64 v57, v10, -1, s[14:15] ; D5010039 0039830A | |
| v_cndmask_b32_e64 v79, v11, -1, s[14:15] ; D501004F 0039830B | |
| v_cmp_eq_u64_e64 s[0:1], 0, v[12:13] ; D4E20000 00021880 | |
| v_cmp_eq_u64_e64 s[6:7], 0, v[64:65] ; D4E20006 00028080 | |
| v_cmp_eq_u64_e64 s[12:13], 0, v[70:71] ; D4E2000C 00028C80 | |
| v_cmp_eq_u64_e64 s[14:15], 0, v[74:75] ; D4E2000E 00029480 | |
| v_cndmask_b32_e64 v44, v44, -1, vcc ; D501002C 01A9832C | |
| v_cndmask_b32_e64 v50, v50, -1, s[4:5] ; D5010032 00118332 | |
| v_cndmask_b32_e64 v54, v54, -1, s[10:11] ; D5010036 00298336 | |
| v_cndmask_b32_e64 v51, v51, -1, s[4:5] ; D5010033 00118333 | |
| v_cndmask_b32_e64 v55, v55, -1, s[10:11] ; D5010037 00298337 | |
| v_cmp_eq_u64_e64 s[4:5], 0, v[62:63] ; D4E20004 00027C80 | |
| v_cmp_eq_u64_e64 s[10:11], 0, v[68:69] ; D4E2000A 00028880 | |
| s_waitcnt vmcnt(7) ; BF8C3F77 | |
| v_mul_hi_u32 v92, v0, v6 ; D56A005C 00020D00 | |
| v_cndmask_b32_e64 v12, -1, v46, s[2:3] ; D501000C 000A5CC1 | |
| v_cndmask_b32_e64 v46, -1, v52, s[8:9] ; D501002E 002268C1 | |
| v_mul_lo_u32 v52, v0, v7 ; D5690034 00020F00 | |
| v_cndmask_b32_e64 v45, v45, -1, vcc ; D501002D 01A9832D | |
| v_cmp_eq_u64_e32 vcc, 0, v[72:73] ; 7DC49080 | |
| v_cndmask_b32_e64 v10, -1, v44, s[0:1] ; D501000A 000258C1 | |
| v_cndmask_b32_e64 v44, -1, v50, s[6:7] ; D501002C 001A64C1 | |
| v_cndmask_b32_e64 v50, -1, v54, s[12:13] ; D5010032 00326CC1 | |
| v_cndmask_b32_e64 v54, -1, v57, s[14:15] ; D5010036 003A72C1 | |
| v_mul_hi_u32 v57, v0, v7 ; D56A0039 00020F00 | |
| v_cndmask_b32_e64 v42, -1, v48, s[4:5] ; D501002A 001260C1 | |
| v_cndmask_b32_e64 v48, -1, v58, s[10:11] ; D5010030 002A74C1 | |
| v_mul_lo_u32 v58, v1, v6 ; D569003A 00020D01 | |
| v_mul_lo_u32 v0, v0, v6 ; D5690000 00020D00 | |
| v_mul_hi_u32 v6, v1, v6 ; D56A0006 00020D01 | |
| v_cndmask_b32_e64 v13, -1, v47, s[2:3] ; D501000D 000A5EC1 | |
| v_cndmask_b32_e64 v43, -1, v49, s[4:5] ; D501002B 001262C1 | |
| v_cndmask_b32_e64 v47, -1, v53, s[8:9] ; D501002F 00226AC1 | |
| v_cndmask_b32_e64 v49, -1, v59, s[10:11] ; D5010031 002A76C1 | |
| v_cndmask_b32_e32 v53, -1, v56, vcc ; 026A70C1 | |
| v_cndmask_b32_e64 v56, v61, -1, s[16:17] ; D5010038 0041833D | |
| v_add_co_u32 v59, s[2:3], v92, v52 ; D70F023B 0002695C | |
| v_mul_lo_u32 v61, v1, v7 ; D569003D 00020F01 | |
| v_mul_hi_u32 v7, v1, v7 ; D56A0007 00020F01 | |
| v_add_co_ci_u32_e64 v57, s[2:3], 0, v57, s[2:3] ; D5280239 000A7280 | |
| v_add_co_u32 v1, s[2:3], v59, v58 ; D70F0201 0002753B | |
| v_add_co_ci_u32_e64 v59, s[2:3], 0, v6, s[2:3] ; D528023B 000A0C80 | |
| v_add_co_u32 v76, s[38:39], v95, v102 ; D70F264C 0002CD5F | |
| v_add_co_u32 v57, s[2:3], v57, v61 ; D70F0239 00027B39 | |
| v_add3_u32 v1, v52, v58, v92 ; D76D0001 05727534 | |
| v_add_co_ci_u32_e64 v77, s[18:19], 0, v109, s[38:39] ; D528124D 009ADA80 | |
| v_add_co_ci_u32_e64 v52, s[2:3], 0, v7, s[2:3] ; D5280234 000A0E80 | |
| s_waitcnt vmcnt(6) ; BF8C3F76 | |
| v_add_co_u32 v6, s[2:3], v0, v14 ; D70F0206 00021D00 | |
| v_add_co_ci_u32_e64 v7, s[2:3], v1, v15, s[2:3] ; D5280207 000A1F01 | |
| v_cndmask_b32_e64 v11, -1, v45, s[0:1] ; D501000B 00025AC1 | |
| v_cmp_eq_u64_e64 s[0:1], 0, v[76:77] ; D4E20000 00029880 | |
| v_add_co_u32 v14, s[2:3], v57, v59 ; D70F020E 00027739 | |
| v_add_co_ci_u32_e64 v15, s[2:3], 0, v52, s[2:3] ; D528020F 000A6880 | |
| v_cmp_lt_u64_e64 s[2:3], v[6:7], v[0:1] ; D4E10002 00020106 | |
| v_cndmask_b32_e64 v57, -1, v56, s[0:1] ; D5010039 000270C1 | |
| v_mul_hi_u32 v1, v2, v8 ; D56A0001 00021102 | |
| v_mul_lo_u32 v56, v2, v9 ; D5690038 00021302 | |
| v_cmp_eq_u64_e64 s[4:5], 0, v[14:15] ; D4E20004 00021C80 | |
| v_mul_lo_u32 v0, v2, v8 ; D5690000 00021102 | |
| v_cndmask_b32_e64 v14, v6, -1, s[2:3] ; D501000E 00098306 | |
| v_mul_hi_u32 v6, v2, v9 ; D56A0006 00021302 | |
| v_mul_lo_u32 v2, v3, v8 ; D5690002 00021103 | |
| v_mul_hi_u32 v8, v3, v8 ; D56A0008 00021103 | |
| v_cndmask_b32_e64 v15, v7, -1, s[2:3] ; D501000F 00098307 | |
| v_add_co_u32 v7, s[2:3], v1, v56 ; D70F0207 00027101 | |
| v_mul_lo_u32 v58, v3, v9 ; D569003A 00021303 | |
| v_mul_hi_u32 v3, v3, v9 ; D56A0003 00021303 | |
| v_add_co_ci_u32_e64 v6, s[2:3], 0, v6, s[2:3] ; D5280206 000A0C80 | |
| v_add_co_u32 v7, s[2:3], v7, v2 ; D70F0207 00020507 | |
| v_add_co_ci_u32_e64 v7, s[2:3], 0, v8, s[2:3] ; D5280207 000A1080 | |
| v_add_co_u32 v6, s[2:3], v6, v58 ; D70F0206 00027506 | |
| v_add3_u32 v1, v56, v2, v1 ; D76D0001 04060538 | |
| v_add_co_ci_u32_e64 v8, s[2:3], 0, v3, s[2:3] ; D5280208 000A0680 | |
| v_add_co_u32 v2, s[2:3], v0, v16 ; D70F0202 00022100 | |
| v_add_co_ci_u32_e64 v3, s[2:3], v1, v17, s[2:3] ; D5280203 000A2301 | |
| v_add_co_u32 v6, s[2:3], v6, v7 ; D70F0206 00020F06 | |
| v_add_co_ci_u32_e64 v7, s[2:3], 0, v8, s[2:3] ; D5280207 000A1080 | |
| s_waitcnt vmcnt(4) ; BF8C3F74 | |
| v_mul_hi_u32 v8, v18, v22 ; D56A0008 00022D12 | |
| v_mul_lo_u32 v9, v18, v23 ; D5690009 00022F12 | |
| v_cndmask_b32_e64 v45, -1, v51, s[6:7] ; D501002D 001A66C1 | |
| v_cmp_eq_u64_e64 s[2:3], 0, v[6:7] ; D4E20002 00020C80 | |
| v_mul_hi_u32 v7, v18, v23 ; D56A0007 00022F12 | |
| v_cmp_lt_u64_e64 s[6:7], v[2:3], v[0:1] ; D4E10006 00020102 | |
| v_cndmask_b32_e64 v0, -1, v14, s[4:5] ; D5010000 00121CC1 | |
| v_mul_lo_u32 v14, v19, v22 ; D569000E 00022D13 | |
| v_mul_hi_u32 v16, v19, v22 ; D56A0010 00022D13 | |
| v_cndmask_b32_e64 v1, -1, v15, s[4:5] ; D5010001 00121EC1 | |
| v_add_co_u32 v15, s[4:5], v8, v9 ; D70F040F 00021308 | |
| v_mul_lo_u32 v17, v19, v23 ; D5690011 00022F13 | |
| v_mul_lo_u32 v6, v18, v22 ; D5690006 00022D12 | |
| v_mul_hi_u32 v18, v19, v23 ; D56A0012 00022F13 | |
| v_add_co_ci_u32_e64 v7, s[4:5], 0, v7, s[4:5] ; D5280407 00120E80 | |
| v_add_co_u32 v15, s[4:5], v15, v14 ; D70F040F 00021D0F | |
| v_add_co_ci_u32_e64 v15, s[4:5], 0, v16, s[4:5] ; D528040F 00122080 | |
| v_add_co_u32 v16, s[4:5], v7, v17 ; D70F0410 00022307 | |
| v_add3_u32 v7, v9, v14, v8 ; D76D0007 04221D09 | |
| v_add_co_ci_u32_e64 v17, s[4:5], 0, v18, s[4:5] ; D5280411 00122480 | |
| s_waitcnt vmcnt(3) ; BF8C3F73 | |
| v_add_co_u32 v8, s[4:5], v6, v26 ; D70F0408 00023506 | |
| v_add_co_ci_u32_e64 v9, s[4:5], v7, v27, s[4:5] ; D5280409 00123707 | |
| v_add_co_u32 v14, s[4:5], v16, v15 ; D70F040E 00021F10 | |
| v_add_co_ci_u32_e64 v15, s[4:5], 0, v17, s[4:5] ; D528040F 00122280 | |
| v_cmp_lt_u64_e64 s[4:5], v[8:9], v[6:7] ; D4E10004 00020D08 | |
| v_mul_hi_u32 v7, v20, v24 ; D56A0007 00023114 | |
| v_mul_lo_u32 v16, v20, v25 ; D5690010 00023314 | |
| v_cmp_eq_u64_e64 s[8:9], 0, v[14:15] ; D4E20008 00021C80 | |
| v_mul_hi_u32 v15, v21, v24 ; D56A000F 00023115 | |
| v_mul_lo_u32 v19, v21, v25 ; D5690013 00023315 | |
| v_cndmask_b32_e64 v17, v8, -1, s[4:5] ; D5010011 00118308 | |
| v_mul_hi_u32 v8, v20, v25 ; D56A0008 00023314 | |
| v_cndmask_b32_e64 v18, v9, -1, s[4:5] ; D5010012 00118309 | |
| v_mul_lo_u32 v9, v21, v24 ; D5690009 00023115 | |
| v_add_co_u32 v14, s[4:5], v7, v16 ; D70F040E 00022107 | |
| v_mul_lo_u32 v6, v20, v24 ; D5690006 00023114 | |
| v_mul_hi_u32 v20, v21, v25 ; D56A0014 00023315 | |
| v_cndmask_b32_e64 v3, v3, -1, s[6:7] ; D5010003 00198303 | |
| v_add_co_ci_u32_e64 v8, s[4:5], 0, v8, s[4:5] ; D5280408 00121080 | |
| v_add_co_u32 v14, s[4:5], v14, v9 ; D70F040E 0002130E | |
| v_add_co_ci_u32_e64 v14, s[4:5], 0, v15, s[4:5] ; D528040E 00121E80 | |
| v_add_co_u32 v15, s[4:5], v8, v19 ; D70F040F 00022708 | |
| v_add3_u32 v7, v16, v9, v7 ; D76D0007 041E1310 | |
| v_add_co_ci_u32_e64 v16, s[4:5], 0, v20, s[4:5] ; D5280410 00122880 | |
| v_add_co_u32 v8, s[4:5], v6, v28 ; D70F0408 00023906 | |
| v_add_co_ci_u32_e64 v9, s[4:5], v7, v29, s[4:5] ; D5280409 00123B07 | |
| v_add_co_u32 v14, s[4:5], v15, v14 ; D70F040E 00021D0F | |
| v_add_co_ci_u32_e64 v15, s[4:5], 0, v16, s[4:5] ; D528040F 00122080 | |
| v_cndmask_b32_e64 v2, v2, -1, s[6:7] ; D5010002 00198302 | |
| v_cmp_lt_u64_e64 s[6:7], v[8:9], v[6:7] ; D4E10006 00020D08 | |
| v_cndmask_b32_e64 v7, -1, v18, s[8:9] ; D5010007 002224C1 | |
| s_waitcnt vmcnt(1) ; BF8C3F71 | |
| v_mul_hi_u32 v16, v30, v34 ; D56A0010 0002451E | |
| v_mul_lo_u32 v18, v30, v35 ; D5690012 0002471E | |
| v_cmp_eq_u64_e64 s[4:5], 0, v[14:15] ; D4E20004 00021C80 | |
| v_mul_hi_u32 v15, v30, v35 ; D56A000F 0002471E | |
| v_cndmask_b32_e64 v6, -1, v17, s[8:9] ; D5010006 002222C1 | |
| v_mul_lo_u32 v17, v31, v34 ; D5690011 0002451F | |
| v_mul_hi_u32 v20, v31, v34 ; D56A0014 0002451F | |
| v_mul_lo_u32 v21, v31, v35 ; D5690015 0002471F | |
| v_mul_lo_u32 v14, v30, v34 ; D569000E 0002451E | |
| v_add_co_u32 v19, s[8:9], v16, v18 ; D70F0813 00022510 | |
| v_add_co_ci_u32_e64 v15, s[8:9], 0, v15, s[8:9] ; D528080F 00221E80 | |
| v_mul_hi_u32 v22, v31, v35 ; D56A0016 0002471F | |
| v_add_co_u32 v19, s[8:9], v19, v17 ; D70F0813 00022313 | |
| v_add_co_ci_u32_e64 v19, s[8:9], 0, v20, s[8:9] ; D5280813 00222880 | |
| v_add_co_u32 v20, s[8:9], v15, v21 ; D70F0814 00022B0F | |
| v_add3_u32 v15, v18, v17, v16 ; D76D000F 04422312 | |
| s_waitcnt vmcnt(0) ; BF8C3F70 | |
| v_add_co_u32 v18, s[10:11], v14, v38 ; D70F0A12 00024D0E | |
| v_add_co_ci_u32_e64 v21, s[8:9], 0, v22, s[8:9] ; D5280815 00222C80 | |
| v_add_co_u32 v16, s[8:9], v20, v19 ; D70F0810 00022714 | |
| v_add_co_ci_u32_e64 v19, s[10:11], v15, v39, s[10:11] ; D5280A13 002A4F0F | |
| v_mul_hi_u32 v20, v32, v36 ; D56A0014 00024920 | |
| v_mul_lo_u32 v22, v32, v37 ; D5690016 00024B20 | |
| v_add_co_ci_u32_e64 v17, s[8:9], 0, v21, s[8:9] ; D5280811 00222A80 | |
| v_cmp_lt_u64_e64 s[8:9], v[18:19], v[14:15] ; D4E10008 00021D12 | |
| v_mul_hi_u32 v15, v32, v37 ; D56A000F 00024B20 | |
| v_mul_lo_u32 v21, v33, v36 ; D5690015 00024921 | |
| v_mul_hi_u32 v24, v33, v36 ; D56A0018 00024921 | |
| v_mul_lo_u32 v25, v33, v37 ; D5690019 00024B21 | |
| v_add_co_u32 v23, s[10:11], v20, v22 ; D70F0A17 00022D14 | |
| v_mul_hi_u32 v26, v33, v37 ; D56A001A 00024B21 | |
| v_mul_lo_u32 v14, v32, v36 ; D569000E 00024920 | |
| v_add_co_ci_u32_e64 v15, s[10:11], 0, v15, s[10:11] ; D5280A0F 002A1E80 | |
| v_add_co_u32 v23, s[10:11], v23, v21 ; D70F0A17 00022B17 | |
| v_add_co_ci_u32_e64 v23, s[10:11], 0, v24, s[10:11] ; D5280A17 002A3080 | |
| v_add_co_u32 v24, s[10:11], v15, v25 ; D70F0A18 0002330F | |
| v_add3_u32 v15, v22, v21, v20 ; D76D000F 04522B16 | |
| v_add_co_ci_u32_e64 v25, s[10:11], 0, v26, s[10:11] ; D5280A19 002A3480 | |
| v_add_co_u32 v20, s[10:11], v14, v40 ; D70F0A14 0002510E | |
| v_add_co_ci_u32_e64 v21, s[10:11], v15, v41, s[10:11] ; D5280A15 002A530F | |
| v_add_co_u32 v22, s[10:11], v24, v23 ; D70F0A16 00022F18 | |
| v_add_co_ci_u32_e64 v23, s[10:11], 0, v25, s[10:11] ; D5280A17 002A3280 | |
| v_cmp_lt_u64_e64 s[10:11], v[20:21], v[14:15] ; D4E1000A 00021D14 | |
| v_cndmask_b32_e64 v8, v8, -1, s[6:7] ; D5010008 00198308 | |
| v_cndmask_b32_e64 v9, v9, -1, s[6:7] ; D5010009 00198309 | |
| v_cmp_eq_u64_e64 s[6:7], 0, v[16:17] ; D4E20006 00022080 | |
| v_cndmask_b32_e64 v14, v18, -1, s[8:9] ; D501000E 00218312 | |
| v_cndmask_b32_e64 v15, v19, -1, s[8:9] ; D501000F 00218313 | |
| v_cmp_eq_u64_e64 s[8:9], 0, v[22:23] ; D4E20008 00022C80 | |
| v_cndmask_b32_e64 v16, v21, -1, s[10:11] ; D5010010 00298315 | |
| v_cndmask_b32_e64 v18, v20, -1, s[10:11] ; D5010012 00298314 | |
| v_cndmask_b32_e64 v52, v60, -1, s[16:17] ; D5010034 0041833C | |
| v_cndmask_b32_e64 v15, -1, v15, s[6:7] ; D501000F 001A1EC1 | |
| v_cndmask_b32_e64 v14, -1, v14, s[6:7] ; D501000E 001A1CC1 | |
| v_add_co_u32 v4, s[6:7], v4, s46 ; D70F0604 00005D04 | |
| v_cndmask_b32_e64 v17, -1, v16, s[8:9] ; D5010011 002220C1 | |
| v_cndmask_b32_e64 v16, -1, v18, s[8:9] ; D5010010 002224C1 | |
| v_add_co_ci_u32_e64 v5, s[6:7], s47, v5, s[6:7] ; D5280605 001A0A2F | |
| v_cndmask_b32_e64 v9, -1, v9, s[4:5] ; D5010009 001212C1 | |
| v_cndmask_b32_e64 v8, -1, v8, s[4:5] ; D5010008 001210C1 | |
| v_cndmask_b32_e64 v3, -1, v3, s[2:3] ; D5010003 000A06C1 | |
| v_cndmask_b32_e64 v2, -1, v2, s[2:3] ; D5010002 000A04C1 | |
| v_cndmask_b32_e64 v51, -1, v55, s[12:13] ; D5010033 00326EC1 | |
| v_cndmask_b32_e64 v55, -1, v79, s[14:15] ; D5010037 003A9EC1 | |
| v_cndmask_b32_e64 v56, -1, v52, s[0:1] ; D5010038 000268C1 | |
| v_cndmask_b32_e32 v52, -1, v78, vcc ; 02689CC1 | |
| global_store_dwordx4 v[4:5], v[14:17], off offset:112 ; DC788070 007D0E04 | |
| global_store_dwordx4 v[4:5], v[6:9], off offset:96 ; DC788060 007D0604 | |
| global_store_dwordx4 v[4:5], v[0:3], off offset:80 ; DC788050 007D0004 | |
| global_store_dwordx4 v[4:5], v[54:57], off offset:64 ; DC788040 007D3604 | |
| global_store_dwordx4 v[4:5], v[50:53], off offset:48 ; DC788030 007D3204 | |
| global_store_dwordx4 v[4:5], v[46:49], off offset:32 ; DC788020 007D2E04 | |
| global_store_dwordx4 v[4:5], v[42:45], off offset:16 ; DC788010 007D2A04 | |
| global_store_dwordx4 v[4:5], v[10:13], off ; DC788000 007D0A04 | |
| s_endpgm ; BF810000 | |
| *** SHADER STATS *** | |
| SGPRS: 56 | |
| VGPRS: 140 | |
| Spilled SGPRs: 0 | |
| Spilled VGPRs: 0 | |
| Private memory VGPRs: 0 | |
| Code Size: 3640 bytes | |
| LDS: 0 bytes | |
| Scratch: 0 bytes per wave | |
| Max Waves: 3 | |
| ******************** | |
| ERROR: Data sample 0:0 does not validate! Expected (0xffffffffffffffff), got (0x0000000000000000), sources (0xb716a67597c4aa2f, 0x7363148f18a84601, 0x85fcf4c74af01599) | |
| Vector ulong16,ulong16,ulong16 FAILED | |
| integer_mad_sat FAILED | |
| PASSED sub-test. | |
| FAILED test. |
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