2021-05-09 by kbeckmann
These are my notes of how I interpret how the clock tree works in Caravel. It might be inaccurate.
caravel:
from nmigen import * | |
from nmigen.build import * | |
from nmigen_boards.tang_nano import TangNanoPlatform | |
class Blinky(Elaboratable): | |
def elaborate(self, platform): | |
m = Module() | |
platform.add_resources([ |
from nmigen import * | |
from enum import IntEnum | |
from nmigen.utils import bits_for | |
class AccessFlags(IntEnum): | |
R = 1 << 0 | |
W = 1 << 1 | |
RW = R | W |
from nmigen import * | |
from nmigen._toolchain.yosys import * | |
from nmigen.back.cxxrtl import rtlil | |
import os, subprocess | |
def _convert_rtlil_text(rtlil_text, black_boxes, verilog_boxes, *, src_loc_at=0): | |
if black_boxes is not None: | |
if not isinstance(black_boxes, dict): | |
raise TypeError("CXXRTL black boxes must be a dictionary, not {!r}" |
Program terminated with signal SIGSEGV, Segmentation fault. | |
#0 0x0000561db819718a in std::vector<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t, std::allocator<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t> >::size (this=<optimized out>) | |
at /usr/include/c++/10.2.0/bits/stl_vector.h:919 | |
919 { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); } | |
(gdb) bt | |
#0 0x0000561db819718a in std::vector<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t, std::allocator<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t> >::size (this=<optimized out>) | |
at /usr/include/c++/10.2.0/bits/stl_vector.h:919 | |
#1 Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ |