Trying to instantiate a 2F PLL -- doesn't work.

gistfile1.txt

`default_nettype none

`define W 24

module top (
        input  CLK,
        output LED1,
        output LED2,
        output LED3,
        output LED4,
        output LED5,
        output P1A1,
        output P1A2,
        output P1A3,
        output P1A4
    );

    wire pll_clk60, pll_clk30, pll_locked;

    SB_PLL40_2F_PAD #(
            .FEEDBACK_PATH("SIMPLE"),
            // .PLLOUT_SELECT_PORTA("GENCLK"),
            .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
            .DIVR(4'b0000),         // DIVR =  0
            .DIVF(7'b1001111),      // DIVF = 79
            .DIVQ(3'b100),          // DIVQ =  4
            .FILTER_RANGE(3'b001)   // FILTER_RANGE = 1
        ) pll (
            .PACKAGEPIN(CLK),
            .PLLOUTGLOBALA(pll_clk60),
            .PLLOUTGLOBALB(pll_clk30),
            .LOCK(pll_locked),
            .RESETB(1'b1),
            .BYPASS(1'b0),
            .LATCHINPUTVALUE(1'b0));

    // SB_PLL40_PAD #(
    //         .FEEDBACK_PATH("SIMPLE"),
    //         .DIVR(4'b0000),         // DIVR =  0
    //         .DIVF(7'b1001111),      // DIVF = 79
    //         .DIVQ(3'b101),          // DIVQ =  5
    //         .FILTER_RANGE(3'b001)   // FILTER_RANGE = 1
    //     ) the_pll (
    //         .PACKAGEPIN(CLK),
    //         .PLLOUTCORE(pll_clk30),
    //         .LOCK(pll_locked),
    //         .RESETB(1'b1),
    //         .BYPASS(1'b0));

    reg [`W:0] counter60, counter30p, counter30n, counter30;

    always @(posedge pll_clk30)
        if (pll_locked)
            counter30 <= counter30 + 1;

    always @(posedge pll_clk60)
        if (pll_locked) begin
            counter60 <= counter60 + 1;
            // if (pll_clk30)
            //     counter30p <= counter30p + 1;
            // else
            //     counter30n <= counter30n + 1;
        end

    assign LED1 = counter30[`W];
    assign LED2 = counter60[`W];
    // assign LED3 = counter30p[`W];
    // assign LED4 = counter30p[`W];
    assign LED5 = 0;
    assign P1A1 = counter30[`W];
    assign P1A2 = counter60[`W];
    assign P1A3 = pll_clk30;
    // assign P1A3 = counter30p[`W];
    // assign P1A4 = counter30p[`W];

endmodule